Lines Matching defs:imm
1142 unsigned imm = fieldFromInstruction(Val, 7, 5);
1164 if (Shift == ARM_AM::ror && imm == 0)
1167 unsigned Op = Shift | (imm << 3);
1328 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1415 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1416 Inst.addOperand(MCOperand::createImm(imm));
1434 imm |= U << 8;
1439 Inst.addOperand(MCOperand::createImm(imm));
1478 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1563 Inst.addOperand(MCOperand::createImm(imm));
1566 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1583 unsigned imm = fieldFromInstruction(Val, 7, 5);
1602 if (ShOp == ARM_AM::ror && imm == 0)
1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1628 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1798 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2056 int imm = fieldFromInstruction(Insn, 0, 8);
2058 if(imm > 4) return MCDisassembler::Fail;
2060 Inst.addOperand(MCOperand::createImm(imm));
2071 unsigned imm = 0;
2073 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2074 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2075 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2076 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2084 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2085 Inst.addOperand(MCOperand::createImm(imm));
2096 unsigned imm = 0;
2098 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2099 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2108 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2109 Inst.addOperand(MCOperand::createImm(imm));
2170 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2189 Inst.addOperand(MCOperand::createImm(Imm));
2199 unsigned imm = fieldFromInstruction(Val, 0, 12);
2205 if (!add) imm *= -1;
2206 if (imm == 0 && !add) imm = INT32_MIN;
2207 Inst.addOperand(MCOperand::createImm(imm));
2209 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2219 // U == 1 to add imm, 0 to subtract it.
2221 unsigned imm = fieldFromInstruction(Val, 0, 8);
2227 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2229 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2239 // U == 1 to add imm, 0 to subtract it.
2241 unsigned imm = fieldFromInstruction(Val, 0, 8);
2247 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2249 imm)));
2292 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2296 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2297 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2299 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2303 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2305 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
3115 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3116 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3117 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3118 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3119 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3130 Inst.addOperand(MCOperand::createImm(imm));
3238 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3253 Inst.addOperand(MCOperand::createImm(imm));
3301 unsigned imm = fieldFromInstruction(Val, 3, 5);
3305 Inst.addOperand(MCOperand::createImm(imm));
3312 unsigned imm = Val << 2;
3314 Inst.addOperand(MCOperand::createImm(imm));
3315 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3334 unsigned imm = fieldFromInstruction(Val, 0, 2);
3351 Inst.addOperand(MCOperand::createImm(imm));
3445 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3446 imm |= (U << 8);
3447 imm |= (Rn << 9);
3517 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3528 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3529 imm |= (Rn << 13);
3597 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3608 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3609 imm |= (Rn << 9);
3636 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3647 int imm = fieldFromInstruction(Insn, 0, 12);
3684 if (imm == 0)
3685 imm = INT32_MIN;
3687 imm = -imm;
3689 Inst.addOperand(MCOperand::createImm(imm));
3699 int imm = Val & 0xFF;
3701 if (!(Val & 0x100)) imm *= -1;
3702 Inst.addOperand(MCOperand::createImm(imm * 4));
3713 unsigned imm = fieldFromInstruction(Val, 0, 9);
3717 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3728 unsigned imm = fieldFromInstruction(Val, 0, 8);
3733 Inst.addOperand(MCOperand::createImm(imm));
3740 int imm = Val & 0xFF;
3742 imm = INT32_MIN;
3744 imm *= -1;
3745 Inst.addOperand(MCOperand::createImm(imm));
3756 unsigned imm = fieldFromInstruction(Val, 0, 9);
3783 imm |= 0x100;
3791 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3863 unsigned imm = fieldFromInstruction(Val, 0, 12);
3878 Inst.addOperand(MCOperand::createImm(imm));
3886 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3890 Inst.addOperand(MCOperand::createImm(imm));
4021 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4022 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4047 unsigned imm = fieldFromInstruction(Val, 0, 8);
4050 Inst.addOperand(MCOperand::createImm(imm));
4053 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4056 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4059 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4060 (imm << 8) | imm));
4066 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4067 Inst.addOperand(MCOperand::createImm(imm));
4279 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4280 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4281 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4290 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4304 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4305 imm
4306 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4317 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4332 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4333 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4334 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4343 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4357 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4358 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4359 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4368 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
5133 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5139 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5140 if (!(imm & 0x38)) {
5171 if (!(imm & 0x20)) return MCDisassembler::Fail;
5177 Inst.addOperand(MCOperand::createImm(64 - imm));
5192 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5198 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5199 if (!(imm & 0x38)) {
5230 if (!(imm & 0x20)) return MCDisassembler::Fail;
5236 Inst.addOperand(MCOperand::createImm(64 - imm));
