Lines Matching full:_dst_
339 : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
341 "$src1 = $_dst_">;
405 : V6_STInst <(outs IntRegs:$_dst_),
408 "$src1 = $_dst_">, NewValueRel {
448 : V6_STInst <(outs IntRegs:$_dst_),
451 "$src1 = $_dst_">, NewValueRel {
482 : V6_STInst<(outs IntRegs:$_dst_),
486 "$src2 = $_dst_">, NewValueRel {
545 : V6_STInst <(outs IntRegs:$_dst_),
549 "$src2 = $_dst_">;
586 : V6_STInst <(outs IntRegs:$_dst_),
590 "$src2 = $_dst_"> , NewValueRel {
632 : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_),
634 "$src1 = $_dst_">, NewValueRel;
666 : V6_STInst <(outs IntRegs:$_dst_),
669 "$src1 = $_dst_">, NewValueRel;
688 : V6_STInst <(outs IntRegs:$_dst_),
691 "$src1 = $_dst_">, NewValueRel;
704 : V6_STInst<(outs IntRegs:$_dst_),
708 "$src2 = $_dst_">, NewValueRel {
736 : V6_STInst <(outs IntRegs:$_dst_),
740 "$src2 = $_dst_">, NewValueRel;
755 : V6_STInst <(outs IntRegs:$_dst_),
759 "$src2 = $_dst_">, NewValueRel {
