Lines Matching full:shiftreg
1231 unsigned ShiftReg = RI.createVirtualRegister(RC);1247 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]1249 // ShiftReg2 = shift ShiftReg1251 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)1258 .addReg(ShiftReg);1266 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]