Lines Matching defs:Opcode
134 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1453 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
1454 return MipsInsts[Opcode];
1457 static bool hasShortDelaySlot(unsigned Opcode) {
1458 switch (Opcode) {
1518 const unsigned Opcode = Inst.getOpcode();
1521 switch (Opcode) {
1600 const unsigned Opcode = Inst.getOpcode();
1604 switch (Opcode) {
1618 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 ||
1619 Opcode == Mips::BBIT1 ? 63 : 31))
1622 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032
1642 // because the pseudo-instruction doesn't have a distinct opcode.
2092 const unsigned Opcode = Inst.getOpcode();
2094 if (Opcode == Mips::JalOneReg) {
2107 } else if (Opcode == Mips::JalTwoReg) {
2598 unsigned OpCode = 0;
2601 OpCode = Mips::BNE;
2604 OpCode = Mips::BEQ;
2613 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
2626 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
2730 unsigned Opcode = Inst.getOpcode();
2731 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;
2745 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6;
2747 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
2781 llvm_unreachable("unknown opcode for branch pseudo-instruction");
2883 llvm_unreachable("unknown opcode for branch pseudo-instruction");
2889 // FIXME: All of these Opcode-specific if's are needed for compatibility
3420 llvm_unreachable("unexpected instruction opcode");
3486 llvm_unreachable("unexpected instruction opcode");
3549 llvm_unreachable("unexpected instruction opcode");
3626 llvm_unreachable("unexpected instruction opcode");
3755 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
