Lines Matching refs:Cond
73 SmallVectorImpl<MachineOperand> &Cond) const {
80 Cond.push_back(MachineOperand::CreateImm(Opc));
83 Cond.push_back(Inst->getOperand(i));
89 SmallVectorImpl<MachineOperand> &Cond,
92 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
99 ArrayRef<MachineOperand> Cond) const {
100 unsigned Opc = Cond[0].getImm();
104 for (unsigned i = 1; i < Cond.size(); ++i) {
105 if (Cond[i].isReg())
106 MIB.addReg(Cond[i].getReg());
107 else if (Cond[i].isImm())
108 MIB.addImm(Cond[i].getImm());
118 ArrayRef<MachineOperand> Cond,
128 assert((Cond.size() <= 3) &&
133 BuildCondBr(MBB, TBB, DL, Cond);
140 if (Cond.empty())
143 BuildCondBr(MBB, TBB, DL, Cond);
172 SmallVectorImpl<MachineOperand> &Cond) const {
173 assert( (Cond.size() && Cond.size() <= 3) &&
175 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
181 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
227 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
256 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
