Lines Matching defs:Opcode
111 /// rotate and mask opcode and mask operation.
183 /// Reg in an asm, because the load or store opcode would have to change.
449 // opcode and that it has a immediate integer right operand.
479 unsigned Opcode = N->getOpcode();
484 if (Opcode == ISD::SHL) {
489 } else if (Opcode == ISD::SRL) {
496 } else if (Opcode == ISD::ROTL) {
2515 unsigned Opcode;
2522 case MVT::f64: Opcode = PPC::LFDU; break;
2523 case MVT::f32: Opcode = PPC::LFSU; break;
2524 case MVT::i32: Opcode = PPC::LWZU; break;
2525 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2527 case MVT::i8: Opcode = PPC::LBZU; break;
2534 case MVT::i64: Opcode = PPC::LDU; break;
2535 case MVT::i32: Opcode = PPC::LWZU8; break;
2536 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2538 case MVT::i8: Opcode = PPC::LBZU8; break;
2546 Opcode, dl, LD->getValueType(0),
2552 unsigned Opcode;
2559 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
2560 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
2561 case MVT::f64: Opcode = PPC::LFDUX; break;
2562 case MVT::f32: Opcode = PPC::LFSUX; break;
2563 case MVT::i32: Opcode = PPC::LWZUX; break;
2564 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2566 case MVT::i8: Opcode = PPC::LBZUX; break;
2574 case MVT::i64: Opcode = PPC::LDUX; break;
2575 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2576 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2578 case MVT::i8: Opcode = PPC::LBZUX8; break;
2586 Opcode, dl, LD->getValueType(0),
2749 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2750 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
3544 unsigned Opcode = MachineNode->getMachineOpcode();
3545 switch (Opcode) {
3594 switch (Opcode) {
3914 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
4331 // inferred from the opcode; when we process it in the AsmPrinter,
