Lines Matching full:v2i64
108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
309 if (VT != MVT::v2i64)
345 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
346 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
347 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
348 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
828 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
849 // bitcast to v2i64 and then extract first element.
852 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
916 case MVT::v2i64:
2294 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2295 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
3981 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
3986 return DAG.getUNDEF(MVT::v2i64);
3997 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
4153 // The best way of building a v2i64 from two i64s is to use VLVGP.
4154 if (VT == MVT::v2i64)
4179 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
4180 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
4182 DL, MVT::v2i64, Op01, Op23);
