Lines Matching defs:Opcode
50 // each having the opcode given by NewOpcode.
147 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
149 MI.setDesc(get(Opcode));
204 unsigned Opcode;
208 Opcode = SystemZ::RISBHH;
210 Opcode = SystemZ::RISBHL;
212 Opcode = SystemZ::RISBLH;
219 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
457 // Return true if MI is a shift of type Opcode by Imm bits.
458 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
459 return (MI->getOpcode() == Opcode &&
523 // If Opcode is a move that has a conditional variant, return that variant,
525 static unsigned getConditionalMove(unsigned Opcode) {
526 switch (Opcode) {
533 static unsigned getConditionalLoadImmediate(unsigned Opcode) {
534 switch (Opcode) {
542 unsigned Opcode = MI.getOpcode();
543 if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
545 if (STI.hasLoadStoreOnCond2() && getConditionalLoadImmediate(Opcode))
547 if (Opcode == SystemZ::Return ||
548 Opcode == SystemZ::Trap ||
549 Opcode == SystemZ::CallJG ||
550 Opcode == SystemZ::CallBR)
597 unsigned Opcode = MI.getOpcode();
599 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
609 if (unsigned CondOpcode = getConditionalLoadImmediate(Opcode)) {
618 if (Opcode == SystemZ::Trap) {
625 if (Opcode == SystemZ::Return) {
632 if (Opcode == SystemZ::CallJG) {
645 if (Opcode == SystemZ::CallBR) {
677 unsigned Opcode;
679 Opcode = SystemZ::LGR;
682 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
684 Opcode = SystemZ::LDR;
686 Opcode = SystemZ::LXR;
688 Opcode = SystemZ::VLR32;
690 Opcode = SystemZ::VLR64;
692 Opcode = SystemZ::VLR;
696 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
750 static LogicOp interpretAndImmediate(unsigned Opcode) {
751 switch (Opcode) {
796 unsigned Opcode = MI.getOpcode();
811 if (Opcode == SystemZ::AHIMux &&
819 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
839 if (LogicOp And = interpretAndImmediate(Opcode)) {
880 unsigned Opcode = MI.getOpcode();
883 if (LIS != nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
920 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
923 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
925 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
933 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
934 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
935 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1003 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1249 llvm_unreachable("Unrecognized branch opcode");
1296 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1298 const MCInstrDesc &MCID = get(Opcode);
1302 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1308 return Opcode;
1312 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1316 // Check whether Opcode allows signed 20-bit displacements.
1318 return Opcode;
1323 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1324 switch (Opcode) {
1393 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1396 switch (Opcode) {
1409 switch (Opcode) {
1430 switch (Opcode) {
1451 switch (Opcode) {
1472 switch (Opcode) {
1500 unsigned Opcode;
1502 Opcode = SystemZ::LGHI;
1504 Opcode = SystemZ::LLILL;
1506 Opcode = SystemZ::LLILH;
1510 Opcode = SystemZ::LGFI;
1512 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
