Lines Matching defs:Copy
636 // Note: This is fine to do a copy from FR32 to FR128, this is the
1235 // Make the copy.
1238 // Avoid a cross-class copy. This is very unlikely.
1242 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
1248 // Swift calling convention does not require we copy the sret argument
1251 // All x86 ABIs require that for returning structs by value we copy
1254 // so now we copy the value out and into %rax/%eax.
1261 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
1753 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1775 const static unsigned Copy = TargetOpcode::COPY;
1809 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
1810 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
1811 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1812 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
1816 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
1817 { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem
1818 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
1819 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
1823 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1824 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem
1825 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
1826 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem
1877 // Copy the zero into the appropriate sub/super/identical physical
1882 TII.get(Copy), TypeEntry.HighInReg)
1886 TII.get(Copy), TypeEntry.HighInReg)
1899 // up with bogus copies like %R9B = COPY %AH. Reference AX
1913 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1923 // Copy the result out of the physreg if we haven't already.
1926 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg)
2145 TII.get(TargetOpcode::COPY), ResultReg).addReg(VBlendReg);
2247 TII.get(TargetOpcode::COPY), ResultReg)
2377 // First issue a copy to GR16_ABCD or GR32_ABCD.
2382 TII.get(TargetOpcode::COPY), CopyReg).addReg(InputReg);
2495 // Emit an explicit copy from register class VR128 to register class FR32.
2498 TII.get(TargetOpcode::COPY), ResultReg)
2536 // Always make a copy of the frame register to to a vreg first, so that we
2541 TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
2786 // First copy the first operand into RAX, which is an implicit input to
2789 TII.get(TargetOpcode::COPY), Reg[VT.SimpleTy-MVT::i8])
2797 Copy the first operand into AL, which is an implicit input to the
2800 TII.get(TargetOpcode::COPY), X86::AL)
2975 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
2980 TII.get(TargetOpcode::COPY), ResultReg)
3214 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3256 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
3351 // Copy all of the result registers out of their specified physreg.
3364 // If we prefer to use the value in xmm registers, copy it out as f80 and
3372 // Copy out the result.
3374 TII.get(TargetOpcode::COPY), CopyReg).addReg(VA.getLocReg());
