Lines Matching defs:Opcode
356 // Get opcode and regclass of the output for the given load instruction.
509 // Get opcode and regclass of the output for the given store instruction.
693 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
819 unsigned Opcode = Instruction::UserOp1;
826 Opcode = I->getOpcode();
830 Opcode = C->getOpcode();
840 switch (Opcode) {
978 unsigned Opcode = Instruction::UserOp1;
1005 Opcode = I->getOpcode();
1009 Opcode = C->getOpcode();
1013 switch (Opcode) {
1347 /// opcode that works for the compare (e.g. CMP32ri) otherwise return 0.
1792 unsigned OpDivRem; // The specific DIV/IDIV opcode to use.
1793 unsigned OpSignExtend; // Opcode for sign-extending lowreg into
1795 unsigned OpCopy; // Opcode for copying dividend into lowreg, or
1848 default: llvm_unreachable("Unexpected div/rem opcode");
2286 unsigned Opcode;
2290 Opcode = X86::VCVTSI2SDrr;
2294 Opcode = X86::VCVTSI2SSrr;
2303 fastEmitInst_rr(Opcode, RC, ImplicitDefReg, true, OpReg, false);
3544 // Get opcode and regclass of the output for the given load instruction.
3698 // Get opcode and regclass for the given zero.
