Lines Matching defs:Add
290 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
1032 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1157 setOperationAction(ISD::ADD, MVT::i1, Custom);
1251 // FIXME. This commands are available on SSE/AVX2, add relevant patterns.
1321 setOperationAction(ISD::ADD, MVT::v8i1, Expand);
1322 setOperationAction(ISD::ADD, MVT::v16i1, Expand);
1419 setOperationAction(ISD::ADD, MVT::v32i1, Expand);
1420 setOperationAction(ISD::ADD, MVT::v64i1, Expand);
1516 // FIXME. This commands are available on SSE/AVX2, add relevant patterns.
1527 setOperationAction(ISD::ADD, MVT::v2i1, Expand);
1528 setOperationAction(ISD::ADD, MVT::v4i1, Expand);
1583 // Add/Sub/Mul with overflow operations are custom lowered.
1642 setTargetDAGCombine(ISD::ADD);
2212 // Add the flag if we have it.
2752 // Get to the caller-allocated home save location. Add 8 to account
2776 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2878 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2901 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3262 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3317 // Add a wrapper.
3320 // Add extra indirection
3357 // Add argument registers to the end of the list so that they are known live
3363 // Add a register mask operand representing the call-preserved registers.
3389 //// If this is the first return lowered for this function, add the regs
3482 // Number smaller than 12 so just add the difference.
3485 // Mask out lower bits, add stackalignment once plus the 12 bytes.
5073 // If we didn't already add operands in the opcode-specific code, default to
5537 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
6108 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6109 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6125 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6198 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6322 // We found a valid add/sub node. Update the information accordingly.
6340 // Make sure that operands in input to each add/sub node always
6367 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6402 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6413 // Try to match an AVX horizontal add/sub of packed single/double
6428 // Try to match an AVX2 horizontal add/sub of signed integers.
6433 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6434 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6447 // Fold this build_vector into a single horizontal add/sub.
6453 // add/sub if we can emit a pair of scalar add/sub.
6469 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6480 // Don't try to expand this build_vector into a pair of horizontal add/sub
6481 // if we can simply emit a pair of scalar add/sub.
6485 // Convert this build_vector into two horizontal add/sub followed by
6515 // TODO: We may be able to add support for other Ops (ADD/SUB + shifts).
8356 // FIXME: Add support for scalar truncation where possible.
12812 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12830 DAG.getNode(ISD::ADD, DL, PtrVT,
12840 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12858 DAG.getNode(ISD::ADD, DL, PtrVT,
12868 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12888 DAG.getNode(ISD::ADD, DL, PtrVT,
12922 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12955 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12969 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
13070 // Add x@dtpoff with the base.
13071 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13115 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13125 // The address of the thread local variable is the add of the thread
13127 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13166 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13181 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
13261 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
13273 // The address of the thread local variable is the add of the thread
13275 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
13743 // For i64 source, we need to add the appropriate power of 2 if the input
13774 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
13784 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13785 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
13870 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
14638 case ISD::ADD:
14678 case ISD::ADD:
14693 case ISD::ADD:
14694 // Due to an isel shortcoming, be conservative if this add is likely to be
14697 // uses of other nodes in the match, such as the ADD in this case. This
14698 // leads to the ADD being left around and reselected, with the result being
14713 // An add of one will be selected as an INC.
14720 // An add of negative one (subtract of one) will be selected as a DEC.
14728 // Otherwise use a regular EFLAGS-setting add.
14729 Opcode = X86ISD::ADD;
14798 case X86ISD::ADD:
14823 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14926 // TODO: Add support for AVX512 (v16f32).
14958 // TODO: Add support for AVX512 (v16f32).
15682 (Opc == X86ISD::ADD ||
15913 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15914 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15980 // branch during isel and doesn't add any extensions.
16218 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
16303 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
16466 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16541 // Check for setcc([su]{add,sub,mul}o == 0).
16560 else if (Cond.getOpcode() == X86ISD::ADD ||
16610 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16613 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16619 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16930 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
16938 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
17337 return DAG.getNode(ISD::ADD, dl, PtrVT, EntryEBP, ParentFrameOffset);
17374 // We allways add rounding mode to the Node.
17375 // If the rounding mode is not specified, we add the
17397 // We add rounding mode to the Node when
18296 // the ECX register. Add 'ecx' explicitly to the chain.
18478 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
18575 DAG.getNode(ISD::ADD, dl, PtrVT,
18700 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
18703 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
18778 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
18787 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
18793 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
18801 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
18808 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
18865 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
18877 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
18884 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
18890 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
18959 DAG.getNode(ISD::ADD, DL, MVT::i16,
19050 // If the hi input nibble is zero then we add both results together, otherwise
19052 // add).
19065 SDValue Res = DAG.getNode(ISD::ADD, DL, CurrVT, Lo, Hi);
19069 // If the upper half of the input element is zero then add the halves'
19085 // NextVT. Mask the lower result to zero if HiZ is true and add the results
19091 Res = DAG.getNode(ISD::ADD, DL, NextVT, R0, R1);
19442 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
19443 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
19697 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
19815 // Simple i8 add case
19817 return DAG.getNode(ISD::ADD, dl, VT, R, R);
20102 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
20264 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
20271 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
20301 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
20302 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
20313 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
20314 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
20410 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
20417 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
20424 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
20474 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
20494 BaseOp = X86ISD::ADD;
20498 BaseOp = X86ISD::ADD;
20606 case AtomicRMWInst::Add:
20613 // If the atomicrmw's result isn't actually used, we can just add a "lock"
20845 // PSADBW instruction horizontally add all bytes and leave the result in i64
20890 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
20938 // LUT. After counting low and high nibbles, add the vector to obtain the
20944 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
20999 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
21003 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
21004 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
21227 "Used AtomicRMW ops other than Add should have been expanded!");
21277 case ISD::ADDC: Opc = X86ISD::ADD; break;
21479 // The mask is killed by scatter, add it to the values
21756 case ISD::ADD: return LowerADD(Op, DAG);
22202 case X86ISD::ADD: return "X86ISD::ADD";
22895 // Add the offset to the reg_save_area to get the final address.
23017 // Now add the instructions.
23190 // Without this, we would add a PHI between the two jumps, which ends up
23314 // Add the true and fallthrough blocks as its successors.
23384 // Add this PHI to the rewrite table.
23512 // Add code to the main basic block to check if the stack limit has been hit,
24073 // Add a register mask with no preserved registers. This results in all
24112 // Add the jump table entries as successors to the MBB.
24617 case X86ISD::ADD:
25152 // TODO - add 16i16 support (requires lane duplication).
25981 /// \brief Try to combine a shuffle into a target-specific add-sub node.
26091 case ISD::ADD :
26409 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
26652 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
26666 case 1: // result = add base, cond
26693 // Add the base if non-zero.
26695 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
26774 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
26905 // TODO: Add other opcodes eventually lowered into BLEND.
26948 // (icmp slt x, 0) -> (icmp sle (add x, 1), 0)
26949 // (icmp sge x, 0) -> (icmp sgt (add x, 1), 0)
27259 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
27277 case 1: // result = add base, cond
27301 // Add the base if non-zero.
27303 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
27638 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
27641 // is an add.
27664 // (mul x, 2^N + 1) => (add (shl x, N), x)
27665 NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
27679 // Do not add new nodes to DAG combiner worklist.
27729 // vector operations in many cases. Also, on sandybridge ADD is faster than
27731 // (shl V, 1) -> add V,V
27736 // hardware support for this operation. This is better expressed as an ADD
27739 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
28365 // (add (xor X, M), (and M, 1))
28515 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
28518 N0.getOpcode() == ISD::ADD &&
28697 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
28698 // %4 = add nuw nsw <N x i32> %3, %2
28729 if (LHS.getOpcode() != ISD::ADD)
28751 if (Operands[0].getOpcode() == ISD::ADD)
28753 else if (Operands[1].getOpcode() != ISD::ADD)
29459 "Unsupported vector type for horizontal add/sub");
29461 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
29561 // Try to synthesize horizontal add/sub from adds/subs of shuffles.
29992 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
29993 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
29995 /// eliminate extend, add, and shift instructions.
30003 // We need an 'add nsw' feeding into the 'sext'.
30004 SDValue Add = Sext->getOperand(0);
30005 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
30008 // Having a constant operand to the 'add' ensures that we are not increasing
30011 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
30015 // Don't make the 'add' bigger if there's no hope of combining it with some
30016 // other 'add' or 'shl' instruction.
30018 // of single 'add' instructions, but the cost model for selecting an LEA
30022 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
30030 // Everything looks good, so pull the 'sext' ahead of the 'add'.
30032 SDValue AddOp0 = Add.getOperand(0);
30034 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
30036 // The wider add is guaranteed to not wrap because both operands are
30040 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
30298 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
30305 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
30587 /// fold (add Y, (sete X, 0)) -> adc 0, Y
30588 /// (add Y, (setne X, 0)) -> sbb -1, Y
30657 // 7: %8 = add nsw <N x i32> %7, %vec.phi
30659 // The last instruction must be a reduction add. The instructions 3-6 forms an
30662 // The two operands of reduction add
30756 SDValue Res = DAG.getNode(ISD::ADD, DL, ResVT, Sad, SubPhi);
30760 return DAG.getNode(ISD::ADD, DL, VT, Sad, Phi);
30792 // immediate. Then add one to the LHS of the sub so we can turn
30801 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
30956 case ISD::ADD: return combineAdd(N, DAG, Subtarget);
31053 case ISD::ADD:
31100 case ISD::ADD:
31405 /// If it is invalid, don't add anything to Ops.
31534 } else if (Op.getOpcode() == ISD::ADD) {
