Lines Matching defs:Copy
2080 // Copy the result values into the output registers.
2122 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2152 // Swift calling convention does not require we copy the sret argument
2155 // All x86 ABIs require that for returning structs by value we copy
2158 // so now we copy the value out and into %rax/%eax.
2227 SDNode *Copy = *N->use_begin();
2228 if (Copy->getOpcode() == ISD::CopyToReg) {
2229 // If the copy has a glue operand, we conservatively assume it isn't safe to
2231 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2233 TCChain = Copy->getOperand(0);
2234 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2238 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2292 // Copy all of the result registers out of their specified physreg.
2303 // If we prefer to use the value in xmm registers, copy it out as f80 and
2377 /// Make a copy of an aggregate at address specified by "Src" to address
2379 /// parameter attribute. The copy will be passed as a byval function parameter.
2678 // Swift calling convention does not require we copy the sret argument
2683 // All x86 ABIs require that for returning structs by value we copy the
2694 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2695 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2838 // Copy all forwards from physical to virtual registers.
2881 // funclet needs a copy of this slot in its (mostly empty) frame, and the
3257 // Copy relative to framepointer.
3286 // Build a sequence of copy-to-reg nodes chained together with token chain
3287 // and flag operands which copy the outgoing args into registers.
3340 // Returns a chain & a flag for retval copy to use.
3423 // Returns a flag for retval copy to use.
8113 copy.
9312 // so prevents folding a load into this instruction or making a copy.
9950 // Make a copy of the mask so it can be modified.
10647 /// from a permuted copy of the vector. This lowering strategy results in four
12351 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
22589 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(TargetOpcode::COPY),
22627 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg())
22663 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg())
22676 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
22701 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg())
22721 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
22723 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
22935 // If we need to align it, do so. Otherwise, just copy the address
22951 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
23178 // copy of t1, and do that renaming, properly generating:
23299 // live into the sink and copy blocks.
23392 // Copy the PHI result to the register defined by the second CMOV.
23394 DL, TII->get(TargetOpcode::COPY),
23514 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
23524 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
23526 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
23563 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
24125 // Keep a copy of Successors since it's modified inside the loop.
29484 std::copy(Mask.begin(), Mask.end(), LMask.begin());
29502 std::copy(Mask.begin(), Mask.end(), RMask.begin());
31063 /// know that the code that lowers COPY of EFLAGS has to use the stack, and if
31908 // Create copy from CSR to a virtual register.
31917 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
31920 // Insert the copy-back instructions right before the terminator.
31923 TII->get(TargetOpcode::COPY), *I)
