Lines Matching defs:Opcode
2216 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2218 opcode = X86ISD::IRET;
2219 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
3531 unsigned Opcode = Def->getOpcode();
3532 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3533 Opcode == X86::LEA64_32r) &&
3790 static bool isTargetShuffle(unsigned Opcode) {
3791 switch(Opcode) {
3828 static bool isTargetShuffleVariableMask(unsigned Opcode) {
3829 switch (Opcode) {
4845 /// Calculates the shuffle mask corresponding to the target-specific opcode.
5073 // If we didn't already add operands in the opcode-specific code, default to
5202 unsigned Opcode = V.getOpcode();
5218 if (isTargetShuffle(Opcode)) {
5243 if (Opcode == ISD::BITCAST) {
6106 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6108 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6109 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6115 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6125 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6145 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6295 unsigned Opcode = Op.getOpcode();
6296 if (Opcode == ISD::UNDEF) {
6301 // Early exit if we found an unexpected opcode.
6302 if (Opcode != ExpectedOpcode)
6508 // Check that all elements have the same opcode.
6510 unsigned Opcode = Op.getOperand(0).getOpcode();
6512 if (Opcode != Op.getOperand(i).getOpcode())
6516 switch (Opcode) {
6522 if (!TLI.isOperationLegalOrPromote(Opcode, VT))
6541 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
7878 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7894 V = DAG.getNode(OpCode, DL, ShiftVT, V,
8549 unsigned Opcode = VT == MVT::v2f64 ? X86ISD::MOVDDUP : X86ISD::VBROADCAST;
8550 bool BroadcastFromReg = (Opcode == X86ISD::MOVDDUP) || Subtarget.hasAVX2();
8635 Opcode = (BroadcastVT.is128BitVector() ? X86ISD::MOVDDUP : Opcode);
8672 if (Opcode == X86ISD::MOVDDUP && !V.getValueType().isVector())
8690 return DAG.getBitcast(VT, DAG.getNode(Opcode, DL, BroadcastVT, V));
12717 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12743 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
14301 "Wrong opcode for lowering FABS or FNEG.");
14664 unsigned Opcode = 0;
14715 Opcode = X86ISD::INC;
14722 Opcode = X86ISD::DEC;
14729 Opcode = X86ISD::ADD;
14783 case ISD::SUB: Opcode = X86ISD::SUB; break;
14784 case ISD::XOR: Opcode = X86ISD::XOR; break;
14785 case ISD::AND: Opcode = X86ISD::AND; break;
14791 Opcode = X86ISD::OR;
14818 // Use a target machine opcode to prevent further DAGCombine
14840 if (Opcode == 0) {
14852 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
15675 /// Return true if opcode is a X86 logical comparison.
17065 default: llvm_unreachable("Unknown opcode!");
17124 // Change opcode to non-immediate version
17398 // - RM Opcode is specified and
18045 unsigned Opcode;
18050 Opcode = X86ISD::PCMPISTRI;
18054 Opcode = X86ISD::PCMPESTRI;
18058 Opcode = X86ISD::PCMPISTRI;
18062 Opcode = X86ISD::PCMPESTRI;
18066 Opcode = X86ISD::PCMPISTRI;
18070 Opcode = X86ISD::PCMPESTRI;
18074 Opcode = X86ISD::PCMPISTRI;
18078 Opcode = X86ISD::PCMPESTRI;
18082 Opcode = X86ISD::PCMPISTRI;
18086 Opcode = X86ISD::PCMPESTRI;
18092 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
18101 unsigned Opcode;
18103 Opcode = X86ISD::PCMPISTRI;
18105 Opcode = X86ISD::PCMPESTRI;
18109 return DAG.getNode(Opcode, dl, VTs, NewOps);
18270 static void getReadTimeStampCounter(SDNode *N, const SDLoc &DL, unsigned Opcode,
18275 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
18292 if (Opcode == X86ISD::RDTSCP_DAG) {
18441 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
18447 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain,
18763 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
18764 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
18772 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
18774 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
18786 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
18789 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
18800 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
18803 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
18869 // This is storing the opcode for MOV32ri.
18870 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
18883 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
19466 unsigned Opcode = Op.getOpcode();
19467 unsigned ExShift = (ISD::MULHU == Opcode ? ISD::SRL : ISD::SRA);
19468 unsigned ExSSE41 = (ISD::MULHU == Opcode ? X86ISD::VZEXT : X86ISD::VSEXT);
19620 unsigned Opcode = Op.getOpcode();
19627 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(HalfVT, HalfVT), Lo0, Lo1);
19628 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(HalfVT, HalfVT), Hi0, Hi1);
19663 unsigned Opcode =
19667 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
19670 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
19707 // Return true if the required (according to Opcode) shift-imm form is natively
19710 unsigned Opcode) {
19723 return (Opcode == ISD::SRA) ? AShift : LShift;
19730 unsigned Opcode) {
19731 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
19734 // Return true if the required (according to Opcode) variable-shift form is
19737 unsigned Opcode) {
19751 return (Opcode == ISD::SRA) ? AShift : LShift;
19861 llvm_unreachable("Unknown shift opcode.");
20970 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
20973 return DAG.getNode(OpCode, DL, VT, V, ShifterV);
21193 llvm_unreachable("Unknown ATOMIC_LOAD_ opcode");
21987 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_SAVE_RBX_DAG
21995 Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
21997 unsigned Opcode =
22004 Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
22075 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
22076 switch ((X86ISD::NodeType)Opcode) {
22604 default: llvm_unreachable("illegal opcode!");
22640 default: llvm_unreachable("illegal opcode!");
23097 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
23139 // true/false values to select between, and a branch opcode to use.
24460 // Get the X86 opcode to use.
24463 default: llvm_unreachable("illegal opcode!");
26082 unsigned Opcode = BC0.getOpcode();
26087 TLI.isOperationLegal(Opcode, VT)) {
26089 switch (Opcode) {
26457 unsigned Opcode = 0;
26473 Opcode = X86ISD::FMIN;
26481 Opcode = X86ISD::FMIN;
26490 Opcode = X86ISD::FMIN;
26499 Opcode = X86ISD::FMAX;
26511 Opcode = X86ISD::FMAX;
26520 Opcode = X86ISD::FMAX;
26538 Opcode = X86ISD::FMIN;
26545 Opcode = X86ISD::FMIN;
26554 Opcode = X86ISD::FMIN;
26561 Opcode = X86ISD::FMAX;
26573 Opcode = X86ISD::FMAX;
26582 Opcode = X86ISD::FMAX;
26587 if (Opcode)
26588 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
27854 unsigned opcode;
27858 if (Subtarget.hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
28057 unsigned Opcode = N->getOpcode();
28058 switch (Opcode) {
28072 llvm_unreachable("Unexpected opcode");
29559 assert((IsFadd || N->getOpcode() == ISD::FSUB) && "Wrong opcode");
29831 default: llvm_unreachable("unknown opcode");
30076 unsigned Opcode = N->getOpcode();
30077 if (Opcode != ISD::SIGN_EXTEND && Opcode != ISD::ZERO_EXTEND)
30123 SDValue SExt = DAG.getNode(Opcode, DL, ExVT, Ex);
30134 return Opcode == ISD::SIGN_EXTEND
30152 SrcVec = Opcode == ISD::SIGN_EXTEND
30227 unsigned Opcode;
30229 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
30231 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
30233 return DAG.getNode(Opcode, dl, VT, A, B, C);
