Lines Matching refs:v4i64
934 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
942 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
953 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
991 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
994 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
997 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1000 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1003 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1011 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1016 // ISD::CTLZ v8i32/v4i64 - scalarization is faster without AVX2
1022 for (auto VT : { MVT::v8i32, MVT::v4i64 })
1031 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1036 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1057 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom);
1068 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1070 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1071 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1075 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1077 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1078 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1083 for (auto VT : { MVT::v8i32, MVT::v4i64 }) {
1089 v4i64,
1103 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1118 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1120 setOperationPromotedToType(ISD::AND, VT, MVT::v4i64);
1121 setOperationPromotedToType(ISD::OR, VT, MVT::v4i64);
1122 setOperationPromotedToType(ISD::XOR, VT, MVT::v4i64);
1123 setOperationPromotedToType(ISD::LOAD, VT, MVT::v4i64);
1124 setOperationPromotedToType(ISD::SELECT, VT, MVT::v4i64);
1160 for (MVT VT : {MVT::v2i64, MVT::v4i32, MVT::v8i32, MVT::v4i64, MVT::v8i16,
1199 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1200 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1201 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1229 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1231 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1233 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1235 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1256 setLoadExtAction(ISD::EXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1257 setLoadExtAction(ISD::EXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1258 setLoadExtAction(ISD::EXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1354 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1359 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1365 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1374 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1379 for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
1387 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64,
1557 for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
1948 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
5846 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
7529 case MVT::v4i64:
8659 if (VT == MVT::v4f64 || VT == MVT::v4i64)
10951 if (VT == MVT::v4f64 || VT == MVT::v4i64)
11248 /// instruction set for v4i64 shuffling..
11253 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
11254 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
11256 assert(Subtarget.hasAVX2() && "We can only lower v4i64 with AVX2!");
11260 if (SDValue V = lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask,
11264 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
11269 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1, V2,
11277 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
11281 MVT::v4i64,
11289 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
11294 if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask,
11300 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
11310 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
11314 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
11694 case MVT::v4i64:
13994 // v4i32 -> v4i64
14002 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14148 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14149 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14189 In = DAG.getBitcast(MVT::v4i64, In);
14192 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14556 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
16126 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
16136 // v4i32 to v4i64
19404 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
19405 "Only know how to lower V2I64/V4I64/V8I64 multiply");
19425 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
19661 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
19722 (VT != MVT::v2i64 && VT != MVT::v4i64));
19750 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
19765 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
19777 if (VT == MVT::v4i64)
19789 if (VT == MVT::v4i64)
19805 if ((VT == MVT::v2i64 || (Subtarget.hasInt256() && VT == MVT::v4i64)) &&
19868 (VT == MVT::v2i64 || (Subtarget.hasInt256() && VT == MVT::v4i64))) {
20056 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) &&
20846 // chunks, thus directly computes the pop count for v2i64 and v4i64.
24712 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
24915 ShuffleVT = (FloatDomain ? MVT::v4f64 : MVT::v4i64);
25067 : MVT::v4i64);
25155 if (ShuffleVT == MVT::v4i64)
25162 else if (ShuffleVT == MVT::v4i64)
27807 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
27960 if (VT != MVT::v2i64 && VT != MVT::v4i64 &&
28304 if (!((VT == MVT::v2i64) || (VT == MVT::v4i64 && Subtarget.hasInt256())))
28406 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
28610 case MVT::v4i64: if (!Subtarget.hasAVX2()) return SDValue(); break;
29968 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
29971 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
29972 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
29973 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
29986 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
31722 case MVT::v4i64:
