Lines Matching full:v16i16
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
168 // On AVX2, a packed v16i16 shift left by a constant build_vector
194 { ISD::SHL, MVT::v16i16, 2 },
195 { ISD::SRL, MVT::v16i16, 4 },
196 { ISD::SRA, MVT::v16i16, 4 },
213 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
216 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
219 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
225 { ISD::SDIV, MVT::v16i16, 16*20 },
229 { ISD::UDIV, MVT::v16i16, 16*20 },
249 { ISD::SHL, MVT::v16i16, 2 }, // psllw.
258 { ISD::SRL, MVT::v16i16, 2 }, // psrlw.
267 { ISD::SRA, MVT::v16i16, 2 }, // psraw.
299 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a
301 if ((VT == MVT::v8i32 || VT == MVT::v16i16) &&
324 { ISD::SHL, MVT::v16i16, 2*32 }, // cmpgtb sequence.
333 { ISD::SRL, MVT::v16i16, 2*32 }, // cmpgtb sequence.
342 { ISD::SRA, MVT::v16i16, 2*32 }, // cmpgtb sequence.
373 { ISD::MUL, MVT::v16i16, 4 },
438 if (ST->hasAVX2() && LT.second == MVT::v16i16)
450 {ISD::VECTOR_SHUFFLE, MVT::v16i16, 5},
559 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 },
568 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
569 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
580 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
597 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
625 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
626 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
657 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
665 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
739 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
740 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
747 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
748 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
756 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
792 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
793 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
802 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
803 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
809 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
815 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 },
905 { ISD::SETCC, MVT::v16i16, 4 },
912 { ISD::SETCC, MVT::v16i16, 1 },
951 { ISD::BITREVERSE, MVT::v16i16, 4 },
965 { ISD::BITREVERSE, MVT::v16i16, 5 },
969 { ISD::BSWAP, MVT::v16i16, 1 }
974 { ISD::BITREVERSE, MVT::v16i16, 10 },
978 { ISD::BSWAP, MVT::v16i16, 4 }
