Lines Matching refs:v4i64
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
149 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
159 { ISD::SHL, MVT::v4i64, 1 },
160 { ISD::SRL, MVT::v4i64, 1 },
200 { ISD::SHL, MVT::v4i64, 2 },
201 { ISD::SRL, MVT::v4i64, 4 },
202 { ISD::SRA, MVT::v4i64, 4 },
221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
227 { ISD::SDIV, MVT::v4i64, 4*20 },
231 { ISD::UDIV, MVT::v4i64, 4*20 },
253 { ISD::SHL, MVT::v4i64, 2 }, // psllq.
262 { ISD::SRL, MVT::v4i64, 2 }, // psrlq.
271 { ISD::SRA, MVT::v4i64, 8 }, // 2 x psrad + shuffle.
328 { ISD::SHL, MVT::v4i64, 2*4 }, // splat+shuffle sequence.
337 { ISD::SRL, MVT::v4i64, 2*4 }, // splat+shuffle sequence.
346 { ISD::SRA, MVT::v4i64, 2*12 }, // srl/xor/sub sequence.
377 { ISD::SUB, MVT::v4i64, 4 },
378 { ISD::ADD, MVT::v4i64, 4 },
379 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
381 // Because we believe v4i64 to be a legal type, we must also include the
384 { ISD::MUL, MVT::v4i64, 18 },
397 // A v2i64/v4i64 and multiply is custom lowered as a series of long
400 { ISD::MUL, MVT::v4i64, 9 },
442 {ISD::VECTOR_SHUFFLE, MVT::v4i64, 1}, // vblendpd
537 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
538 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
543 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
546 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
607 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 },
617 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
618 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
622 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
627 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
628 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
631 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
632 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
634 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
635 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
636 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
648 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
649 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
652 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
653 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
658 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
659 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
662 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
663 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
668 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
669 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
670 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
705 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 20 },
706 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
707 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
724 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
725 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
726 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
727 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
728 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
729 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
786 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
787 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 },
798 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
799 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 },
804 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
805 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 },
903 { ISD::SETCC, MVT::v4i64, 4 },
910 { ISD::SETCC, MVT::v4i64, 1 },
949 { ISD::BITREVERSE, MVT::v4i64, 4 },
963 { ISD::BITREVERSE, MVT::v4i64, 5 },
967 { ISD::BSWAP, MVT::v4i64, 1 },
972 { ISD::BITREVERSE, MVT::v4i64, 10 },
976 { ISD::BSWAP, MVT::v4i64, 4 },
1220 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
1239 { ISD::ADD, MVT::v4i64, 3 },
