Lines Matching refs:svga
48 #define EMIT_RS(svga, value, token, fail) \
50 STATIC_ASSERT(SVGA3D_RS_##token < ARRAY_SIZE(svga->state.hw_draw.rs)); \
51 if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
53 svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
57 #define EMIT_RS_FLOAT(svga, fvalue, token, fail) \
60 STATIC_ASSERT(SVGA3D_RS_##token < ARRAY_SIZE(svga->state.hw_draw.rs)); \
61 if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
63 svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
84 emit_rss_vgpu9(struct svga_context *svga, unsigned dirty)
86 struct svga_screen *screen = svga_screen(svga->pipe.screen);
93 const struct svga_blend_state *curr = svga->curr.blend;
95 EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
96 EMIT_RS( svga, curr->rt[0].blend_enable, BLENDENABLE, fail );
99 EMIT_RS( svga, curr->rt[0].srcblend, SRCBLEND, fail );
100 EMIT_RS( svga, curr->rt[0].dstblend, DSTBLEND, fail );
101 EMIT_RS( svga, curr->rt[0].blendeq, BLENDEQUATION, fail );
103 EMIT_RS( svga, curr->rt[0].separate_alpha_blend_enable,
107 EMIT_RS( svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA, fail );
108 EMIT_RS( svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA, fail );
109 EMIT_RS( svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA, fail );
116 uint32 r = float_to_ubyte(svga->curr.blend_color.color[0]);
117 uint32 g = float_to_ubyte(svga->curr.blend_color.color[1]);
118 uint32 b = float_to_ubyte(svga->curr.blend_color.color[2]);
119 uint32 a = float_to_ubyte(svga->curr.blend_color.color[3]);
123 EMIT_RS( svga, color, BLENDCOLOR, fail );
127 const struct svga_depth_stencil_state *curr = svga->curr.depth;
128 const struct svga_rasterizer_state *rast = svga->curr.rast;
134 EMIT_RS( svga, FALSE, STENCILENABLE, fail );
135 EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
141 EMIT_RS( svga, TRUE, STENCILENABLE, fail );
142 EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
144 EMIT_RS( svga, curr->stencil[0].func, STENCILFUNC, fail );
145 EMIT_RS( svga, curr->stencil[0].fail, STENCILFAIL, fail );
146 EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail );
147 EMIT_RS( svga, curr->stencil[0].pass, STENCILPASS, fail );
149 EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
150 EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
171 EMIT_RS( svga, TRUE, STENCILENABLE, fail );
172 EMIT_RS( svga, TRUE, STENCILENABLE2SIDED, fail );
174 EMIT_RS( svga, curr->stencil[cw].func, STENCILFUNC, fail );
175 EMIT_RS( svga, curr->stencil[cw].fail, STENCILFAIL, fail );
176 EMIT_RS( svga, curr->stencil[cw].zfail, STENCILZFAIL, fail );
177 EMIT_RS( svga, curr->stencil[cw].pass, STENCILPASS, fail );
179 EMIT_RS( svga, curr->stencil[ccw].func, CCWSTENCILFUNC, fail );
180 EMIT_RS( svga, curr->stencil[ccw].fail, CCWSTENCILFAIL, fail );
181 EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail );
182 EMIT_RS( svga, curr->stencil[ccw].pass, CCWSTENCILPASS, fail );
184 EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
185 EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
188 EMIT_RS( svga, curr->zenable, ZENABLE, fail );
190 EMIT_RS( svga, curr->zfunc, ZFUNC, fail );
191 EMIT_RS( svga, curr->zwriteenable, ZWRITEENABLE, fail );
194 EMIT_RS( svga, curr->alphatestenable, ALPHATESTENABLE, fail );
196 EMIT_RS( svga, curr->alphafunc, ALPHAFUNC, fail );
197 EMIT_RS_FLOAT( svga, curr->alpharef, ALPHAREF, fail );
202 EMIT_RS( svga, svga->curr.stencil_ref.ref_value[0], STENCILREF, fail );
207 const struct svga_rasterizer_state *curr = svga->curr.rast;
213 EMIT_RS( svga, curr->shademode, SHADEMODE, fail );
219 if (svga->state.sw.need_pipeline)
224 EMIT_RS( svga, cullmode, CULLMODE, fail );
225 EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail );
226 EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail );
227 EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail );
228 EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail );
229 EMIT_RS_FLOAT( svga, point_size_min, POINTSIZEMIN, fail );
230 EMIT_RS_FLOAT( svga, screen->maxPointSize, POINTSIZEMAX, fail );
231 EMIT_RS( svga, curr->pointsprite, POINTSPRITEENABLE, fail);
235 EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail );
237 EMIT_RS( svga, curr->antialiasedlineenable, ANTIALIASEDLINEENABLE, fail );
239 EMIT_RS_FLOAT( svga, curr->linewidth, LINEWIDTH, fail );
244 const struct svga_rasterizer_state *curr = svga->curr.rast;
252 if (!svga->state.sw.need_pipeline &&
253 svga->curr.framebuffer.zsbuf)
256 bias = svga->curr.depthscale * curr->depthbias;
259 EMIT_RS_FLOAT( svga, slope, SLOPESCALEDEPTHBIAS, fail );
260 EMIT_RS_FLOAT( svga, bias, DEPTHBIAS, fail );
266 if (svga->curr.framebuffer.cbufs[0] &&
267 util_format_is_srgb(svga->curr.framebuffer.cbufs[0]->format)) {
270 EMIT_RS_FLOAT(svga, gamma, OUTPUTGAMMA, fail);
275 unsigned enabled = svga->curr.rast->templ.clip_plane_enable;
276 EMIT_RS( svga, enabled, CLIPPLANEENABLE, fail );
282 if (SVGA3D_BeginSetRenderState( svga->swc,
291 SVGA_FIFOCommitAll( svga->swc );
302 memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
311 get_no_cull_rasterizer_state(struct svga_context *svga)
313 const struct svga_rasterizer_state *r = svga->curr.rast;
316 if (!svga->rasterizer_no_cull[aa_point]) {
333 svga->rasterizer_no_cull[aa_point] =
334 svga->pipe.create_rasterizer_state(&svga->pipe, &rast);
336 return svga->rasterizer_no_cull[aa_point];
340 emit_rss_vgpu10(struct svga_context *svga, unsigned dirty)
344 svga_hwtnl_flush_retry(svga);
350 if (svga_has_any_integer_cbufs(svga)) {
352 curr = svga->noop_blend;
359 curr = svga->curr.blend;
365 blend_factor[3] = svga->curr.blend_color.color[3];
368 blend_factor[0] = svga->curr.blend_color.color[0];
369 blend_factor[1] = svga->curr.blend_color.color[1];
370 blend_factor[2] = svga->curr.blend_color.color[2];
371 blend_factor[3] = svga->curr.blend_color.color[3];
376 if (svga->state.hw_draw.blend_id != curr->id ||
377 svga->state.hw_draw.blend_factor[0] != blend_factor[0] ||
378 svga->state.hw_draw.blend_factor[1] != blend_factor[1] ||
379 svga->state.hw_draw.blend_factor[2] != blend_factor[2] ||
380 svga->state.hw_draw.blend_factor[3] != blend_factor[3] ||
381 svga->state.hw_draw.blend_sample_mask != svga->curr.sample_mask) {
382 ret = SVGA3D_vgpu10_SetBlendState(svga->swc, curr->id,
384 svga->curr.sample_mask);
388 svga->state.hw_draw.blend_id = curr->id;
389 svga->state.hw_draw.blend_factor[0] = blend_factor[0];
390 svga->state.hw_draw.blend_factor[1] = blend_factor[1];
391 svga->state.hw_draw.blend_factor[2] = blend_factor[2];
392 svga->state.hw_draw.blend_factor[3] = blend_factor[3];
393 svga->state.hw_draw.blend_sample_mask = svga->curr.sample_mask;
398 const struct svga_depth_stencil_state *curr = svga->curr.depth;
399 unsigned curr_ref = svga->curr.stencil_ref.ref_value[0];
401 if (curr->id != svga->state.hw_draw.depth_stencil_id ||
402 curr_ref != svga->state.hw_draw.stencil_ref) {
404 ret = SVGA3D_vgpu10_SetDepthStencilState(svga->swc, curr->id,
409 svga->state.hw_draw.depth_stencil_id = curr->id;
410 svga->state.hw_draw.stencil_ref = curr_ref;
417 if (svga->curr.reduced_prim == PIPE_PRIM_POINTS &&
418 svga->curr.gs && svga->curr.gs->wide_point) {
423 rast = get_no_cull_rasterizer_state(svga);
426 rast = svga->curr.rast;
429 if (svga->state.hw_draw.rasterizer_id != rast->id) {
431 ret = SVGA3D_vgpu10_SetRasterizerState(svga->swc, rast->id);
434 svga->state.hw_draw.rasterizer_id = rast->id;
442 emit_rss(struct svga_context *svga, unsigned dirty)
444 if (svga_have_vgpu10(svga)) {
445 return emit_rss_vgpu10(svga, dirty);
448 return emit_rss_vgpu9(svga, dirty);
