Lines Matching refs:ws
104 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
148 static bool do_winsys_init(struct radeon_drm_winsys *ws)
175 version = drmGetVersion(ws->fd);
188 ws->info.drm_major = version->version_major;
189 ws->info.drm_minor = version->version_minor;
190 ws->info.drm_patchlevel = version->version_patchlevel;
194 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
195 &ws->info.pci_id))
199 switch (ws->info.pci_id) {
200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
217 switch (ws->info.family) {
230 ws->info.chip_class = R300;
241 ws->info.chip_class = R400;
249 ws->info.chip_class = R500;
259 ws->info.chip_class = R600;
265 ws->info.chip_class = R700;
278 ws->info.chip_class = EVERGREEN;
282 ws->info.chip_class = CAYMAN;
289 ws->info.chip_class = SI;
296 ws->info.chip_class = CIK;
301 switch (ws->info.family) {
317 ws->info.has_dedicated_vram = false;
321 ws->info.has_dedicated_vram = true;
325 ws->info.has_sdma = false;
327 if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
328 ws->info.has_sdma = true;
332 ws->info.has_uvd = false;
333 ws->info.vce_fw_version = 0x00000000;
334 if (ws->info.drm_minor >= 32) {
336 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
338 ws->info.has_uvd = value;
341 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
344 if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
346 ws->info.vce_fw_version = value;
360 ws->info.has_userptr =
361 drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
366 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
373 ws->info.gart_size = gem_info.gart_size;
374 ws->info.vram_size = gem_info.vram_size;
378 ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
379 if (ws->info.drm_minor < 40)
380 ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
383 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
384 &ws->info.max_shader_clock);
385 ws->info.max_shader_clock /= 1000;
387 radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
388 &ws->info.enabled_rb_mask);
390 ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
393 if (ws->gen == DRV_R300) {
394 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
396 &ws->info.r300_num_gb_pipes))
399 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
401 &ws->info.r300_num_z_pipes))
404 else if (ws->gen >= DRV_R600) {
407 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
409 &ws->info.num_render_backends))
413 radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
414 &ws->info.clock_crystal_freq);
416 radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
419 ws->info.r600_num_banks =
420 ws->info.chip_class >= EVERGREEN ?
424 ws->info.pipe_interleave_bytes =
425 ws->info.chip_class >= EVERGREEN ?
429 if (!ws->info.pipe_interleave_bytes)
430 ws->info.pipe_interleave_bytes =
431 ws->info.chip_class >= EVERGREEN ? 512 : 256;
433 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
434 &ws->info.num_tile_pipes);
441 if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
442 ws->info.num_tile_pipes = 8;
444 if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
445 &ws->info.r600_gb_backend_map))
446 ws->info.r600_gb_backend_map_valid = true;
448 ws->info.has_virtual_memory = false;
449 if (ws->info.drm_minor >= 13) {
452 ws->info.has_virtual_memory = true;
453 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
454 &ws->va_start))
455 ws->info.has_virtual_memory = false;
456 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
458 ws->info.has_virtual_memory = false;
459 radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
460 &ws->va_unmap_working);
462 if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
463 ws->info.has_virtual_memory = false;
468 ws->info.r600_max_quad_pipes = 2;
469 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
470 &ws->info.r600_max_quad_pipes);
473 ws->info.num_good_compute_units = 1;
474 radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
475 &ws->info.num_good_compute_units);
477 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
478 &ws->info.max_se);
480 if (!ws->info.max_se) {
481 switch (ws->info.family) {
483 ws->info.max_se = 1;
492 ws->info.max_se = 2;
495 ws->info.max_se = 4;
500 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
501 &ws->info.max_sh_per_se);
503 radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
504 &ws->accel_working2);
505 if (ws->info.family == CHIP_HAWAII && ws
509 ws->accel_working2);
513 if (ws->info.chip_class == CIK) {
514 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
515 ws->info.cik_macrotile_mode_array)) {
521 if (ws->info.chip_class >= SI) {
522 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
523 ws->info.si_tile_mode_array)) {
532 ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
533 (ws->info.family == CHIP_HAWAII &&
534 ws->accel_working2 < 3);
536 ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
543 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
545 if (util_queue_is_initialized(&ws->cs_queue))
546 util_queue_destroy(&ws->cs_queue);
548 pipe_mutex_destroy(ws->hyperz_owner_mutex);
549 pipe_mutex_destroy(ws->cmask_owner_mutex);
551 if (ws->info.has_virtual_memory)
552 pb_slabs_deinit(&ws->bo_slabs);
553 pb_cache_deinit(&ws->bo_cache);
555 if (ws->gen >= DRV_R600) {
556 radeon_surface_manager_free(ws->surf_man);
559 util_hash_table_destroy(ws->bo_names);
560 util_hash_table_destroy(ws->bo_handles);
561 util_hash_table_destroy(ws->bo_vas);
562 pipe_mutex_destroy(ws->bo_handles_mutex);
563 pipe_mutex_destroy(ws->bo_va_mutex);
564 pipe_mutex_destroy(ws->bo_fence_lock);
566 if (ws->fd >= 0)
567 close(ws->fd);
586 return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
587 &cs->ws->hyperz_owner_mutex,
592 return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
593 &cs->ws->cmask_owner_mutex,
603 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
608 return ws->allocated_vram;
610 return ws->allocated_gtt;
612 return ws->mapped_vram;
614 return ws->mapped_gtt;
616 return ws->buffer_wait_time;
618 if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
623 radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
627 return ws->num_gfx_IBs;
629 return ws->num_sdma_IBs;
631 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
637 radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
641 radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
645 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
649 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
653 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
657 radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
668 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
674 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, ®))
705 static bool radeon_winsys_unref(struct radeon_winsys *ws)
707 struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
739 struct radeon_drm_winsys *ws;
746 ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
747 if (ws) {
748 pipe_reference(NULL, &ws->reference);
750 return &ws->base;
753 ws = CALLOC_STRUCT(radeon_drm_winsys);
754 if (!ws) {
759 ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
761 if (!do_winsys_init(ws))
764 pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
765 MIN2(ws->info.vram_size, ws->info.gart_size),
769 if (ws->info.has_virtual_memory) {
774 if (!pb_slabs_init(&ws->bo_slabs,
777 ws,
783 ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
785 ws->info.min_alloc_size = ws->info.gart_page_size;
788 if (ws->gen >= DRV_R600) {
789 ws->surf_man = radeon_surface_manager_new(ws->fd);
790 if (!ws->surf_man)
795 pipe_reference_init(&ws->reference, 1);
798 ws->base.unref = radeon_winsys_unref;
799 ws->base.destroy = radeon_winsys_destroy;
800 ws->base.query_info = radeon_query_info;
801 ws->base.cs_request_feature = radeon_cs_request_feature;
802 ws->base.query_value = radeon_query_value;
803 ws->base.read_registers = radeon_read_registers;
805 radeon_drm_bo_init_functions(ws);
806 radeon_drm_cs_init_functions(ws);
807 radeon_surface_init_functions(ws);
809 pipe_mutex_init(ws->hyperz_owner_mutex);
810 pipe_mutex_init(ws->cmask_owner_mutex);
812 ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
813 ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
814 ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
815 pipe_mutex_init(ws->bo_handles_mutex);
816 pipe_mutex_init(ws->bo_va_mutex);
817 pipe_mutex_init(ws->bo_fence_lock);
818 ws->va_offset = ws->va_start;
819 list_inithead(&ws->va_holes);
822 ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
824 if (ws->num_cpus > 1 && debug_get_option_thread())
825 util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1);
830 * Alternatively, we could create the screen based on "ws->gen"
832 ws->base.screen = screen_create(&ws->base);
833 if (!ws->base.screen) {
834 radeon_winsys_destroy(&ws->base);
839 util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
846 return &ws->base;
849 if (ws->info.has_virtual_memory)
850 pb_slabs_deinit(&ws->bo_slabs);
852 pb_cache_deinit(&ws->bo_cache);
855 if (ws->surf_man)
856 radeon_surface_manager_free(ws->surf_man);
857 if (ws->fd >= 0)
858 close(ws->fd);
860 FREE(ws);
