1 /* 2 * Copyright 2009 Corbin Simpson 3 * Copyright 2011 Marek Olk <maraeo (at) gmail.com> 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 */ 27 /* 28 * Authors: 29 * Corbin Simpson <MostAwesomeDude (at) gmail.com> 30 * Joakim Sindholt <opensource (at) zhasha.com> 31 * Marek Olk <maraeo (at) gmail.com> 32 */ 33 34 #include "radeon_drm_bo.h" 35 #include "radeon_drm_cs.h" 36 #include "radeon_drm_public.h" 37 38 #include "util/u_memory.h" 39 #include "util/u_hash_table.h" 40 41 #include <xf86drm.h> 42 #include <stdio.h> 43 #include <sys/types.h> 44 #include <sys/stat.h> 45 #include <unistd.h> 46 #include <fcntl.h> 47 #include <radeon_surface.h> 48 49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT 50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20 51 #endif 52 53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP 54 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21 55 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22 56 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23 57 #define RADEON_INFO_READ_REG 0x24 58 #endif 59 60 #define RADEON_INFO_VA_UNMAP_WORKING 0x25 61 62 #ifndef RADEON_INFO_GPU_RESET_COUNTER 63 #define RADEON_INFO_GPU_RESET_COUNTER 0x26 64 #endif 65 66 static struct util_hash_table *fd_tab = NULL; 67 pipe_static_mutex(fd_tab_mutex); 68 69 /* Enable/disable feature access for one command stream. 70 * If enable == true, return true on success. 71 * Otherwise, return false. 72 * 73 * We basically do the same thing kernel does, because we have to deal 74 * with multiple contexts (here command streams) backed by one winsys. */ 75 static bool radeon_set_fd_access(struct radeon_drm_cs *applier, 76 struct radeon_drm_cs **owner, 77 pipe_mutex *mutex, 78 unsigned request, const char *request_name, 79 bool enable) 80 { 81 struct drm_radeon_info info; 82 unsigned value = enable ? 1 : 0; 83 84 memset(&info, 0, sizeof(info)); 85 86 pipe_mutex_lock(*mutex); 87 88 /* Early exit if we are sure the request will fail. */ 89 if (enable) { 90 if (*owner) { 91 pipe_mutex_unlock(*mutex); 92 return false; 93 } 94 } else { 95 if (*owner != applier) { 96 pipe_mutex_unlock(*mutex); 97 return false; 98 } 99 } 100 101 /* Pass through the request to the kernel. */ 102 info.value = (unsigned long)&value; 103 info.request = request; 104 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO, 105 &info, sizeof(info)) != 0) { 106 pipe_mutex_unlock(*mutex); 107 return false; 108 } 109 110 /* Update the rights in the winsys. */ 111 if (enable) { 112 if (value) { 113 *owner = applier; 114 pipe_mutex_unlock(*mutex); 115 return true; 116 } 117 } else { 118 *owner = NULL; 119 } 120 121 pipe_mutex_unlock(*mutex); 122 return false; 123 } 124 125 static bool radeon_get_drm_value(int fd, unsigned request, 126 const char *errname, uint32_t *out) 127 { 128 struct drm_radeon_info info; 129 int retval; 130 131 memset(&info, 0, sizeof(info)); 132 133 info.value = (unsigned long)out; 134 info.request = request; 135 136 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)); 137 if (retval) { 138 if (errname) { 139 fprintf(stderr, "radeon: Failed to get %s, error number %d\n", 140 errname, retval); 141 } 142 return false; 143 } 144 return true; 145 } 146 147 /* Helper function to do the ioctls needed for setup and init. */ 148 static bool do_winsys_init(struct radeon_drm_winsys *ws) 149 { 150 struct drm_radeon_gem_info gem_info; 151 int retval; 152 drmVersionPtr version; 153 154 memset(&gem_info, 0, sizeof(gem_info)); 155 156 /* We do things in a specific order here. 157 * 158 * DRM version first. We need to be sure we're running on a KMS chipset. 159 * This is also for some features. 160 * 161 * Then, the PCI ID. This is essential and should return usable numbers 162 * for all Radeons. If this fails, we probably got handed an FD for some 163 * non-Radeon card. 164 * 165 * The GEM info is actually bogus on the kernel side, as well as our side 166 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because 167 * we don't actually use the info for anything yet. 168 * 169 * The GB and Z pipe requests should always succeed, but they might not 170 * return sensical values for all chipsets, but that's alright because 171 * the pipe drivers already know that. 172 */ 173 174 /* Get DRM version. */ 175 version = drmGetVersion(ws->fd); 176 if (version->version_major != 2 || 177 version->version_minor < 12) { 178 fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is " 179 "only compatible with 2.12.0 (kernel 3.2) or later.\n", 180 __FUNCTION__, 181 version->version_major, 182 version->version_minor, 183 version->version_patchlevel); 184 drmFreeVersion(version); 185 return false; 186 } 187 188 ws->info.drm_major = version->version_major; 189 ws->info.drm_minor = version->version_minor; 190 ws->info.drm_patchlevel = version->version_patchlevel; 191 drmFreeVersion(version); 192 193 /* Get PCI ID. */ 194 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID", 195 &ws->info.pci_id)) 196 return false; 197 198 /* Check PCI ID. */ 199 switch (ws->info.pci_id) { 200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break; 201 #include "pci_ids/r300_pci_ids.h" 202 #undef CHIPSET 203 204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break; 205 #include "pci_ids/r600_pci_ids.h" 206 #undef CHIPSET 207 208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break; 209 #include "pci_ids/radeonsi_pci_ids.h" 210 #undef CHIPSET 211 212 default: 213 fprintf(stderr, "radeon: Invalid PCI ID.\n"); 214 return false; 215 } 216 217 switch (ws->info.family) { 218 default: 219 case CHIP_UNKNOWN: 220 fprintf(stderr, "radeon: Unknown family.\n"); 221 return false; 222 case CHIP_R300: 223 case CHIP_R350: 224 case CHIP_RV350: 225 case CHIP_RV370: 226 case CHIP_RV380: 227 case CHIP_RS400: 228 case CHIP_RC410: 229 case CHIP_RS480: 230 ws->info.chip_class = R300; 231 break; 232 case CHIP_R420: /* R4xx-based cores. */ 233 case CHIP_R423: 234 case CHIP_R430: 235 case CHIP_R480: 236 case CHIP_R481: 237 case CHIP_RV410: 238 case CHIP_RS600: 239 case CHIP_RS690: 240 case CHIP_RS740: 241 ws->info.chip_class = R400; 242 break; 243 case CHIP_RV515: /* R5xx-based cores. */ 244 case CHIP_R520: 245 case CHIP_RV530: 246 case CHIP_R580: 247 case CHIP_RV560: 248 case CHIP_RV570: 249 ws->info.chip_class = R500; 250 break; 251 case CHIP_R600: 252 case CHIP_RV610: 253 case CHIP_RV630: 254 case CHIP_RV670: 255 case CHIP_RV620: 256 case CHIP_RV635: 257 case CHIP_RS780: 258 case CHIP_RS880: 259 ws->info.chip_class = R600; 260 break; 261 case CHIP_RV770: 262 case CHIP_RV730: 263 case CHIP_RV710: 264 case CHIP_RV740: 265 ws->info.chip_class = R700; 266 break; 267 case CHIP_CEDAR: 268 case CHIP_REDWOOD: 269 case CHIP_JUNIPER: 270 case CHIP_CYPRESS: 271 case CHIP_HEMLOCK: 272 case CHIP_PALM: 273 case CHIP_SUMO: 274 case CHIP_SUMO2: 275 case CHIP_BARTS: 276 case CHIP_TURKS: 277 case CHIP_CAICOS: 278 ws->info.chip_class = EVERGREEN; 279 break; 280 case CHIP_CAYMAN: 281 case CHIP_ARUBA: 282 ws->info.chip_class = CAYMAN; 283 break; 284 case CHIP_TAHITI: 285 case CHIP_PITCAIRN: 286 case CHIP_VERDE: 287 case CHIP_OLAND: 288 case CHIP_HAINAN: 289 ws->info.chip_class = SI; 290 break; 291 case CHIP_BONAIRE: 292 case CHIP_KAVERI: 293 case CHIP_KABINI: 294 case CHIP_HAWAII: 295 case CHIP_MULLINS: 296 ws->info.chip_class = CIK; 297 break; 298 } 299 300 /* Set which chips don't have dedicated VRAM. */ 301 switch (ws->info.family) { 302 case CHIP_RS400: 303 case CHIP_RC410: 304 case CHIP_RS480: 305 case CHIP_RS600: 306 case CHIP_RS690: 307 case CHIP_RS740: 308 case CHIP_RS780: 309 case CHIP_RS880: 310 case CHIP_PALM: 311 case CHIP_SUMO: 312 case CHIP_SUMO2: 313 case CHIP_ARUBA: 314 case CHIP_KAVERI: 315 case CHIP_KABINI: 316 case CHIP_MULLINS: 317 ws->info.has_dedicated_vram = false; 318 break; 319 320 default: 321 ws->info.has_dedicated_vram = true; 322 } 323 324 /* Check for dma */ 325 ws->info.has_sdma = false; 326 /* DMA is disabled on R700. There is IB corruption and hangs. */ 327 if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { 328 ws->info.has_sdma = true; 329 } 330 331 /* Check for UVD and VCE */ 332 ws->info.has_uvd = false; 333 ws->info.vce_fw_version = 0x00000000; 334 if (ws->info.drm_minor >= 32) { 335 uint32_t value = RADEON_CS_RING_UVD; 336 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, 337 "UVD Ring working", &value)) 338 ws->info.has_uvd = value; 339 340 value = RADEON_CS_RING_VCE; 341 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, 342 NULL, &value) && value) { 343 344 if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION, 345 "VCE FW version", &value)) 346 ws->info.vce_fw_version = value; 347 } 348 } 349 350 /* Check for userptr support. */ 351 { 352 struct drm_radeon_gem_userptr args = {0}; 353 354 /* If the ioctl doesn't exist, -EINVAL is returned. 355 * 356 * If the ioctl exists, it should return -EACCES 357 * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER 358 * aren't set. 359 */ 360 ws->info.has_userptr = 361 drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR, 362 &args, sizeof(args)) == -EACCES; 363 } 364 365 /* Get GEM info. */ 366 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO, 367 &gem_info, sizeof(gem_info)); 368 if (retval) { 369 fprintf(stderr, "radeon: Failed to get MM info, error number %d\n", 370 retval); 371 return false; 372 } 373 ws->info.gart_size = gem_info.gart_size; 374 ws->info.vram_size = gem_info.vram_size; 375 376 /* Radeon allocates all buffers as contigous, which makes large allocations 377 * unlikely to succeed. */ 378 ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7; 379 if (ws->info.drm_minor < 40) 380 ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024); 381 382 /* Get max clock frequency info and convert it to MHz */ 383 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL, 384 &ws->info.max_shader_clock); 385 ws->info.max_shader_clock /= 1000; 386 387 radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL, 388 &ws->info.enabled_rb_mask); 389 390 ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN); 391 392 /* Generation-specific queries. */ 393 if (ws->gen == DRV_R300) { 394 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES, 395 "GB pipe count", 396 &ws->info.r300_num_gb_pipes)) 397 return false; 398 399 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES, 400 "Z pipe count", 401 &ws->info.r300_num_z_pipes)) 402 return false; 403 } 404 else if (ws->gen >= DRV_R600) { 405 uint32_t tiling_config = 0; 406 407 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS, 408 "num backends", 409 &ws->info.num_render_backends)) 410 return false; 411 412 /* get the GPU counter frequency, failure is not fatal */ 413 radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL, 414 &ws->info.clock_crystal_freq); 415 416 radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL, 417 &tiling_config); 418 419 ws->info.r600_num_banks = 420 ws->info.chip_class >= EVERGREEN ? 421 4 << ((tiling_config & 0xf0) >> 4) : 422 4 << ((tiling_config & 0x30) >> 4); 423 424 ws->info.pipe_interleave_bytes = 425 ws->info.chip_class >= EVERGREEN ? 426 256 << ((tiling_config & 0xf00) >> 8) : 427 256 << ((tiling_config & 0xc0) >> 6); 428 429 if (!ws->info.pipe_interleave_bytes) 430 ws->info.pipe_interleave_bytes = 431 ws->info.chip_class >= EVERGREEN ? 512 : 256; 432 433 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL, 434 &ws->info.num_tile_pipes); 435 436 /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the 437 * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti) 438 * reports a different value (12). Fix it by setting what's in the 439 * GB_TILE_MODE array (8). 440 */ 441 if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12) 442 ws->info.num_tile_pipes = 8; 443 444 if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL, 445 &ws->info.r600_gb_backend_map)) 446 ws->info.r600_gb_backend_map_valid = true; 447 448 ws->info.has_virtual_memory = false; 449 if (ws->info.drm_minor >= 13) { 450 uint32_t ib_vm_max_size; 451 452 ws->info.has_virtual_memory = true; 453 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL, 454 &ws->va_start)) 455 ws->info.has_virtual_memory = false; 456 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL, 457 &ib_vm_max_size)) 458 ws->info.has_virtual_memory = false; 459 radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL, 460 &ws->va_unmap_working); 461 } 462 if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false)) 463 ws->info.has_virtual_memory = false; 464 } 465 466 /* Get max pipes, this is only needed for compute shaders. All evergreen+ 467 * chips have at least 2 pipes, so we use 2 as a default. */ 468 ws->info.r600_max_quad_pipes = 2; 469 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL, 470 &ws->info.r600_max_quad_pipes); 471 472 /* All GPUs have at least one compute unit */ 473 ws->info.num_good_compute_units = 1; 474 radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL, 475 &ws->info.num_good_compute_units); 476 477 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL, 478 &ws->info.max_se); 479 480 if (!ws->info.max_se) { 481 switch (ws->info.family) { 482 default: 483 ws->info.max_se = 1; 484 break; 485 case CHIP_CYPRESS: 486 case CHIP_HEMLOCK: 487 case CHIP_BARTS: 488 case CHIP_CAYMAN: 489 case CHIP_TAHITI: 490 case CHIP_PITCAIRN: 491 case CHIP_BONAIRE: 492 ws->info.max_se = 2; 493 break; 494 case CHIP_HAWAII: 495 ws->info.max_se = 4; 496 break; 497 } 498 } 499 500 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL, 501 &ws->info.max_sh_per_se); 502 503 radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL, 504 &ws->accel_working2); 505 if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) { 506 fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, " 507 "returned accel_working2 value %u is smaller than 2. " 508 "Please install a newer kernel.\n", 509 ws->accel_working2); 510 return false; 511 } 512 513 if (ws->info.chip_class == CIK) { 514 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL, 515 ws->info.cik_macrotile_mode_array)) { 516 fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n"); 517 return false; 518 } 519 } 520 521 if (ws->info.chip_class >= SI) { 522 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL, 523 ws->info.si_tile_mode_array)) { 524 fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n"); 525 return false; 526 } 527 } 528 529 /* Hawaii with old firmware needs type2 nop packet. 530 * accel_working2 with value 3 indicates the new firmware. 531 */ 532 ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI || 533 (ws->info.family == CHIP_HAWAII && 534 ws->accel_working2 < 3); 535 536 ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; 537 538 return true; 539 } 540 541 static void radeon_winsys_destroy(struct radeon_winsys *rws) 542 { 543 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; 544 545 if (util_queue_is_initialized(&ws->cs_queue)) 546 util_queue_destroy(&ws->cs_queue); 547 548 pipe_mutex_destroy(ws->hyperz_owner_mutex); 549 pipe_mutex_destroy(ws->cmask_owner_mutex); 550 551 if (ws->info.has_virtual_memory) 552 pb_slabs_deinit(&ws->bo_slabs); 553 pb_cache_deinit(&ws->bo_cache); 554 555 if (ws->gen >= DRV_R600) { 556 radeon_surface_manager_free(ws->surf_man); 557 } 558 559 util_hash_table_destroy(ws->bo_names); 560 util_hash_table_destroy(ws->bo_handles); 561 util_hash_table_destroy(ws->bo_vas); 562 pipe_mutex_destroy(ws->bo_handles_mutex); 563 pipe_mutex_destroy(ws->bo_va_mutex); 564 pipe_mutex_destroy(ws->bo_fence_lock); 565 566 if (ws->fd >= 0) 567 close(ws->fd); 568 569 FREE(rws); 570 } 571 572 static void radeon_query_info(struct radeon_winsys *rws, 573 struct radeon_info *info) 574 { 575 *info = ((struct radeon_drm_winsys *)rws)->info; 576 } 577 578 static bool radeon_cs_request_feature(struct radeon_winsys_cs *rcs, 579 enum radeon_feature_id fid, 580 bool enable) 581 { 582 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); 583 584 switch (fid) { 585 case RADEON_FID_R300_HYPERZ_ACCESS: 586 return radeon_set_fd_access(cs, &cs->ws->hyperz_owner, 587 &cs->ws->hyperz_owner_mutex, 588 RADEON_INFO_WANT_HYPERZ, "Hyper-Z", 589 enable); 590 591 case RADEON_FID_R300_CMASK_ACCESS: 592 return radeon_set_fd_access(cs, &cs->ws->cmask_owner, 593 &cs->ws->cmask_owner_mutex, 594 RADEON_INFO_WANT_CMASK, "AA optimizations", 595 enable); 596 } 597 return false; 598 } 599 600 static uint64_t radeon_query_value(struct radeon_winsys *rws, 601 enum radeon_value_id value) 602 { 603 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; 604 uint64_t retval = 0; 605 606 switch (value) { 607 case RADEON_REQUESTED_VRAM_MEMORY: 608 return ws->allocated_vram; 609 case RADEON_REQUESTED_GTT_MEMORY: 610 return ws->allocated_gtt; 611 case RADEON_MAPPED_VRAM: 612 return ws->mapped_vram; 613 case RADEON_MAPPED_GTT: 614 return ws->mapped_gtt; 615 case RADEON_BUFFER_WAIT_TIME_NS: 616 return ws->buffer_wait_time; 617 case RADEON_TIMESTAMP: 618 if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) { 619 assert(0); 620 return 0; 621 } 622 623 radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp", 624 (uint32_t*)&retval); 625 return retval; 626 case RADEON_NUM_GFX_IBS: 627 return ws->num_gfx_IBs; 628 case RADEON_NUM_SDMA_IBS: 629 return ws->num_sdma_IBs; 630 case RADEON_NUM_BYTES_MOVED: 631 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED, 632 "num-bytes-moved", (uint32_t*)&retval); 633 return retval; 634 case RADEON_NUM_EVICTIONS: 635 return 0; /* unimplemented */ 636 case RADEON_VRAM_USAGE: 637 radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE, 638 "vram-usage", (uint32_t*)&retval); 639 return retval; 640 case RADEON_GTT_USAGE: 641 radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE, 642 "gtt-usage", (uint32_t*)&retval); 643 return retval; 644 case RADEON_GPU_TEMPERATURE: 645 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP, 646 "gpu-temp", (uint32_t*)&retval); 647 return retval; 648 case RADEON_CURRENT_SCLK: 649 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK, 650 "current-gpu-sclk", (uint32_t*)&retval); 651 return retval; 652 case RADEON_CURRENT_MCLK: 653 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK, 654 "current-gpu-mclk", (uint32_t*)&retval); 655 return retval; 656 case RADEON_GPU_RESET_COUNTER: 657 radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER, 658 "gpu-reset-counter", (uint32_t*)&retval); 659 return retval; 660 } 661 return 0; 662 } 663 664 static bool radeon_read_registers(struct radeon_winsys *rws, 665 unsigned reg_offset, 666 unsigned num_registers, uint32_t *out) 667 { 668 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; 669 unsigned i; 670 671 for (i = 0; i < num_registers; i++) { 672 uint32_t reg = reg_offset + i*4; 673 674 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, ®)) 675 return false; 676 out[i] = reg; 677 } 678 return true; 679 } 680 681 static unsigned hash_fd(void *key) 682 { 683 int fd = pointer_to_intptr(key); 684 struct stat stat; 685 fstat(fd, &stat); 686 687 return stat.st_dev ^ stat.st_ino ^ stat.st_rdev; 688 } 689 690 static int compare_fd(void *key1, void *key2) 691 { 692 int fd1 = pointer_to_intptr(key1); 693 int fd2 = pointer_to_intptr(key2); 694 struct stat stat1, stat2; 695 fstat(fd1, &stat1); 696 fstat(fd2, &stat2); 697 698 return stat1.st_dev != stat2.st_dev || 699 stat1.st_ino != stat2.st_ino || 700 stat1.st_rdev != stat2.st_rdev; 701 } 702 703 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true) 704 705 static bool radeon_winsys_unref(struct radeon_winsys *ws) 706 { 707 struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws; 708 bool destroy; 709 710 /* When the reference counter drops to zero, remove the fd from the table. 711 * This must happen while the mutex is locked, so that 712 * radeon_drm_winsys_create in another thread doesn't get the winsys 713 * from the table when the counter drops to 0. */ 714 pipe_mutex_lock(fd_tab_mutex); 715 716 destroy = pipe_reference(&rws->reference, NULL); 717 if (destroy && fd_tab) 718 util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd)); 719 720 pipe_mutex_unlock(fd_tab_mutex); 721 return destroy; 722 } 723 724 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) 725 726 static unsigned handle_hash(void *key) 727 { 728 return PTR_TO_UINT(key); 729 } 730 731 static int handle_compare(void *key1, void *key2) 732 { 733 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2); 734 } 735 736 PUBLIC struct radeon_winsys * 737 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create) 738 { 739 struct radeon_drm_winsys *ws; 740 741 pipe_mutex_lock(fd_tab_mutex); 742 if (!fd_tab) { 743 fd_tab = util_hash_table_create(hash_fd, compare_fd); 744 } 745 746 ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd)); 747 if (ws) { 748 pipe_reference(NULL, &ws->reference); 749 pipe_mutex_unlock(fd_tab_mutex); 750 return &ws->base; 751 } 752 753 ws = CALLOC_STRUCT(radeon_drm_winsys); 754 if (!ws) { 755 pipe_mutex_unlock(fd_tab_mutex); 756 return NULL; 757 } 758 759 ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3); 760 761 if (!do_winsys_init(ws)) 762 goto fail1; 763 764 pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0, 765 MIN2(ws->info.vram_size, ws->info.gart_size), 766 radeon_bo_destroy, 767 radeon_bo_can_reclaim); 768 769 if (ws->info.has_virtual_memory) { 770 /* There is no fundamental obstacle to using slab buffer allocation 771 * without GPUVM, but enabling it requires making sure that the drivers 772 * honor the address offset. 773 */ 774 if (!pb_slabs_init(&ws->bo_slabs, 775 RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2, 776 12, 777 ws, 778 radeon_bo_can_reclaim_slab, 779 radeon_bo_slab_alloc, 780 radeon_bo_slab_free)) 781 goto fail_cache; 782 783 ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2; 784 } else { 785 ws->info.min_alloc_size = ws->info.gart_page_size; 786 } 787 788 if (ws->gen >= DRV_R600) { 789 ws->surf_man = radeon_surface_manager_new(ws->fd); 790 if (!ws->surf_man) 791 goto fail_slab; 792 } 793 794 /* init reference */ 795 pipe_reference_init(&ws->reference, 1); 796 797 /* Set functions. */ 798 ws->base.unref = radeon_winsys_unref; 799 ws->base.destroy = radeon_winsys_destroy; 800 ws->base.query_info = radeon_query_info; 801 ws->base.cs_request_feature = radeon_cs_request_feature; 802 ws->base.query_value = radeon_query_value; 803 ws->base.read_registers = radeon_read_registers; 804 805 radeon_drm_bo_init_functions(ws); 806 radeon_drm_cs_init_functions(ws); 807 radeon_surface_init_functions(ws); 808 809 pipe_mutex_init(ws->hyperz_owner_mutex); 810 pipe_mutex_init(ws->cmask_owner_mutex); 811 812 ws->bo_names = util_hash_table_create(handle_hash, handle_compare); 813 ws->bo_handles = util_hash_table_create(handle_hash, handle_compare); 814 ws->bo_vas = util_hash_table_create(handle_hash, handle_compare); 815 pipe_mutex_init(ws->bo_handles_mutex); 816 pipe_mutex_init(ws->bo_va_mutex); 817 pipe_mutex_init(ws->bo_fence_lock); 818 ws->va_offset = ws->va_start; 819 list_inithead(&ws->va_holes); 820 821 /* TTM aligns the BO size to the CPU page size */ 822 ws->info.gart_page_size = sysconf(_SC_PAGESIZE); 823 824 if (ws->num_cpus > 1 && debug_get_option_thread()) 825 util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1); 826 827 /* Create the screen at the end. The winsys must be initialized 828 * completely. 829 * 830 * Alternatively, we could create the screen based on "ws->gen" 831 * and link all drivers into one binary blob. */ 832 ws->base.screen = screen_create(&ws->base); 833 if (!ws->base.screen) { 834 radeon_winsys_destroy(&ws->base); 835 pipe_mutex_unlock(fd_tab_mutex); 836 return NULL; 837 } 838 839 util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws); 840 841 /* We must unlock the mutex once the winsys is fully initialized, so that 842 * other threads attempting to create the winsys from the same fd will 843 * get a fully initialized winsys and not just half-way initialized. */ 844 pipe_mutex_unlock(fd_tab_mutex); 845 846 return &ws->base; 847 848 fail_slab: 849 if (ws->info.has_virtual_memory) 850 pb_slabs_deinit(&ws->bo_slabs); 851 fail_cache: 852 pb_cache_deinit(&ws->bo_cache); 853 fail1: 854 pipe_mutex_unlock(fd_tab_mutex); 855 if (ws->surf_man) 856 radeon_surface_manager_free(ws->surf_man); 857 if (ws->fd >= 0) 858 close(ws->fd); 859 860 FREE(ws); 861 return NULL; 862 } 863
