Lines Matching defs:ioaddr
54 /* define all ioaddr */
56 #define byPAR0 ioaddr
57 #define byRCR ioaddr + 6
58 #define byTCR ioaddr + 7
59 #define byCR0 ioaddr + 8
60 #define byCR1 ioaddr + 9
61 #define byISR0 ioaddr + 0x0c
62 #define byISR1 ioaddr + 0x0d
63 #define byIMR0 ioaddr + 0x0e
64 #define byIMR1 ioaddr + 0x0f
65 #define byMAR0 ioaddr + 0x10
66 #define byMAR1 ioaddr + 0x11
67 #define byMAR2 ioaddr + 0x12
68 #define byMAR3 ioaddr + 0x13
69 #define byMAR4 ioaddr + 0x14
70 #define byMAR5 ioaddr + 0x15
71 #define byMAR6 ioaddr + 0x16
72 #define byMAR7 ioaddr + 0x17
73 #define dwCurrentRxDescAddr ioaddr + 0x18
74 #define dwCurrentTxDescAddr ioaddr + 0x1c
75 #define dwCurrentRDSE0 ioaddr + 0x20
76 #define dwCurrentRDSE1 ioaddr + 0x24
77 #define dwCurrentRDSE2 ioaddr + 0x28
78 #define dwCurrentRDSE3 ioaddr + 0x2c
79 #define dwNextRDSE0 ioaddr + 0x30
80 #define dwNextRDSE1 ioaddr + 0x34
81 #define dwNextRDSE2 ioaddr + 0x38
82 #define dwNextRDSE3 ioaddr + 0x3c
83 #define dwCurrentTDSE0 ioaddr + 0x40
84 #define dwCurrentTDSE1 ioaddr + 0x44
85 #define dwCurrentTDSE2 ioaddr + 0x48
86 #define dwCurrentTDSE3 ioaddr + 0x4c
87 #define dwNextTDSE0 ioaddr + 0x50
88 #define dwNextTDSE1 ioaddr + 0x54
89 #define dwNextTDSE2 ioaddr + 0x58
90 #define dwNextTDSE3 ioaddr + 0x5c
91 #define dwCurrRxDMAPtr ioaddr + 0x60
92 #define dwCurrTxDMAPtr ioaddr + 0x64
93 #define byMPHY ioaddr + 0x6c
94 #define byMIISR ioaddr + 0x6d
95 #define byBCR0 ioaddr + 0x6e
96 #define byBCR1 ioaddr + 0x6f
97 #define byMIICR ioaddr + 0x70
98 #define byMIIAD ioaddr + 0x71
99 #define wMIIDATA ioaddr + 0x72
100 #define byEECSR ioaddr + 0x74
101 #define byTEST ioaddr + 0x75
102 #define byGPIO ioaddr + 0x76
103 #define byCFGA ioaddr + 0x78
104 #define byCFGB ioaddr + 0x79
105 #define byCFGC ioaddr + 0x7a
106 #define byCFGD ioaddr + 0x7b
107 #define wTallyCntMPA ioaddr + 0x7c
108 #define wTallyCntCRC ioaddr + 0x7d
109 #define bySTICKHW ioaddr + 0x83
110 #define byWOLcrClr ioaddr + 0xA4
111 #define byWOLcgClr ioaddr + 0xA7
112 #define byPwrcsrClr ioaddr + 0xAC
671 unsigned short ioaddr;
687 static void rhine_probe1 (struct nic *nic, struct pci_device *pci, int ioaddr,
699 static void reload_eeprom(int ioaddr);
702 static void reload_eeprom(int ioaddr)
755 QueryAuto (int ioaddr)
764 MIIReturn = ReadMII (byMIIIndex, ioaddr);
768 MIIReturn = ReadMII (byMIIIndex, ioaddr);
781 ReadMII (int byMIIIndex, int ioaddr)
821 WriteMII (char byMIISetByte, char byMIISetBit, char byMIIOP, int ioaddr)
942 intr_status = inw(nic->ioaddr + IntrStatus);
949 intr_status |= inb(nic->ioaddr + IntrStatus2) << 16;
953 outw(intr_status, nic->ioaddr + IntrEnable);
956 outw(0x0010, nic->ioaddr + 0x84);
968 if (!pci->ioaddr)
971 rhine_probe1 (nic, pci, pci->ioaddr, pci->device, -1);
980 nic->ioaddr = tp->ioaddr;
988 int ioaddr = tp->ioaddr;
999 rhine_probe1 (struct nic *nic, struct pci_device *pci, int ioaddr, int chip_id, int options)
1077 reload_eeprom(ioaddr);
1083 DBG ( "IO address %#hX Ethernet Address: %s\n", ioaddr, eth_ntoa ( nic->node_addr ) );
1086 WriteMII (0, 9, 1, ioaddr);
1094 if (ReadMII (1, ioaddr) & 0x0020)
1101 printf("MII : Address %hhX ",inb(ioaddr+0x6c));
1105 st1=ReadMII(1,ioaddr)>>8;
1106 st2=ReadMII(1,ioaddr)&0xFF;
1107 adv1=ReadMII(4,ioaddr)>>8;
1108 adv2=ReadMII(4,ioaddr)&0xFF;
1109 l1=ReadMII(5,ioaddr)>>8;
1110 l2=ReadMII(5,ioaddr)&0xFF;
1117 byMIIvalue = inb (ioaddr + 0x6d);
1128 FDXFlag = QueryAuto (ioaddr);
1142 WriteMII (0x17, 1, 1, ioaddr);
1157 tp->ioaddr = ioaddr;
1176 int ioaddr = tp->ioaddr;
1194 int ioaddr = tp->ioaddr;
1208 /*outb(CmdReset, ioaddr + ChipCmd); */
1270 FDXFlag = QueryAuto (ioaddr);
1286 #define IOSYNC do { inb(nic->ioaddr + StationAddr); } while (0)
1301 intr_status = inw(nic->ioaddr + IntrStatus);
1305 intr_status |= inb(nic->ioaddr + IntrStatus2) << 16;
1309 outb(0x08, nic->ioaddr + IntrStatus2);
1310 outw(intr_status & 0xffff, nic->ioaddr + IntrStatus);
1336 outw(DEFAULT_INTR & ~IntrRxDone, nic->ioaddr + IntrStatus);
1348 int ioaddr = tp->ioaddr;
