Lines Matching refs:code
119 these fields where the VALUE will be extracted from CODE and returned.
129 extract_fields (aarch64_insn code, aarch64_insn mask, ...)
145 value |= extract_field (kind, code, mask);
229 const aarch64_insn code,
232 info->reg.regno = extract_field (self->fields[0], code, 0);
238 const aarch64_insn code ATTRIBUTE_UNUSED,
250 const aarch64_insn code,
253 info->reg.regno = extract_field (self->fields[0], code, 0);
268 const aarch64_insn code,
272 info->reglane.regno = extract_field (self->fields[0], code,
285 aarch64_insn value = extract_field (FLD_imm4, code, 0);
301 aarch64_insn value = extract_field (FLD_imm5, code, 0);
321 info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
327 info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
331 info->reglane.index = extract_field (FLD_H, code, 0);
343 const aarch64_insn code,
347 info->reglist.first_regno = extract_field (self->fields[0], code, 0);
349 info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
356 aarch64_opnd_info *info, const aarch64_insn code,
383 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
385 value = extract_field (FLD_opcode, code, 0);
397 aarch64_opnd_info *info, const aarch64_insn code,
403 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
405 value = extract_field (FLD_S, code, 0);
423 aarch64_opnd_info *info, const aarch64_insn code,
431 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
435 opcodeh2 = extract_field_2 (&field, code, 0);
436 QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size);
464 if (extract_field (FLD_S, code, 0))
492 aarch64_opnd_info *info, const aarch64_insn code,
499 immh = extract_field (FLD_immh, code, 0);
502 imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
514 Q = extract_field (FLD_Q, code, 0);
555 aarch64_opnd_info *info, const aarch64_insn code,
560 val = extract_field (FLD_size, code, 0);
576 const aarch64_insn code,
584 imm = extract_field (self->fields[0], code, 0);
587 imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]);
608 const aarch64_insn code,
611 aarch64_ext_imm (self, info, code, inst);
613 info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
622 const aarch64_insn code,
635 imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
670 info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
676 info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
689 aarch64_opnd_info *info, const aarch64_insn code,
692 info->imm.value = 64- extract_field (FLD_scale, code, 0);
700 aarch64_opnd_info *info, const aarch64_insn code,
707 value = extract_field (FLD_shift, code, 0);
712 info->imm.value = extract_field (FLD_imm12, code, 0);
721 aarch64_opnd_info *info, const aarch64_insn code,
730 value = extract_fields (code, 0, 3, FLD_N, FLD_immr, FLD_imms);
796 const aarch64_insn code, const aarch64_inst *inst)
801 info->reg.regno = extract_field (FLD_Rt, code, 0);
804 value = extract_field (FLD_ldst_size, code, 0);
823 value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
836 aarch64_insn code,
840 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
849 aarch64_insn code, const aarch64_inst *inst)
854 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
856 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
858 value = extract_field (FLD_option, code, 0);
866 S = extract_field (FLD_S, code, 0);
891 aarch64_insn code, const aarch64_inst *inst)
897 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
899 imm = extract_field (self->fields[0], code, 0);
914 if (extract_field (self->fields[1], code, 0) == 1)
926 aarch64_insn code,
933 info->addr.base_regno = extract_field (self->fields[0], code, 0);
935 info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
944 aarch64_insn code, const aarch64_inst *inst)
951 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
953 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
977 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
981 value = extract_field (FLD_cond, code, 0);
990 aarch64_insn code,
994 info->sysreg = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
1002 aarch64_opnd_info *info, aarch64_insn code,
1007 info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
1019 aarch64_insn code,
1026 value = extract_fields (code, 0, 5,
1058 aarch64_insn code,
1062 info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
1072 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
1075 info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
1085 aarch64_insn code,
1092 hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
1111 aarch64_insn code,
1117 info->reg.regno = extract_field (FLD_Rm, code, 0);
1119 value = extract_field (FLD_option, code, 0);
1123 info->shifter.amount = extract_field (FLD_imm3, code, 0);
1144 aarch64_insn code,
1150 info->reg.regno = extract_field (FLD_Rm, code, 0);
1152 value = extract_field (FLD_shift, code, 0);
1161 info->shifter.amount = extract_field (FLD_imm6, code, 0);
1226 We tag one operand with the qualifer according to the code;
1235 aarch64_insn code;
1248 code = inst->value;
1249 value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
1906 adding more operand code to handle unusual encoding/decoding; on other
2001 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2002 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2006 determined and used to disassemble CODE; this is done just before the
2010 aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
2020 if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
2030 inst->value = code;
2059 && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst)))
2067 if (opcode->verifier && ! opcode->verifier (opcode, code))
2076 /* Arriving here, the CODE has been determined as a valid instruction
2173 The two operand code should be the same in all cases, apart from
2334 /* Try to infer the code or data type from a symbol.
