1 /* aarch64-dis.c -- AArch64 disassembler. 2 Copyright (C) 2009-2016 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; see the file COPYING3. If not, 19 see <http://www.gnu.org/licenses/>. */ 20 21 #include "sysdep.h" 22 #include "bfd_stdint.h" 23 #include "dis-asm.h" 24 #include "libiberty.h" 25 #include "opintl.h" 26 #include "aarch64-dis.h" 27 #include "elf-bfd.h" 28 29 #define ERR_OK 0 30 #define ERR_UND -1 31 #define ERR_UNP -3 32 #define ERR_NYI -5 33 34 #define INSNLEN 4 35 36 /* Cached mapping symbol state. */ 37 enum map_type 38 { 39 MAP_INSN, 40 MAP_DATA 41 }; 42 43 static enum map_type last_type; 44 static int last_mapping_sym = -1; 45 static bfd_vma last_mapping_addr = 0; 46 47 /* Other options */ 48 static int no_aliases = 0; /* If set disassemble as most general inst. */ 49 50 52 static void 53 set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED) 54 { 55 } 56 57 static void 58 parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED) 59 { 60 /* Try to match options that are simple flags */ 61 if (CONST_STRNEQ (option, "no-aliases")) 62 { 63 no_aliases = 1; 64 return; 65 } 66 67 if (CONST_STRNEQ (option, "aliases")) 68 { 69 no_aliases = 0; 70 return; 71 } 72 73 #ifdef DEBUG_AARCH64 74 if (CONST_STRNEQ (option, "debug_dump")) 75 { 76 debug_dump = 1; 77 return; 78 } 79 #endif /* DEBUG_AARCH64 */ 80 81 /* Invalid option. */ 82 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); 83 } 84 85 static void 86 parse_aarch64_dis_options (const char *options) 87 { 88 const char *option_end; 89 90 if (options == NULL) 91 return; 92 93 while (*options != '\0') 94 { 95 /* Skip empty options. */ 96 if (*options == ',') 97 { 98 options++; 99 continue; 100 } 101 102 /* We know that *options is neither NUL or a comma. */ 103 option_end = options + 1; 104 while (*option_end != ',' && *option_end != '\0') 105 option_end++; 106 107 parse_aarch64_dis_option (options, option_end - options); 108 109 /* Go on to the next one. If option_end points to a comma, it 110 will be skipped above. */ 111 options = option_end; 112 } 113 } 114 115 /* Functions doing the instruction disassembling. */ 117 118 /* The unnamed arguments consist of the number of fields and information about 119 these fields where the VALUE will be extracted from CODE and returned. 120 MASK can be zero or the base mask of the opcode. 121 122 N.B. the fields are required to be in such an order than the most signficant 123 field for VALUE comes the first, e.g. the <index> in 124 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] 125 is encoded in H:L:M in some cases, the fields H:L:M should be passed in 126 the order of H, L, M. */ 127 128 static inline aarch64_insn 129 extract_fields (aarch64_insn code, aarch64_insn mask, ...) 130 { 131 uint32_t num; 132 const aarch64_field *field; 133 enum aarch64_field_kind kind; 134 va_list va; 135 136 va_start (va, mask); 137 num = va_arg (va, uint32_t); 138 assert (num <= 5); 139 aarch64_insn value = 0x0; 140 while (num--) 141 { 142 kind = va_arg (va, enum aarch64_field_kind); 143 field = &fields[kind]; 144 value <<= field->width; 145 value |= extract_field (kind, code, mask); 146 } 147 return value; 148 } 149 150 /* Sign-extend bit I of VALUE. */ 151 static inline int32_t 152 sign_extend (aarch64_insn value, unsigned i) 153 { 154 uint32_t ret = value; 155 156 assert (i < 32); 157 if ((value >> i) & 0x1) 158 { 159 uint32_t val = (uint32_t)(-1) << i; 160 ret = ret | val; 161 } 162 return (int32_t) ret; 163 } 164 165 /* N.B. the following inline helpfer functions create a dependency on the 166 order of operand qualifier enumerators. */ 167 168 /* Given VALUE, return qualifier for a general purpose register. */ 169 static inline enum aarch64_opnd_qualifier 170 get_greg_qualifier_from_value (aarch64_insn value) 171 { 172 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value; 173 assert (value <= 0x1 174 && aarch64_get_qualifier_standard_value (qualifier) == value); 175 return qualifier; 176 } 177 178 /* Given VALUE, return qualifier for a vector register. This does not support 179 decoding instructions that accept the 2H vector type. */ 180 181 static inline enum aarch64_opnd_qualifier 182 get_vreg_qualifier_from_value (aarch64_insn value) 183 { 184 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value; 185 186 /* Instructions using vector type 2H should not call this function. Skip over 187 the 2H qualifier. */ 188 if (qualifier >= AARCH64_OPND_QLF_V_2H) 189 qualifier += 1; 190 191 assert (value <= 0x8 192 && aarch64_get_qualifier_standard_value (qualifier) == value); 193 return qualifier; 194 } 195 196 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */ 197 static inline enum aarch64_opnd_qualifier 198 get_sreg_qualifier_from_value (aarch64_insn value) 199 { 200 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value; 201 202 assert (value <= 0x4 203 && aarch64_get_qualifier_standard_value (qualifier) == value); 204 return qualifier; 205 } 206 207 /* Given the instruction in *INST which is probably half way through the 208 decoding and our caller wants to know the expected qualifier for operand 209 I. Return such a qualifier if we can establish it; otherwise return 210 AARCH64_OPND_QLF_NIL. */ 211 212 static aarch64_opnd_qualifier_t 213 get_expected_qualifier (const aarch64_inst *inst, int i) 214 { 215 aarch64_opnd_qualifier_seq_t qualifiers; 216 /* Should not be called if the qualifier is known. */ 217 assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL); 218 if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list, 219 i, qualifiers)) 220 return qualifiers[i]; 221 else 222 return AARCH64_OPND_QLF_NIL; 223 } 224 225 /* Operand extractors. */ 226 227 int 228 aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info, 229 const aarch64_insn code, 230 const aarch64_inst *inst ATTRIBUTE_UNUSED) 231 { 232 info->reg.regno = extract_field (self->fields[0], code, 0); 233 return 1; 234 } 235 236 int 237 aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, 238 const aarch64_insn code ATTRIBUTE_UNUSED, 239 const aarch64_inst *inst ATTRIBUTE_UNUSED) 240 { 241 assert (info->idx == 1 242 || info->idx ==3); 243 info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1; 244 return 1; 245 } 246 247 /* e.g. IC <ic_op>{, <Xt>}. */ 248 int 249 aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info, 250 const aarch64_insn code, 251 const aarch64_inst *inst ATTRIBUTE_UNUSED) 252 { 253 info->reg.regno = extract_field (self->fields[0], code, 0); 254 assert (info->idx == 1 255 && (aarch64_get_operand_class (inst->operands[0].type) 256 == AARCH64_OPND_CLASS_SYSTEM)); 257 /* This will make the constraint checking happy and more importantly will 258 help the disassembler determine whether this operand is optional or 259 not. */ 260 info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op); 261 262 return 1; 263 } 264 265 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ 266 int 267 aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, 268 const aarch64_insn code, 269 const aarch64_inst *inst ATTRIBUTE_UNUSED) 270 { 271 /* regno */ 272 info->reglane.regno = extract_field (self->fields[0], code, 273 inst->opcode->mask); 274 275 /* Index and/or type. */ 276 if (inst->opcode->iclass == asisdone 277 || inst->opcode->iclass == asimdins) 278 { 279 if (info->type == AARCH64_OPND_En 280 && inst->opcode->operands[0] == AARCH64_OPND_Ed) 281 { 282 unsigned shift; 283 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */ 284 assert (info->idx == 1); /* Vn */ 285 aarch64_insn value = extract_field (FLD_imm4, code, 0); 286 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */ 287 info->qualifier = get_expected_qualifier (inst, info->idx); 288 shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); 289 info->reglane.index = value >> shift; 290 } 291 else 292 { 293 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>]. 294 imm5<3:0> <V> 295 0000 RESERVED 296 xxx1 B 297 xx10 H 298 x100 S 299 1000 D */ 300 int pos = -1; 301 aarch64_insn value = extract_field (FLD_imm5, code, 0); 302 while (++pos <= 3 && (value & 0x1) == 0) 303 value >>= 1; 304 if (pos > 3) 305 return 0; 306 info->qualifier = get_sreg_qualifier_from_value (pos); 307 info->reglane.index = (unsigned) (value >> 1); 308 } 309 } 310 else 311 { 312 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] 313 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ 314 315 /* Need information in other operand(s) to help decoding. */ 316 info->qualifier = get_expected_qualifier (inst, info->idx); 317 switch (info->qualifier) 318 { 319 case AARCH64_OPND_QLF_S_H: 320 /* h:l:m */ 321 info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, 322 FLD_M); 323 info->reglane.regno &= 0xf; 324 break; 325 case AARCH64_OPND_QLF_S_S: 326 /* h:l */ 327 info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); 328 break; 329 case AARCH64_OPND_QLF_S_D: 330 /* H */ 331 info->reglane.index = extract_field (FLD_H, code, 0); 332 break; 333 default: 334 return 0; 335 } 336 } 337 338 return 1; 339 } 340 341 int 342 aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info, 343 const aarch64_insn code, 344 const aarch64_inst *inst ATTRIBUTE_UNUSED) 345 { 346 /* R */ 347 info->reglist.first_regno = extract_field (self->fields[0], code, 0); 348 /* len */ 349 info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1; 350 return 1; 351 } 352 353 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */ 354 int 355 aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, 356 aarch64_opnd_info *info, const aarch64_insn code, 357 const aarch64_inst *inst) 358 { 359 aarch64_insn value; 360 /* Number of elements in each structure to be loaded/stored. */ 361 unsigned expected_num = get_opcode_dependent_value (inst->opcode); 362 363 struct 364 { 365 unsigned is_reserved; 366 unsigned num_regs; 367 unsigned num_elements; 368 } data [] = 369 { {0, 4, 4}, 370 {1, 4, 4}, 371 {0, 4, 1}, 372 {0, 4, 2}, 373 {0, 3, 3}, 374 {1, 3, 3}, 375 {0, 3, 1}, 376 {0, 1, 1}, 377 {0, 2, 2}, 378 {1, 2, 2}, 379 {0, 2, 1}, 380 }; 381 382 /* Rt */ 383 info->reglist.first_regno = extract_field (FLD_Rt, code, 0); 384 /* opcode */ 385 value = extract_field (FLD_opcode, code, 0); 386 if (expected_num != data[value].num_elements || data[value].is_reserved) 387 return 0; 388 info->reglist.num_regs = data[value].num_regs; 389 390 return 1; 391 } 392 393 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all 394 lanes instructions. */ 395 int 396 aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, 397 aarch64_opnd_info *info, const aarch64_insn code, 398 const aarch64_inst *inst) 399 { 400 aarch64_insn value; 401 402 /* Rt */ 403 info->reglist.first_regno = extract_field (FLD_Rt, code, 0); 404 /* S */ 405 value = extract_field (FLD_S, code, 0); 406 407 /* Number of registers is equal to the number of elements in 408 each structure to be loaded/stored. */ 409 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); 410 assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); 411 412 /* Except when it is LD1R. */ 413 if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1) 414 info->reglist.num_regs = 2; 415 416 return 1; 417 } 418 419 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD 420 load/store single element instructions. */ 421 int 422 aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, 423 aarch64_opnd_info *info, const aarch64_insn code, 424 const aarch64_inst *inst ATTRIBUTE_UNUSED) 425 { 426 aarch64_field field = {0, 0}; 427 aarch64_insn QSsize; /* fields Q:S:size. */ 428 aarch64_insn opcodeh2; /* opcode<2:1> */ 429 430 /* Rt */ 431 info->reglist.first_regno = extract_field (FLD_Rt, code, 0); 432 433 /* Decode the index, opcode<2:1> and size. */ 434 gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); 435 opcodeh2 = extract_field_2 (&field, code, 0); 436 QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size); 437 switch (opcodeh2) 438 { 439 case 0x0: 440 info->qualifier = AARCH64_OPND_QLF_S_B; 441 /* Index encoded in "Q:S:size". */ 442 info->reglist.index = QSsize; 443 break; 444 case 0x1: 445 if (QSsize & 0x1) 446 /* UND. */ 447 return 0; 448 info->qualifier = AARCH64_OPND_QLF_S_H; 449 /* Index encoded in "Q:S:size<1>". */ 450 info->reglist.index = QSsize >> 1; 451 break; 452 case 0x2: 453 if ((QSsize >> 1) & 0x1) 454 /* UND. */ 455 return 0; 456 if ((QSsize & 0x1) == 0) 457 { 458 info->qualifier = AARCH64_OPND_QLF_S_S; 459 /* Index encoded in "Q:S". */ 460 info->reglist.index = QSsize >> 2; 461 } 462 else 463 { 464 if (extract_field (FLD_S, code, 0)) 465 /* UND */ 466 return 0; 467 info->qualifier = AARCH64_OPND_QLF_S_D; 468 /* Index encoded in "Q". */ 469 info->reglist.index = QSsize >> 3; 470 } 471 break; 472 default: 473 return 0; 474 } 475 476 info->reglist.has_index = 1; 477 info->reglist.num_regs = 0; 478 /* Number of registers is equal to the number of elements in 479 each structure to be loaded/stored. */ 480 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); 481 assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); 482 483 return 1; 484 } 485 486 /* Decode fields immh:immb and/or Q for e.g. 487 SSHR <Vd>.<T>, <Vn>.<T>, #<shift> 488 or SSHR <V><d>, <V><n>, #<shift>. */ 489 490 int 491 aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, 492 aarch64_opnd_info *info, const aarch64_insn code, 493 const aarch64_inst *inst) 494 { 495 int pos; 496 aarch64_insn Q, imm, immh; 497 enum aarch64_insn_class iclass = inst->opcode->iclass; 498 499 immh = extract_field (FLD_immh, code, 0); 500 if (immh == 0) 501 return 0; 502 imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb); 503 pos = 4; 504 /* Get highest set bit in immh. */ 505 while (--pos >= 0 && (immh & 0x8) == 0) 506 immh <<= 1; 507 508 assert ((iclass == asimdshf || iclass == asisdshf) 509 && (info->type == AARCH64_OPND_IMM_VLSR 510 || info->type == AARCH64_OPND_IMM_VLSL)); 511 512 if (iclass == asimdshf) 513 { 514 Q = extract_field (FLD_Q, code, 0); 515 /* immh Q <T> 516 0000 x SEE AdvSIMD modified immediate 517 0001 0 8B 518 0001 1 16B 519 001x 0 4H 520 001x 1 8H 521 01xx 0 2S 522 01xx 1 4S 523 1xxx 0 RESERVED 524 1xxx 1 2D */ 525 info->qualifier = 526 get_vreg_qualifier_from_value ((pos << 1) | (int) Q); 527 } 528 else 529 info->qualifier = get_sreg_qualifier_from_value (pos); 530 531 if (info->type == AARCH64_OPND_IMM_VLSR) 532 /* immh <shift> 533 0000 SEE AdvSIMD modified immediate 534 0001 (16-UInt(immh:immb)) 535 001x (32-UInt(immh:immb)) 536 01xx (64-UInt(immh:immb)) 537 1xxx (128-UInt(immh:immb)) */ 538 info->imm.value = (16 << pos) - imm; 539 else 540 /* immh:immb 541 immh <shift> 542 0000 SEE AdvSIMD modified immediate 543 0001 (UInt(immh:immb)-8) 544 001x (UInt(immh:immb)-16) 545 01xx (UInt(immh:immb)-32) 546 1xxx (UInt(immh:immb)-64) */ 547 info->imm.value = imm - (8 << pos); 548 549 return 1; 550 } 551 552 /* Decode shift immediate for e.g. sshr (imm). */ 553 int 554 aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, 555 aarch64_opnd_info *info, const aarch64_insn code, 556 const aarch64_inst *inst ATTRIBUTE_UNUSED) 557 { 558 int64_t imm; 559 aarch64_insn val; 560 val = extract_field (FLD_size, code, 0); 561 switch (val) 562 { 563 case 0: imm = 8; break; 564 case 1: imm = 16; break; 565 case 2: imm = 32; break; 566 default: return 0; 567 } 568 info->imm.value = imm; 569 return 1; 570 } 571 572 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. 573 value in the field(s) will be extracted as unsigned immediate value. */ 574 int 575 aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, 576 const aarch64_insn code, 577 const aarch64_inst *inst ATTRIBUTE_UNUSED) 578 { 579 int64_t imm; 580 /* Maximum of two fields to extract. */ 581 assert (self->fields[2] == FLD_NIL); 582 583 if (self->fields[1] == FLD_NIL) 584 imm = extract_field (self->fields[0], code, 0); 585 else 586 /* e.g. TBZ b5:b40. */ 587 imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]); 588 589 if (info->type == AARCH64_OPND_FPIMM) 590 info->imm.is_fp = 1; 591 592 if (operand_need_sign_extension (self)) 593 imm = sign_extend (imm, get_operand_fields_width (self) - 1); 594 595 if (operand_need_shift_by_two (self)) 596 imm <<= 2; 597 598 if (info->type == AARCH64_OPND_ADDR_ADRP) 599 imm <<= 12; 600 601 info->imm.value = imm; 602 return 1; 603 } 604 605 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */ 606 int 607 aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info, 608 const aarch64_insn code, 609 const aarch64_inst *inst ATTRIBUTE_UNUSED) 610 { 611 aarch64_ext_imm (self, info, code, inst); 612 info->shifter.kind = AARCH64_MOD_LSL; 613 info->shifter.amount = extract_field (FLD_hw, code, 0) << 4; 614 return 1; 615 } 616 617 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g. 618 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */ 619 int 620 aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, 621 aarch64_opnd_info *info, 622 const aarch64_insn code, 623 const aarch64_inst *inst ATTRIBUTE_UNUSED) 624 { 625 uint64_t imm; 626 enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier; 627 aarch64_field field = {0, 0}; 628 629 assert (info->idx == 1); 630 631 if (info->type == AARCH64_OPND_SIMD_FPIMM) 632 info->imm.is_fp = 1; 633 634 /* a:b:c:d:e:f:g:h */ 635 imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh); 636 if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8) 637 { 638 /* Either MOVI <Dd>, #<imm> 639 or MOVI <Vd>.2D, #<imm>. 640 <imm> is a 64-bit immediate 641 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', 642 encoded in "a:b:c:d:e:f:g:h". */ 643 int i; 644 unsigned abcdefgh = imm; 645 for (imm = 0ull, i = 0; i < 8; i++) 646 if (((abcdefgh >> i) & 0x1) != 0) 647 imm |= 0xffull << (8 * i); 648 } 649 info->imm.value = imm; 650 651 /* cmode */ 652 info->qualifier = get_expected_qualifier (inst, info->idx); 653 switch (info->qualifier) 654 { 655 case AARCH64_OPND_QLF_NIL: 656 /* no shift */ 657 info->shifter.kind = AARCH64_MOD_NONE; 658 return 1; 659 case AARCH64_OPND_QLF_LSL: 660 /* shift zeros */ 661 info->shifter.kind = AARCH64_MOD_LSL; 662 switch (aarch64_get_qualifier_esize (opnd0_qualifier)) 663 { 664 case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ 665 case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ 666 case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ 667 default: assert (0); return 0; 668 } 669 /* 00: 0; 01: 8; 10:16; 11:24. */ 670 info->shifter.amount = extract_field_2 (&field, code, 0) << 3; 671 break; 672 case AARCH64_OPND_QLF_MSL: 673 /* shift ones */ 674 info->shifter.kind = AARCH64_MOD_MSL; 675 gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ 676 info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8; 677 break; 678 default: 679 assert (0); 680 return 0; 681 } 682 683 return 1; 684 } 685 686 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ 687 int 688 aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, 689 aarch64_opnd_info *info, const aarch64_insn code, 690 const aarch64_inst *inst ATTRIBUTE_UNUSED) 691 { 692 info->imm.value = 64- extract_field (FLD_scale, code, 0); 693 return 1; 694 } 695 696 /* Decode arithmetic immediate for e.g. 697 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */ 698 int 699 aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, 700 aarch64_opnd_info *info, const aarch64_insn code, 701 const aarch64_inst *inst ATTRIBUTE_UNUSED) 702 { 703 aarch64_insn value; 704 705 info->shifter.kind = AARCH64_MOD_LSL; 706 /* shift */ 707 value = extract_field (FLD_shift, code, 0); 708 if (value >= 2) 709 return 0; 710 info->shifter.amount = value ? 12 : 0; 711 /* imm12 (unsigned) */ 712 info->imm.value = extract_field (FLD_imm12, code, 0); 713 714 return 1; 715 } 716 717 /* Decode logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */ 718 719 int 720 aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED, 721 aarch64_opnd_info *info, const aarch64_insn code, 722 const aarch64_inst *inst ATTRIBUTE_UNUSED) 723 { 724 uint64_t imm, mask; 725 uint32_t sf; 726 uint32_t N, R, S; 727 unsigned simd_size; 728 aarch64_insn value; 729 730 value = extract_fields (code, 0, 3, FLD_N, FLD_immr, FLD_imms); 731 assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_W 732 || inst->operands[0].qualifier == AARCH64_OPND_QLF_X); 733 sf = aarch64_get_qualifier_esize (inst->operands[0].qualifier) != 4; 734 735 /* value is N:immr:imms. */ 736 S = value & 0x3f; 737 R = (value >> 6) & 0x3f; 738 N = (value >> 12) & 0x1; 739 740 if (sf == 0 && N == 1) 741 return 0; 742 743 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R 744 (in other words, right rotated by R), then replicated. */ 745 if (N != 0) 746 { 747 simd_size = 64; 748 mask = 0xffffffffffffffffull; 749 } 750 else 751 { 752 switch (S) 753 { 754 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break; 755 case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break; 756 case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break; 757 case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break; 758 case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break; 759 default: return 0; 760 } 761 mask = (1ull << simd_size) - 1; 762 /* Top bits are IGNORED. */ 763 R &= simd_size - 1; 764 } 765 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */ 766 if (S == simd_size - 1) 767 return 0; 768 /* S+1 consecutive bits to 1. */ 769 /* NOTE: S can't be 63 due to detection above. */ 770 imm = (1ull << (S + 1)) - 1; 771 /* Rotate to the left by simd_size - R. */ 772 if (R != 0) 773 imm = ((imm << (simd_size - R)) & mask) | (imm >> R); 774 /* Replicate the value according to SIMD size. */ 775 switch (simd_size) 776 { 777 case 2: imm = (imm << 2) | imm; 778 case 4: imm = (imm << 4) | imm; 779 case 8: imm = (imm << 8) | imm; 780 case 16: imm = (imm << 16) | imm; 781 case 32: imm = (imm << 32) | imm; 782 case 64: break; 783 default: assert (0); return 0; 784 } 785 786 info->imm.value = sf ? imm : imm & 0xffffffff; 787 788 return 1; 789 } 790 791 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}] 792 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */ 793 int 794 aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, 795 aarch64_opnd_info *info, 796 const aarch64_insn code, const aarch64_inst *inst) 797 { 798 aarch64_insn value; 799 800 /* Rt */ 801 info->reg.regno = extract_field (FLD_Rt, code, 0); 802 803 /* size */ 804 value = extract_field (FLD_ldst_size, code, 0); 805 if (inst->opcode->iclass == ldstpair_indexed 806 || inst->opcode->iclass == ldstnapair_offs 807 || inst->opcode->iclass == ldstpair_off 808 || inst->opcode->iclass == loadlit) 809 { 810 enum aarch64_opnd_qualifier qualifier; 811 switch (value) 812 { 813 case 0: qualifier = AARCH64_OPND_QLF_S_S; break; 814 case 1: qualifier = AARCH64_OPND_QLF_S_D; break; 815 case 2: qualifier = AARCH64_OPND_QLF_S_Q; break; 816 default: return 0; 817 } 818 info->qualifier = qualifier; 819 } 820 else 821 { 822 /* opc1:size */ 823 value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size); 824 if (value > 0x4) 825 return 0; 826 info->qualifier = get_sreg_qualifier_from_value (value); 827 } 828 829 return 1; 830 } 831 832 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ 833 int 834 aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, 835 aarch64_opnd_info *info, 836 aarch64_insn code, 837 const aarch64_inst *inst ATTRIBUTE_UNUSED) 838 { 839 /* Rn */ 840 info->addr.base_regno = extract_field (FLD_Rn, code, 0); 841 return 1; 842 } 843 844 /* Decode the address operand for e.g. 845 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 846 int 847 aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, 848 aarch64_opnd_info *info, 849 aarch64_insn code, const aarch64_inst *inst) 850 { 851 aarch64_insn S, value; 852 853 /* Rn */ 854 info->addr.base_regno = extract_field (FLD_Rn, code, 0); 855 /* Rm */ 856 info->addr.offset.regno = extract_field (FLD_Rm, code, 0); 857 /* option */ 858 value = extract_field (FLD_option, code, 0); 859 info->shifter.kind = 860 aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); 861 /* Fix-up the shifter kind; although the table-driven approach is 862 efficient, it is slightly inflexible, thus needing this fix-up. */ 863 if (info->shifter.kind == AARCH64_MOD_UXTX) 864 info->shifter.kind = AARCH64_MOD_LSL; 865 /* S */ 866 S = extract_field (FLD_S, code, 0); 867 if (S == 0) 868 { 869 info->shifter.amount = 0; 870 info->shifter.amount_present = 0; 871 } 872 else 873 { 874 int size; 875 /* Need information in other operand(s) to help achieve the decoding 876 from 'S' field. */ 877 info->qualifier = get_expected_qualifier (inst, info->idx); 878 /* Get the size of the data element that is accessed, which may be 879 different from that of the source register size, e.g. in strb/ldrb. */ 880 size = aarch64_get_qualifier_esize (info->qualifier); 881 info->shifter.amount = get_logsz (size); 882 info->shifter.amount_present = 1; 883 } 884 885 return 1; 886 } 887 888 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */ 889 int 890 aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, 891 aarch64_insn code, const aarch64_inst *inst) 892 { 893 aarch64_insn imm; 894 info->qualifier = get_expected_qualifier (inst, info->idx); 895 896 /* Rn */ 897 info->addr.base_regno = extract_field (FLD_Rn, code, 0); 898 /* simm (imm9 or imm7) */ 899 imm = extract_field (self->fields[0], code, 0); 900 info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1); 901 if (self->fields[0] == FLD_imm7) 902 /* scaled immediate in ld/st pair instructions. */ 903 info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); 904 /* qualifier */ 905 if (inst->opcode->iclass == ldst_unscaled 906 || inst->opcode->iclass == ldstnapair_offs 907 || inst->opcode->iclass == ldstpair_off 908 || inst->opcode->iclass == ldst_unpriv) 909 info->addr.writeback = 0; 910 else 911 { 912 /* pre/post- index */ 913 info->addr.writeback = 1; 914 if (extract_field (self->fields[1], code, 0) == 1) 915 info->addr.preind = 1; 916 else 917 info->addr.postind = 1; 918 } 919 920 return 1; 921 } 922 923 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */ 924 int 925 aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, 926 aarch64_insn code, 927 const aarch64_inst *inst ATTRIBUTE_UNUSED) 928 { 929 int shift; 930 info->qualifier = get_expected_qualifier (inst, info->idx); 931 shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); 932 /* Rn */ 933 info->addr.base_regno = extract_field (self->fields[0], code, 0); 934 /* uimm12 */ 935 info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift; 936 return 1; 937 } 938 939 /* Decode the address operand for e.g. 940 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */ 941 int 942 aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, 943 aarch64_opnd_info *info, 944 aarch64_insn code, const aarch64_inst *inst) 945 { 946 /* The opcode dependent area stores the number of elements in 947 each structure to be loaded/stored. */ 948 int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1; 949 950 /* Rn */ 951 info->addr.base_regno = extract_field (FLD_Rn, code, 0); 952 /* Rm | #<amount> */ 953 info->addr.offset.regno = extract_field (FLD_Rm, code, 0); 954 if (info->addr.offset.regno == 31) 955 { 956 if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL) 957 /* Special handling of loading single structure to all lane. */ 958 info->addr.offset.imm = (is_ld1r ? 1 959 : inst->operands[0].reglist.num_regs) 960 * aarch64_get_qualifier_esize (inst->operands[0].qualifier); 961 else 962 info->addr.offset.imm = inst->operands[0].reglist.num_regs 963 * aarch64_get_qualifier_esize (inst->operands[0].qualifier) 964 * aarch64_get_qualifier_nelem (inst->operands[0].qualifier); 965 } 966 else 967 info->addr.offset.is_reg = 1; 968 info->addr.writeback = 1; 969 970 return 1; 971 } 972 973 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */ 974 int 975 aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, 976 aarch64_opnd_info *info, 977 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED) 978 { 979 aarch64_insn value; 980 /* cond */ 981 value = extract_field (FLD_cond, code, 0); 982 info->cond = get_cond_from_value (value); 983 return 1; 984 } 985 986 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */ 987 int 988 aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, 989 aarch64_opnd_info *info, 990 aarch64_insn code, 991 const aarch64_inst *inst ATTRIBUTE_UNUSED) 992 { 993 /* op0:op1:CRn:CRm:op2 */ 994 info->sysreg = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, 995 FLD_CRm, FLD_op2); 996 return 1; 997 } 998 999 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */ 1000 int 1001 aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, 1002 aarch64_opnd_info *info, aarch64_insn code, 1003 const aarch64_inst *inst ATTRIBUTE_UNUSED) 1004 { 1005 int i; 1006 /* op1:op2 */ 1007 info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); 1008 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) 1009 if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) 1010 return 1; 1011 /* Reserved value in <pstatefield>. */ 1012 return 0; 1013 } 1014 1015 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */ 1016 int 1017 aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, 1018 aarch64_opnd_info *info, 1019 aarch64_insn code, 1020 const aarch64_inst *inst ATTRIBUTE_UNUSED) 1021 { 1022 int i; 1023 aarch64_insn value; 1024 const aarch64_sys_ins_reg *sysins_ops; 1025 /* op0:op1:CRn:CRm:op2 */ 1026 value = extract_fields (code, 0, 5, 1027 FLD_op0, FLD_op1, FLD_CRn, 1028 FLD_CRm, FLD_op2); 1029 1030 switch (info->type) 1031 { 1032 case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break; 1033 case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break; 1034 case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break; 1035 case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break; 1036 default: assert (0); return 0; 1037 } 1038 1039 for (i = 0; sysins_ops[i].name != NULL; ++i) 1040 if (sysins_ops[i].value == value) 1041 { 1042 info->sysins_op = sysins_ops + i; 1043 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.", 1044 info->sysins_op->name, 1045 (unsigned)info->sysins_op->value, 1046 aarch64_sys_ins_reg_has_xt (info->sysins_op), i); 1047 return 1; 1048 } 1049 1050 return 0; 1051 } 1052 1053 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */ 1054 1055 int 1056 aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED, 1057 aarch64_opnd_info *info, 1058 aarch64_insn code, 1059 const aarch64_inst *inst ATTRIBUTE_UNUSED) 1060 { 1061 /* CRm */ 1062 info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0); 1063 return 1; 1064 } 1065 1066 /* Decode the prefetch operation option operand for e.g. 1067 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ 1068 1069 int 1070 aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED, 1071 aarch64_opnd_info *info, 1072 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED) 1073 { 1074 /* prfop in Rt */ 1075 info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0); 1076 return 1; 1077 } 1078 1079 /* Decode the hint number for an alias taking an operand. Set info->hint_option 1080 to the matching name/value pair in aarch64_hint_options. */ 1081 1082 int 1083 aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, 1084 aarch64_opnd_info *info, 1085 aarch64_insn code, 1086 const aarch64_inst *inst ATTRIBUTE_UNUSED) 1087 { 1088 /* CRm:op2. */ 1089 unsigned hint_number; 1090 int i; 1091 1092 hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2); 1093 1094 for (i = 0; aarch64_hint_options[i].name != NULL; i++) 1095 { 1096 if (hint_number == aarch64_hint_options[i].value) 1097 { 1098 info->hint_option = &(aarch64_hint_options[i]); 1099 return 1; 1100 } 1101 } 1102 1103 return 0; 1104 } 1105 1106 /* Decode the extended register operand for e.g. 1107 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1108 int 1109 aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, 1110 aarch64_opnd_info *info, 1111 aarch64_insn code, 1112 const aarch64_inst *inst ATTRIBUTE_UNUSED) 1113 { 1114 aarch64_insn value; 1115 1116 /* Rm */ 1117 info->reg.regno = extract_field (FLD_Rm, code, 0); 1118 /* option */ 1119 value = extract_field (FLD_option, code, 0); 1120 info->shifter.kind = 1121 aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); 1122 /* imm3 */ 1123 info->shifter.amount = extract_field (FLD_imm3, code, 0); 1124 1125 /* This makes the constraint checking happy. */ 1126 info->shifter.operator_present = 1; 1127 1128 /* Assume inst->operands[0].qualifier has been resolved. */ 1129 assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL); 1130 info->qualifier = AARCH64_OPND_QLF_W; 1131 if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X 1132 && (info->shifter.kind == AARCH64_MOD_UXTX 1133 || info->shifter.kind == AARCH64_MOD_SXTX)) 1134 info->qualifier = AARCH64_OPND_QLF_X; 1135 1136 return 1; 1137 } 1138 1139 /* Decode the shifted register operand for e.g. 1140 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */ 1141 int 1142 aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, 1143 aarch64_opnd_info *info, 1144 aarch64_insn code, 1145 const aarch64_inst *inst ATTRIBUTE_UNUSED) 1146 { 1147 aarch64_insn value; 1148 1149 /* Rm */ 1150 info->reg.regno = extract_field (FLD_Rm, code, 0); 1151 /* shift */ 1152 value = extract_field (FLD_shift, code, 0); 1153 info->shifter.kind = 1154 aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */); 1155 if (info->shifter.kind == AARCH64_MOD_ROR 1156 && inst->opcode->iclass != log_shift) 1157 /* ROR is not available for the shifted register operand in arithmetic 1158 instructions. */ 1159 return 0; 1160 /* imm6 */ 1161 info->shifter.amount = extract_field (FLD_imm6, code, 0); 1162 1163 /* This makes the constraint checking happy. */ 1164 info->shifter.operator_present = 1; 1165 1166 return 1; 1167 } 1168 1169 /* Bitfields that are commonly used to encode certain operands' information 1171 may be partially used as part of the base opcode in some instructions. 1172 For example, the bit 1 of the field 'size' in 1173 FCVTXN <Vb><d>, <Va><n> 1174 is actually part of the base opcode, while only size<0> is available 1175 for encoding the register type. Another example is the AdvSIMD 1176 instruction ORR (register), in which the field 'size' is also used for 1177 the base opcode, leaving only the field 'Q' available to encode the 1178 vector register arrangement specifier '8B' or '16B'. 1179 1180 This function tries to deduce the qualifier from the value of partially 1181 constrained field(s). Given the VALUE of such a field or fields, the 1182 qualifiers CANDIDATES and the MASK (indicating which bits are valid for 1183 operand encoding), the function returns the matching qualifier or 1184 AARCH64_OPND_QLF_NIL if nothing matches. 1185 1186 N.B. CANDIDATES is a group of possible qualifiers that are valid for 1187 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and 1188 may end with AARCH64_OPND_QLF_NIL. */ 1189 1190 static enum aarch64_opnd_qualifier 1191 get_qualifier_from_partial_encoding (aarch64_insn value, 1192 const enum aarch64_opnd_qualifier* \ 1193 candidates, 1194 aarch64_insn mask) 1195 { 1196 int i; 1197 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask); 1198 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) 1199 { 1200 aarch64_insn standard_value; 1201 if (candidates[i] == AARCH64_OPND_QLF_NIL) 1202 break; 1203 standard_value = aarch64_get_qualifier_standard_value (candidates[i]); 1204 if ((standard_value & mask) == (value & mask)) 1205 return candidates[i]; 1206 } 1207 return AARCH64_OPND_QLF_NIL; 1208 } 1209 1210 /* Given a list of qualifier sequences, return all possible valid qualifiers 1211 for operand IDX in QUALIFIERS. 1212 Assume QUALIFIERS is an array whose length is large enough. */ 1213 1214 static void 1215 get_operand_possible_qualifiers (int idx, 1216 const aarch64_opnd_qualifier_seq_t *list, 1217 enum aarch64_opnd_qualifier *qualifiers) 1218 { 1219 int i; 1220 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) 1221 if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL) 1222 break; 1223 } 1224 1225 /* Decode the size Q field for e.g. SHADD. 1226 We tag one operand with the qualifer according to the code; 1227 whether the qualifier is valid for this opcode or not, it is the 1228 duty of the semantic checking. */ 1229 1230 static int 1231 decode_sizeq (aarch64_inst *inst) 1232 { 1233 int idx; 1234 enum aarch64_opnd_qualifier qualifier; 1235 aarch64_insn code; 1236 aarch64_insn value, mask; 1237 enum aarch64_field_kind fld_sz; 1238 enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; 1239 1240 if (inst->opcode->iclass == asisdlse 1241 || inst->opcode->iclass == asisdlsep 1242 || inst->opcode->iclass == asisdlso 1243 || inst->opcode->iclass == asisdlsop) 1244 fld_sz = FLD_vldst_size; 1245 else 1246 fld_sz = FLD_size; 1247 1248 code = inst->value; 1249 value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q); 1250 /* Obtain the info that which bits of fields Q and size are actually 1251 available for operand encoding. Opcodes like FMAXNM and FMLA have 1252 size[1] unavailable. */ 1253 mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q); 1254 1255 /* The index of the operand we are going to tag a qualifier and the qualifer 1256 itself are reasoned from the value of the size and Q fields and the 1257 possible valid qualifier lists. */ 1258 idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode); 1259 DEBUG_TRACE ("key idx: %d", idx); 1260 1261 /* For most related instruciton, size:Q are fully available for operand 1262 encoding. */ 1263 if (mask == 0x7) 1264 { 1265 inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value); 1266 return 1; 1267 } 1268 1269 get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, 1270 candidates); 1271 #ifdef DEBUG_AARCH64 1272 if (debug_dump) 1273 { 1274 int i; 1275 for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL 1276 && i < AARCH64_MAX_QLF_SEQ_NUM; ++i) 1277 DEBUG_TRACE ("qualifier %d: %s", i, 1278 aarch64_get_qualifier_name(candidates[i])); 1279 DEBUG_TRACE ("%d, %d", (int)value, (int)mask); 1280 } 1281 #endif /* DEBUG_AARCH64 */ 1282 1283 qualifier = get_qualifier_from_partial_encoding (value, candidates, mask); 1284 1285 if (qualifier == AARCH64_OPND_QLF_NIL) 1286 return 0; 1287 1288 inst->operands[idx].qualifier = qualifier; 1289 return 1; 1290 } 1291 1292 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for 1293 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 1294 1295 static int 1296 decode_asimd_fcvt (aarch64_inst *inst) 1297 { 1298 aarch64_field field = {0, 0}; 1299 aarch64_insn value; 1300 enum aarch64_opnd_qualifier qualifier; 1301 1302 gen_sub_field (FLD_size, 0, 1, &field); 1303 value = extract_field_2 (&field, inst->value, 0); 1304 qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S 1305 : AARCH64_OPND_QLF_V_2D; 1306 switch (inst->opcode->op) 1307 { 1308 case OP_FCVTN: 1309 case OP_FCVTN2: 1310 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 1311 inst->operands[1].qualifier = qualifier; 1312 break; 1313 case OP_FCVTL: 1314 case OP_FCVTL2: 1315 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ 1316 inst->operands[0].qualifier = qualifier; 1317 break; 1318 default: 1319 assert (0); 1320 return 0; 1321 } 1322 1323 return 1; 1324 } 1325 1326 /* Decode size[0], i.e. bit 22, for 1327 e.g. FCVTXN <Vb><d>, <Va><n>. */ 1328 1329 static int 1330 decode_asisd_fcvtxn (aarch64_inst *inst) 1331 { 1332 aarch64_field field = {0, 0}; 1333 gen_sub_field (FLD_size, 0, 1, &field); 1334 if (!extract_field_2 (&field, inst->value, 0)) 1335 return 0; 1336 inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S; 1337 return 1; 1338 } 1339 1340 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */ 1341 static int 1342 decode_fcvt (aarch64_inst *inst) 1343 { 1344 enum aarch64_opnd_qualifier qualifier; 1345 aarch64_insn value; 1346 const aarch64_field field = {15, 2}; 1347 1348 /* opc dstsize */ 1349 value = extract_field_2 (&field, inst->value, 0); 1350 switch (value) 1351 { 1352 case 0: qualifier = AARCH64_OPND_QLF_S_S; break; 1353 case 1: qualifier = AARCH64_OPND_QLF_S_D; break; 1354 case 3: qualifier = AARCH64_OPND_QLF_S_H; break; 1355 default: return 0; 1356 } 1357 inst->operands[0].qualifier = qualifier; 1358 1359 return 1; 1360 } 1361 1362 /* Do miscellaneous decodings that are not common enough to be driven by 1363 flags. */ 1364 1365 static int 1366 do_misc_decoding (aarch64_inst *inst) 1367 { 1368 switch (inst->opcode->op) 1369 { 1370 case OP_FCVT: 1371 return decode_fcvt (inst); 1372 case OP_FCVTN: 1373 case OP_FCVTN2: 1374 case OP_FCVTL: 1375 case OP_FCVTL2: 1376 return decode_asimd_fcvt (inst); 1377 case OP_FCVTXN_S: 1378 return decode_asisd_fcvtxn (inst); 1379 default: 1380 return 0; 1381 } 1382 } 1383 1384 /* Opcodes that have fields shared by multiple operands are usually flagged 1385 with flags. In this function, we detect such flags, decode the related 1386 field(s) and store the information in one of the related operands. The 1387 'one' operand is not any operand but one of the operands that can 1388 accommadate all the information that has been decoded. */ 1389 1390 static int 1391 do_special_decoding (aarch64_inst *inst) 1392 { 1393 int idx; 1394 aarch64_insn value; 1395 /* Condition for truly conditional executed instructions, e.g. b.cond. */ 1396 if (inst->opcode->flags & F_COND) 1397 { 1398 value = extract_field (FLD_cond2, inst->value, 0); 1399 inst->cond = get_cond_from_value (value); 1400 } 1401 /* 'sf' field. */ 1402 if (inst->opcode->flags & F_SF) 1403 { 1404 idx = select_operand_for_sf_field_coding (inst->opcode); 1405 value = extract_field (FLD_sf, inst->value, 0); 1406 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); 1407 if ((inst->opcode->flags & F_N) 1408 && extract_field (FLD_N, inst->value, 0) != value) 1409 return 0; 1410 } 1411 /* 'sf' field. */ 1412 if (inst->opcode->flags & F_LSE_SZ) 1413 { 1414 idx = select_operand_for_sf_field_coding (inst->opcode); 1415 value = extract_field (FLD_lse_sz, inst->value, 0); 1416 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); 1417 } 1418 /* size:Q fields. */ 1419 if (inst->opcode->flags & F_SIZEQ) 1420 return decode_sizeq (inst); 1421 1422 if (inst->opcode->flags & F_FPTYPE) 1423 { 1424 idx = select_operand_for_fptype_field_coding (inst->opcode); 1425 value = extract_field (FLD_type, inst->value, 0); 1426 switch (value) 1427 { 1428 case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break; 1429 case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break; 1430 case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break; 1431 default: return 0; 1432 } 1433 } 1434 1435 if (inst->opcode->flags & F_SSIZE) 1436 { 1437 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part 1438 of the base opcode. */ 1439 aarch64_insn mask; 1440 enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; 1441 idx = select_operand_for_scalar_size_field_coding (inst->opcode); 1442 value = extract_field (FLD_size, inst->value, inst->opcode->mask); 1443 mask = extract_field (FLD_size, ~inst->opcode->mask, 0); 1444 /* For most related instruciton, the 'size' field is fully available for 1445 operand encoding. */ 1446 if (mask == 0x3) 1447 inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value); 1448 else 1449 { 1450 get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, 1451 candidates); 1452 inst->operands[idx].qualifier 1453 = get_qualifier_from_partial_encoding (value, candidates, mask); 1454 } 1455 } 1456 1457 if (inst->opcode->flags & F_T) 1458 { 1459 /* Num of consecutive '0's on the right side of imm5<3:0>. */ 1460 int num = 0; 1461 unsigned val, Q; 1462 assert (aarch64_get_operand_class (inst->opcode->operands[0]) 1463 == AARCH64_OPND_CLASS_SIMD_REG); 1464 /* imm5<3:0> q <t> 1465 0000 x reserved 1466 xxx1 0 8b 1467 xxx1 1 16b 1468 xx10 0 4h 1469 xx10 1 8h 1470 x100 0 2s 1471 x100 1 4s 1472 1000 0 reserved 1473 1000 1 2d */ 1474 val = extract_field (FLD_imm5, inst->value, 0); 1475 while ((val & 0x1) == 0 && ++num <= 3) 1476 val >>= 1; 1477 if (num > 3) 1478 return 0; 1479 Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask); 1480 inst->operands[0].qualifier = 1481 get_vreg_qualifier_from_value ((num << 1) | Q); 1482 } 1483 1484 if (inst->opcode->flags & F_GPRSIZE_IN_Q) 1485 { 1486 /* Use Rt to encode in the case of e.g. 1487 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ 1488 idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt); 1489 if (idx == -1) 1490 { 1491 /* Otherwise use the result operand, which has to be a integer 1492 register. */ 1493 assert (aarch64_get_operand_class (inst->opcode->operands[0]) 1494 == AARCH64_OPND_CLASS_INT_REG); 1495 idx = 0; 1496 } 1497 assert (idx == 0 || idx == 1); 1498 value = extract_field (FLD_Q, inst->value, 0); 1499 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); 1500 } 1501 1502 if (inst->opcode->flags & F_LDS_SIZE) 1503 { 1504 aarch64_field field = {0, 0}; 1505 assert (aarch64_get_operand_class (inst->opcode->operands[0]) 1506 == AARCH64_OPND_CLASS_INT_REG); 1507 gen_sub_field (FLD_opc, 0, 1, &field); 1508 value = extract_field_2 (&field, inst->value, 0); 1509 inst->operands[0].qualifier 1510 = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; 1511 } 1512 1513 /* Miscellaneous decoding; done as the last step. */ 1514 if (inst->opcode->flags & F_MISC) 1515 return do_misc_decoding (inst); 1516 1517 return 1; 1518 } 1519 1520 /* Converters converting a real opcode instruction to its alias form. */ 1521 1522 /* ROR <Wd>, <Ws>, #<shift> 1523 is equivalent to: 1524 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */ 1525 static int 1526 convert_extr_to_ror (aarch64_inst *inst) 1527 { 1528 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) 1529 { 1530 copy_operand_info (inst, 2, 3); 1531 inst->operands[3].type = AARCH64_OPND_NIL; 1532 return 1; 1533 } 1534 return 0; 1535 } 1536 1537 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb> 1538 is equivalent to: 1539 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */ 1540 static int 1541 convert_shll_to_xtl (aarch64_inst *inst) 1542 { 1543 if (inst->operands[2].imm.value == 0) 1544 { 1545 inst->operands[2].type = AARCH64_OPND_NIL; 1546 return 1; 1547 } 1548 return 0; 1549 } 1550 1551 /* Convert 1552 UBFM <Xd>, <Xn>, #<shift>, #63. 1553 to 1554 LSR <Xd>, <Xn>, #<shift>. */ 1555 static int 1556 convert_bfm_to_sr (aarch64_inst *inst) 1557 { 1558 int64_t imms, val; 1559 1560 imms = inst->operands[3].imm.value; 1561 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; 1562 if (imms == val) 1563 { 1564 inst->operands[3].type = AARCH64_OPND_NIL; 1565 return 1; 1566 } 1567 1568 return 0; 1569 } 1570 1571 /* Convert MOV to ORR. */ 1572 static int 1573 convert_orr_to_mov (aarch64_inst *inst) 1574 { 1575 /* MOV <Vd>.<T>, <Vn>.<T> 1576 is equivalent to: 1577 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */ 1578 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) 1579 { 1580 inst->operands[2].type = AARCH64_OPND_NIL; 1581 return 1; 1582 } 1583 return 0; 1584 } 1585 1586 /* When <imms> >= <immr>, the instruction written: 1587 SBFX <Xd>, <Xn>, #<lsb>, #<width> 1588 is equivalent to: 1589 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */ 1590 1591 static int 1592 convert_bfm_to_bfx (aarch64_inst *inst) 1593 { 1594 int64_t immr, imms; 1595 1596 immr = inst->operands[2].imm.value; 1597 imms = inst->operands[3].imm.value; 1598 if (imms >= immr) 1599 { 1600 int64_t lsb = immr; 1601 inst->operands[2].imm.value = lsb; 1602 inst->operands[3].imm.value = imms + 1 - lsb; 1603 /* The two opcodes have different qualifiers for 1604 the immediate operands; reset to help the checking. */ 1605 reset_operand_qualifier (inst, 2); 1606 reset_operand_qualifier (inst, 3); 1607 return 1; 1608 } 1609 1610 return 0; 1611 } 1612 1613 /* When <imms> < <immr>, the instruction written: 1614 SBFIZ <Xd>, <Xn>, #<lsb>, #<width> 1615 is equivalent to: 1616 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */ 1617 1618 static int 1619 convert_bfm_to_bfi (aarch64_inst *inst) 1620 { 1621 int64_t immr, imms, val; 1622 1623 immr = inst->operands[2].imm.value; 1624 imms = inst->operands[3].imm.value; 1625 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; 1626 if (imms < immr) 1627 { 1628 inst->operands[2].imm.value = (val - immr) & (val - 1); 1629 inst->operands[3].imm.value = imms + 1; 1630 /* The two opcodes have different qualifiers for 1631 the immediate operands; reset to help the checking. */ 1632 reset_operand_qualifier (inst, 2); 1633 reset_operand_qualifier (inst, 3); 1634 return 1; 1635 } 1636 1637 return 0; 1638 } 1639 1640 /* The instruction written: 1641 BFC <Xd>, #<lsb>, #<width> 1642 is equivalent to: 1643 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */ 1644 1645 static int 1646 convert_bfm_to_bfc (aarch64_inst *inst) 1647 { 1648 int64_t immr, imms, val; 1649 1650 /* Should have been assured by the base opcode value. */ 1651 assert (inst->operands[1].reg.regno == 0x1f); 1652 1653 immr = inst->operands[2].imm.value; 1654 imms = inst->operands[3].imm.value; 1655 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; 1656 if (imms < immr) 1657 { 1658 /* Drop XZR from the second operand. */ 1659 copy_operand_info (inst, 1, 2); 1660 copy_operand_info (inst, 2, 3); 1661 inst->operands[3].type = AARCH64_OPND_NIL; 1662 1663 /* Recalculate the immediates. */ 1664 inst->operands[1].imm.value = (val - immr) & (val - 1); 1665 inst->operands[2].imm.value = imms + 1; 1666 1667 /* The two opcodes have different qualifiers for the operands; reset to 1668 help the checking. */ 1669 reset_operand_qualifier (inst, 1); 1670 reset_operand_qualifier (inst, 2); 1671 reset_operand_qualifier (inst, 3); 1672 1673 return 1; 1674 } 1675 1676 return 0; 1677 } 1678 1679 /* The instruction written: 1680 LSL <Xd>, <Xn>, #<shift> 1681 is equivalent to: 1682 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */ 1683 1684 static int 1685 convert_ubfm_to_lsl (aarch64_inst *inst) 1686 { 1687 int64_t immr = inst->operands[2].imm.value; 1688 int64_t imms = inst->operands[3].imm.value; 1689 int64_t val 1690 = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; 1691 1692 if ((immr == 0 && imms == val) || immr == imms + 1) 1693 { 1694 inst->operands[3].type = AARCH64_OPND_NIL; 1695 inst->operands[2].imm.value = val - imms; 1696 return 1; 1697 } 1698 1699 return 0; 1700 } 1701 1702 /* CINC <Wd>, <Wn>, <cond> 1703 is equivalent to: 1704 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>) 1705 where <cond> is not AL or NV. */ 1706 1707 static int 1708 convert_from_csel (aarch64_inst *inst) 1709 { 1710 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno 1711 && (inst->operands[3].cond->value & 0xe) != 0xe) 1712 { 1713 copy_operand_info (inst, 2, 3); 1714 inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond); 1715 inst->operands[3].type = AARCH64_OPND_NIL; 1716 return 1; 1717 } 1718 return 0; 1719 } 1720 1721 /* CSET <Wd>, <cond> 1722 is equivalent to: 1723 CSINC <Wd>, WZR, WZR, invert(<cond>) 1724 where <cond> is not AL or NV. */ 1725 1726 static int 1727 convert_csinc_to_cset (aarch64_inst *inst) 1728 { 1729 if (inst->operands[1].reg.regno == 0x1f 1730 && inst->operands[2].reg.regno == 0x1f 1731 && (inst->operands[3].cond->value & 0xe) != 0xe) 1732 { 1733 copy_operand_info (inst, 1, 3); 1734 inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond); 1735 inst->operands[3].type = AARCH64_OPND_NIL; 1736 inst->operands[2].type = AARCH64_OPND_NIL; 1737 return 1; 1738 } 1739 return 0; 1740 } 1741 1742 /* MOV <Wd>, #<imm> 1743 is equivalent to: 1744 MOVZ <Wd>, #<imm16>, LSL #<shift>. 1745 1746 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when 1747 ORR has an immediate that could be generated by a MOVZ or MOVN instruction, 1748 or where a MOVN has an immediate that could be encoded by MOVZ, or where 1749 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the 1750 machine-instruction mnemonic must be used. */ 1751 1752 static int 1753 convert_movewide_to_mov (aarch64_inst *inst) 1754 { 1755 uint64_t value = inst->operands[1].imm.value; 1756 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */ 1757 if (value == 0 && inst->operands[1].shifter.amount != 0) 1758 return 0; 1759 inst->operands[1].type = AARCH64_OPND_IMM_MOV; 1760 inst->operands[1].shifter.kind = AARCH64_MOD_NONE; 1761 value <<= inst->operands[1].shifter.amount; 1762 /* As an alias convertor, it has to be clear that the INST->OPCODE 1763 is the opcode of the real instruction. */ 1764 if (inst->opcode->op == OP_MOVN) 1765 { 1766 int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; 1767 value = ~value; 1768 /* A MOVN has an immediate that could be encoded by MOVZ. */ 1769 if (aarch64_wide_constant_p (value, is32, NULL) == TRUE) 1770 return 0; 1771 } 1772 inst->operands[1].imm.value = value; 1773 inst->operands[1].shifter.amount = 0; 1774 return 1; 1775 } 1776 1777 /* MOV <Wd>, #<imm> 1778 is equivalent to: 1779 ORR <Wd>, WZR, #<imm>. 1780 1781 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when 1782 ORR has an immediate that could be generated by a MOVZ or MOVN instruction, 1783 or where a MOVN has an immediate that could be encoded by MOVZ, or where 1784 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the 1785 machine-instruction mnemonic must be used. */ 1786 1787 static int 1788 convert_movebitmask_to_mov (aarch64_inst *inst) 1789 { 1790 int is32; 1791 uint64_t value; 1792 1793 /* Should have been assured by the base opcode value. */ 1794 assert (inst->operands[1].reg.regno == 0x1f); 1795 copy_operand_info (inst, 1, 2); 1796 is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; 1797 inst->operands[1].type = AARCH64_OPND_IMM_MOV; 1798 value = inst->operands[1].imm.value; 1799 /* ORR has an immediate that could be generated by a MOVZ or MOVN 1800 instruction. */ 1801 if (inst->operands[0].reg.regno != 0x1f 1802 && (aarch64_wide_constant_p (value, is32, NULL) == TRUE 1803 || aarch64_wide_constant_p (~value, is32, NULL) == TRUE)) 1804 return 0; 1805 1806 inst->operands[2].type = AARCH64_OPND_NIL; 1807 return 1; 1808 } 1809 1810 /* Some alias opcodes are disassembled by being converted from their real-form. 1811 N.B. INST->OPCODE is the real opcode rather than the alias. */ 1812 1813 static int 1814 convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias) 1815 { 1816 switch (alias->op) 1817 { 1818 case OP_ASR_IMM: 1819 case OP_LSR_IMM: 1820 return convert_bfm_to_sr (inst); 1821 case OP_LSL_IMM: 1822 return convert_ubfm_to_lsl (inst); 1823 case OP_CINC: 1824 case OP_CINV: 1825 case OP_CNEG: 1826 return convert_from_csel (inst); 1827 case OP_CSET: 1828 case OP_CSETM: 1829 return convert_csinc_to_cset (inst); 1830 case OP_UBFX: 1831 case OP_BFXIL: 1832 case OP_SBFX: 1833 return convert_bfm_to_bfx (inst); 1834 case OP_SBFIZ: 1835 case OP_BFI: 1836 case OP_UBFIZ: 1837 return convert_bfm_to_bfi (inst); 1838 case OP_BFC: 1839 return convert_bfm_to_bfc (inst); 1840 case OP_MOV_V: 1841 return convert_orr_to_mov (inst); 1842 case OP_MOV_IMM_WIDE: 1843 case OP_MOV_IMM_WIDEN: 1844 return convert_movewide_to_mov (inst); 1845 case OP_MOV_IMM_LOG: 1846 return convert_movebitmask_to_mov (inst); 1847 case OP_ROR_IMM: 1848 return convert_extr_to_ror (inst); 1849 case OP_SXTL: 1850 case OP_SXTL2: 1851 case OP_UXTL: 1852 case OP_UXTL2: 1853 return convert_shll_to_xtl (inst); 1854 default: 1855 return 0; 1856 } 1857 } 1858 1859 static int aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, 1860 aarch64_inst *, int); 1861 1862 /* Given the instruction information in *INST, check if the instruction has 1863 any alias form that can be used to represent *INST. If the answer is yes, 1864 update *INST to be in the form of the determined alias. */ 1865 1866 /* In the opcode description table, the following flags are used in opcode 1867 entries to help establish the relations between the real and alias opcodes: 1868 1869 F_ALIAS: opcode is an alias 1870 F_HAS_ALIAS: opcode has alias(es) 1871 F_P1 1872 F_P2 1873 F_P3: Disassembly preference priority 1-3 (the larger the 1874 higher). If nothing is specified, it is the priority 1875 0 by default, i.e. the lowest priority. 1876 1877 Although the relation between the machine and the alias instructions are not 1878 explicitly described, it can be easily determined from the base opcode 1879 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode 1880 description entries: 1881 1882 The mask of an alias opcode must be equal to or a super-set (i.e. more 1883 constrained) of that of the aliased opcode; so is the base opcode value. 1884 1885 if (opcode_has_alias (real) && alias_opcode_p (opcode) 1886 && (opcode->mask & real->mask) == real->mask 1887 && (real->mask & opcode->opcode) == (real->mask & real->opcode)) 1888 then OPCODE is an alias of, and only of, the REAL instruction 1889 1890 The alias relationship is forced flat-structured to keep related algorithm 1891 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS. 1892 1893 During the disassembling, the decoding decision tree (in 1894 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry; 1895 if the decoding of such a machine instruction succeeds (and -Mno-aliases is 1896 not specified), the disassembler will check whether there is any alias 1897 instruction exists for this real instruction. If there is, the disassembler 1898 will try to disassemble the 32-bit binary again using the alias's rule, or 1899 try to convert the IR to the form of the alias. In the case of the multiple 1900 aliases, the aliases are tried one by one from the highest priority 1901 (currently the flag F_P3) to the lowest priority (no priority flag), and the 1902 first succeeds first adopted. 1903 1904 You may ask why there is a need for the conversion of IR from one form to 1905 another in handling certain aliases. This is because on one hand it avoids 1906 adding more operand code to handle unusual encoding/decoding; on other 1907 hand, during the disassembling, the conversion is an effective approach to 1908 check the condition of an alias (as an alias may be adopted only if certain 1909 conditions are met). 1910 1911 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed 1912 aarch64_opcode_table and generated aarch64_find_alias_opcode and 1913 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */ 1914 1915 static void 1916 determine_disassembling_preference (struct aarch64_inst *inst) 1917 { 1918 const aarch64_opcode *opcode; 1919 const aarch64_opcode *alias; 1920 1921 opcode = inst->opcode; 1922 1923 /* This opcode does not have an alias, so use itself. */ 1924 if (opcode_has_alias (opcode) == FALSE) 1925 return; 1926 1927 alias = aarch64_find_alias_opcode (opcode); 1928 assert (alias); 1929 1930 #ifdef DEBUG_AARCH64 1931 if (debug_dump) 1932 { 1933 const aarch64_opcode *tmp = alias; 1934 printf ("#### LIST orderd: "); 1935 while (tmp) 1936 { 1937 printf ("%s, ", tmp->name); 1938 tmp = aarch64_find_next_alias_opcode (tmp); 1939 } 1940 printf ("\n"); 1941 } 1942 #endif /* DEBUG_AARCH64 */ 1943 1944 for (; alias; alias = aarch64_find_next_alias_opcode (alias)) 1945 { 1946 DEBUG_TRACE ("try %s", alias->name); 1947 assert (alias_opcode_p (alias) || opcode_has_alias (opcode)); 1948 1949 /* An alias can be a pseudo opcode which will never be used in the 1950 disassembly, e.g. BIC logical immediate is such a pseudo opcode 1951 aliasing AND. */ 1952 if (pseudo_opcode_p (alias)) 1953 { 1954 DEBUG_TRACE ("skip pseudo %s", alias->name); 1955 continue; 1956 } 1957 1958 if ((inst->value & alias->mask) != alias->opcode) 1959 { 1960 DEBUG_TRACE ("skip %s as base opcode not match", alias->name); 1961 continue; 1962 } 1963 /* No need to do any complicated transformation on operands, if the alias 1964 opcode does not have any operand. */ 1965 if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value) 1966 { 1967 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name); 1968 aarch64_replace_opcode (inst, alias); 1969 return; 1970 } 1971 if (alias->flags & F_CONV) 1972 { 1973 aarch64_inst copy; 1974 memcpy (©, inst, sizeof (aarch64_inst)); 1975 /* ALIAS is the preference as long as the instruction can be 1976 successfully converted to the form of ALIAS. */ 1977 if (convert_to_alias (©, alias) == 1) 1978 { 1979 aarch64_replace_opcode (©, alias); 1980 assert (aarch64_match_operands_constraint (©, NULL)); 1981 DEBUG_TRACE ("succeed with %s via conversion", alias->name); 1982 memcpy (inst, ©, sizeof (aarch64_inst)); 1983 return; 1984 } 1985 } 1986 else 1987 { 1988 /* Directly decode the alias opcode. */ 1989 aarch64_inst temp; 1990 memset (&temp, '\0', sizeof (aarch64_inst)); 1991 if (aarch64_opcode_decode (alias, inst->value, &temp, 1) == 1) 1992 { 1993 DEBUG_TRACE ("succeed with %s via direct decoding", alias->name); 1994 memcpy (inst, &temp, sizeof (aarch64_inst)); 1995 return; 1996 } 1997 } 1998 } 1999 } 2000 2001 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding 2002 fails, which meanes that CODE is not an instruction of OPCODE; otherwise 2003 return 1. 2004 2005 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be 2006 determined and used to disassemble CODE; this is done just before the 2007 return. */ 2008 2009 static int 2010 aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, 2011 aarch64_inst *inst, int noaliases_p) 2012 { 2013 int i; 2014 2015 DEBUG_TRACE ("enter with %s", opcode->name); 2016 2017 assert (opcode && inst); 2018 2019 /* Check the base opcode. */ 2020 if ((code & opcode->mask) != (opcode->opcode & opcode->mask)) 2021 { 2022 DEBUG_TRACE ("base opcode match FAIL"); 2023 goto decode_fail; 2024 } 2025 2026 /* Clear inst. */ 2027 memset (inst, '\0', sizeof (aarch64_inst)); 2028 2029 inst->opcode = opcode; 2030 inst->value = code; 2031 2032 /* Assign operand codes and indexes. */ 2033 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 2034 { 2035 if (opcode->operands[i] == AARCH64_OPND_NIL) 2036 break; 2037 inst->operands[i].type = opcode->operands[i]; 2038 inst->operands[i].idx = i; 2039 } 2040 2041 /* Call the opcode decoder indicated by flags. */ 2042 if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0) 2043 { 2044 DEBUG_TRACE ("opcode flag-based decoder FAIL"); 2045 goto decode_fail; 2046 } 2047 2048 /* Call operand decoders. */ 2049 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) 2050 { 2051 const aarch64_operand *opnd; 2052 enum aarch64_opnd type; 2053 2054 type = opcode->operands[i]; 2055 if (type == AARCH64_OPND_NIL) 2056 break; 2057 opnd = &aarch64_operands[type]; 2058 if (operand_has_extractor (opnd) 2059 && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst))) 2060 { 2061 DEBUG_TRACE ("operand decoder FAIL at operand %d", i); 2062 goto decode_fail; 2063 } 2064 } 2065 2066 /* If the opcode has a verifier, then check it now. */ 2067 if (opcode->verifier && ! opcode->verifier (opcode, code)) 2068 { 2069 DEBUG_TRACE ("operand verifier FAIL"); 2070 goto decode_fail; 2071 } 2072 2073 /* Match the qualifiers. */ 2074 if (aarch64_match_operands_constraint (inst, NULL) == 1) 2075 { 2076 /* Arriving here, the CODE has been determined as a valid instruction 2077 of OPCODE and *INST has been filled with information of this OPCODE 2078 instruction. Before the return, check if the instruction has any 2079 alias and should be disassembled in the form of its alias instead. 2080 If the answer is yes, *INST will be updated. */ 2081 if (!noaliases_p) 2082 determine_disassembling_preference (inst); 2083 DEBUG_TRACE ("SUCCESS"); 2084 return 1; 2085 } 2086 else 2087 { 2088 DEBUG_TRACE ("constraint matching FAIL"); 2089 } 2090 2091 decode_fail: 2092 return 0; 2093 } 2094 2095 /* This does some user-friendly fix-up to *INST. It is currently focus on 2097 the adjustment of qualifiers to help the printed instruction 2098 recognized/understood more easily. */ 2099 2100 static void 2101 user_friendly_fixup (aarch64_inst *inst) 2102 { 2103 switch (inst->opcode->iclass) 2104 { 2105 case testbranch: 2106 /* TBNZ Xn|Wn, #uimm6, label 2107 Test and Branch Not Zero: conditionally jumps to label if bit number 2108 uimm6 in register Xn is not zero. The bit number implies the width of 2109 the register, which may be written and should be disassembled as Wn if 2110 uimm is less than 32. Limited to a branch offset range of +/- 32KiB. 2111 */ 2112 if (inst->operands[1].imm.value < 32) 2113 inst->operands[0].qualifier = AARCH64_OPND_QLF_W; 2114 break; 2115 default: break; 2116 } 2117 } 2118 2119 /* Decode INSN and fill in *INST the instruction information. An alias 2120 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on 2121 success. */ 2122 2123 int 2124 aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, 2125 bfd_boolean noaliases_p) 2126 { 2127 const aarch64_opcode *opcode = aarch64_opcode_lookup (insn); 2128 2129 #ifdef DEBUG_AARCH64 2130 if (debug_dump) 2131 { 2132 const aarch64_opcode *tmp = opcode; 2133 printf ("\n"); 2134 DEBUG_TRACE ("opcode lookup:"); 2135 while (tmp != NULL) 2136 { 2137 aarch64_verbose (" %s", tmp->name); 2138 tmp = aarch64_find_next_opcode (tmp); 2139 } 2140 } 2141 #endif /* DEBUG_AARCH64 */ 2142 2143 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot 2144 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same 2145 opcode field and value, apart from the difference that one of them has an 2146 extra field as part of the opcode, but such a field is used for operand 2147 encoding in other opcode(s) ('immh' in the case of the example). */ 2148 while (opcode != NULL) 2149 { 2150 /* But only one opcode can be decoded successfully for, as the 2151 decoding routine will check the constraint carefully. */ 2152 if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p) == 1) 2153 return ERR_OK; 2154 opcode = aarch64_find_next_opcode (opcode); 2155 } 2156 2157 return ERR_UND; 2158 } 2159 2160 /* Print operands. */ 2161 2162 static void 2163 print_operands (bfd_vma pc, const aarch64_opcode *opcode, 2164 const aarch64_opnd_info *opnds, struct disassemble_info *info) 2165 { 2166 int i, pcrel_p, num_printed; 2167 for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i) 2168 { 2169 char str[128]; 2170 /* We regard the opcode operand info more, however we also look into 2171 the inst->operands to support the disassembling of the optional 2172 operand. 2173 The two operand code should be the same in all cases, apart from 2174 when the operand can be optional. */ 2175 if (opcode->operands[i] == AARCH64_OPND_NIL 2176 || opnds[i].type == AARCH64_OPND_NIL) 2177 break; 2178 2179 /* Generate the operand string in STR. */ 2180 aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p, 2181 &info->target); 2182 2183 /* Print the delimiter (taking account of omitted operand(s)). */ 2184 if (str[0] != '\0') 2185 (*info->fprintf_func) (info->stream, "%s", 2186 num_printed++ == 0 ? "\t" : ", "); 2187 2188 /* Print the operand. */ 2189 if (pcrel_p) 2190 (*info->print_address_func) (info->target, info); 2191 else 2192 (*info->fprintf_func) (info->stream, "%s", str); 2193 } 2194 } 2195 2196 /* Print the instruction mnemonic name. */ 2197 2198 static void 2199 print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info) 2200 { 2201 if (inst->opcode->flags & F_COND) 2202 { 2203 /* For instructions that are truly conditionally executed, e.g. b.cond, 2204 prepare the full mnemonic name with the corresponding condition 2205 suffix. */ 2206 char name[8], *ptr; 2207 size_t len; 2208 2209 ptr = strchr (inst->opcode->name, '.'); 2210 assert (ptr && inst->cond); 2211 len = ptr - inst->opcode->name; 2212 assert (len < 8); 2213 strncpy (name, inst->opcode->name, len); 2214 name [len] = '\0'; 2215 (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]); 2216 } 2217 else 2218 (*info->fprintf_func) (info->stream, "%s", inst->opcode->name); 2219 } 2220 2221 /* Print the instruction according to *INST. */ 2222 2223 static void 2224 print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, 2225 struct disassemble_info *info) 2226 { 2227 print_mnemonic_name (inst, info); 2228 print_operands (pc, inst->opcode, inst->operands, info); 2229 } 2230 2231 /* Entry-point of the instruction disassembler and printer. */ 2232 2233 static void 2234 print_insn_aarch64_word (bfd_vma pc, 2235 uint32_t word, 2236 struct disassemble_info *info) 2237 { 2238 static const char *err_msg[6] = 2239 { 2240 [ERR_OK] = "_", 2241 [-ERR_UND] = "undefined", 2242 [-ERR_UNP] = "unpredictable", 2243 [-ERR_NYI] = "NYI" 2244 }; 2245 2246 int ret; 2247 aarch64_inst inst; 2248 2249 info->insn_info_valid = 1; 2250 info->branch_delay_insns = 0; 2251 info->data_size = 0; 2252 info->target = 0; 2253 info->target2 = 0; 2254 2255 if (info->flags & INSN_HAS_RELOC) 2256 /* If the instruction has a reloc associated with it, then 2257 the offset field in the instruction will actually be the 2258 addend for the reloc. (If we are using REL type relocs). 2259 In such cases, we can ignore the pc when computing 2260 addresses, since the addend is not currently pc-relative. */ 2261 pc = 0; 2262 2263 ret = aarch64_decode_insn (word, &inst, no_aliases); 2264 2265 if (((word >> 21) & 0x3ff) == 1) 2266 { 2267 /* RESERVED for ALES. */ 2268 assert (ret != ERR_OK); 2269 ret = ERR_NYI; 2270 } 2271 2272 switch (ret) 2273 { 2274 case ERR_UND: 2275 case ERR_UNP: 2276 case ERR_NYI: 2277 /* Handle undefined instructions. */ 2278 info->insn_type = dis_noninsn; 2279 (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s", 2280 word, err_msg[-ret]); 2281 break; 2282 case ERR_OK: 2283 user_friendly_fixup (&inst); 2284 print_aarch64_insn (pc, &inst, info); 2285 break; 2286 default: 2287 abort (); 2288 } 2289 } 2290 2291 /* Disallow mapping symbols ($x, $d etc) from 2292 being displayed in symbol relative addresses. */ 2293 2294 bfd_boolean 2295 aarch64_symbol_is_valid (asymbol * sym, 2296 struct disassemble_info * info ATTRIBUTE_UNUSED) 2297 { 2298 const char * name; 2299 2300 if (sym == NULL) 2301 return FALSE; 2302 2303 name = bfd_asymbol_name (sym); 2304 2305 return name 2306 && (name[0] != '$' 2307 || (name[1] != 'x' && name[1] != 'd') 2308 || (name[2] != '\0' && name[2] != '.')); 2309 } 2310 2311 /* Print data bytes on INFO->STREAM. */ 2312 2313 static void 2314 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 2315 uint32_t word, 2316 struct disassemble_info *info) 2317 { 2318 switch (info->bytes_per_chunk) 2319 { 2320 case 1: 2321 info->fprintf_func (info->stream, ".byte\t0x%02x", word); 2322 break; 2323 case 2: 2324 info->fprintf_func (info->stream, ".short\t0x%04x", word); 2325 break; 2326 case 4: 2327 info->fprintf_func (info->stream, ".word\t0x%08x", word); 2328 break; 2329 default: 2330 abort (); 2331 } 2332 } 2333 2334 /* Try to infer the code or data type from a symbol. 2335 Returns nonzero if *MAP_TYPE was set. */ 2336 2337 static int 2338 get_sym_code_type (struct disassemble_info *info, int n, 2339 enum map_type *map_type) 2340 { 2341 elf_symbol_type *es; 2342 unsigned int type; 2343 const char *name; 2344 2345 es = *(elf_symbol_type **)(info->symtab + n); 2346 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 2347 2348 /* If the symbol has function type then use that. */ 2349 if (type == STT_FUNC) 2350 { 2351 *map_type = MAP_INSN; 2352 return TRUE; 2353 } 2354 2355 /* Check for mapping symbols. */ 2356 name = bfd_asymbol_name(info->symtab[n]); 2357 if (name[0] == '$' 2358 && (name[1] == 'x' || name[1] == 'd') 2359 && (name[2] == '\0' || name[2] == '.')) 2360 { 2361 *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA); 2362 return TRUE; 2363 } 2364 2365 return FALSE; 2366 } 2367 2368 /* Entry-point of the AArch64 disassembler. */ 2369 2370 int 2371 print_insn_aarch64 (bfd_vma pc, 2372 struct disassemble_info *info) 2373 { 2374 bfd_byte buffer[INSNLEN]; 2375 int status; 2376 void (*printer) (bfd_vma, uint32_t, struct disassemble_info *); 2377 bfd_boolean found = FALSE; 2378 unsigned int size = 4; 2379 unsigned long data; 2380 2381 if (info->disassembler_options) 2382 { 2383 set_default_aarch64_dis_options (info); 2384 2385 parse_aarch64_dis_options (info->disassembler_options); 2386 2387 /* To avoid repeated parsing of these options, we remove them here. */ 2388 info->disassembler_options = NULL; 2389 } 2390 2391 /* Aarch64 instructions are always little-endian */ 2392 info->endian_code = BFD_ENDIAN_LITTLE; 2393 2394 /* First check the full symtab for a mapping symbol, even if there 2395 are no usable non-mapping symbols for this address. */ 2396 if (info->symtab_size != 0 2397 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 2398 { 2399 enum map_type type = MAP_INSN; 2400 int last_sym = -1; 2401 bfd_vma addr; 2402 int n; 2403 2404 if (pc <= last_mapping_addr) 2405 last_mapping_sym = -1; 2406 2407 /* Start scanning at the start of the function, or wherever 2408 we finished last time. */ 2409 n = info->symtab_pos + 1; 2410 if (n < last_mapping_sym) 2411 n = last_mapping_sym; 2412 2413 /* Scan up to the location being disassembled. */ 2414 for (; n < info->symtab_size; n++) 2415 { 2416 addr = bfd_asymbol_value (info->symtab[n]); 2417 if (addr > pc) 2418 break; 2419 if ((info->section == NULL 2420 || info->section == info->symtab[n]->section) 2421 && get_sym_code_type (info, n, &type)) 2422 { 2423 last_sym = n; 2424 found = TRUE; 2425 } 2426 } 2427 2428 if (!found) 2429 { 2430 n = info->symtab_pos; 2431 if (n < last_mapping_sym) 2432 n = last_mapping_sym; 2433 2434 /* No mapping symbol found at this address. Look backwards 2435 for a preceeding one. */ 2436 for (; n >= 0; n--) 2437 { 2438 if (get_sym_code_type (info, n, &type)) 2439 { 2440 last_sym = n; 2441 found = TRUE; 2442 break; 2443 } 2444 } 2445 } 2446 2447 last_mapping_sym = last_sym; 2448 last_type = type; 2449 2450 /* Look a little bit ahead to see if we should print out 2451 less than four bytes of data. If there's a symbol, 2452 mapping or otherwise, after two bytes then don't 2453 print more. */ 2454 if (last_type == MAP_DATA) 2455 { 2456 size = 4 - (pc & 3); 2457 for (n = last_sym + 1; n < info->symtab_size; n++) 2458 { 2459 addr = bfd_asymbol_value (info->symtab[n]); 2460 if (addr > pc) 2461 { 2462 if (addr - pc < size) 2463 size = addr - pc; 2464 break; 2465 } 2466 } 2467 /* If the next symbol is after three bytes, we need to 2468 print only part of the data, so that we can use either 2469 .byte or .short. */ 2470 if (size == 3) 2471 size = (pc & 1) ? 1 : 2; 2472 } 2473 } 2474 2475 if (last_type == MAP_DATA) 2476 { 2477 /* size was set above. */ 2478 info->bytes_per_chunk = size; 2479 info->display_endian = info->endian; 2480 printer = print_insn_data; 2481 } 2482 else 2483 { 2484 info->bytes_per_chunk = size = INSNLEN; 2485 info->display_endian = info->endian_code; 2486 printer = print_insn_aarch64_word; 2487 } 2488 2489 status = (*info->read_memory_func) (pc, buffer, size, info); 2490 if (status != 0) 2491 { 2492 (*info->memory_error_func) (status, pc, info); 2493 return -1; 2494 } 2495 2496 data = bfd_get_bits (buffer, size * 8, 2497 info->display_endian == BFD_ENDIAN_BIG); 2498 2499 (*printer) (pc, data, info); 2500 2501 return size; 2502 } 2503 2504 void 2506 print_aarch64_disassembler_options (FILE *stream) 2507 { 2508 fprintf (stream, _("\n\ 2509 The following AARCH64 specific disassembler options are supported for use\n\ 2510 with the -M switch (multiple options should be separated by commas):\n")); 2511 2512 fprintf (stream, _("\n\ 2513 no-aliases Don't print instruction aliases.\n")); 2514 2515 fprintf (stream, _("\n\ 2516 aliases Do print instruction aliases.\n")); 2517 2518 #ifdef DEBUG_AARCH64 2519 fprintf (stream, _("\n\ 2520 debug_dump Temp switch for debug trace.\n")); 2521 #endif /* DEBUG_AARCH64 */ 2522 2523 fprintf (stream, _("\n")); 2524 } 2525
