| /art/test/065-mismatched-implements/src/ |
| Defs.java | 17 public interface Defs {
|
| /art/test/066-mismatched-super/src2/ |
| Defs.java | 17 public interface Defs {
|
| /art/test/065-mismatched-implements/src2/ |
| Defs.java | 17 public abstract class Defs {
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| /art/test/066-mismatched-super/src/ |
| Defs.java | 17 public abstract class Defs {
|
| /external/llvm/utils/TableGen/ |
| CTagsEmitter.cpp | 67 const auto &Defs = Records.getDefs();
70 Tags.reserve(Classes.size() + Defs.size());
73 for (const auto &D : Defs)
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| CodeGenTarget.cpp | 431 std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
434 Result.reserve(Defs.size());
436 for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
437 bool isTarget = Defs[I]->getValueAsBit("isTarget");
439 Result.push_back(CodeGenIntrinsic(Defs[I]));
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| InstrInfoEmitter.cpp | 358 // Emit all of the instruction's implicit uses and defs.
366 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
367 if (!Defs.empty()) {
368 unsigned &IL = EmittedLists[Defs];
369 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
526 // Emit the implicit uses and defs lists...
533 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
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| /external/llvm/lib/CodeGen/ |
| MachineCopyPropagation.cpp | 255 SmallVector<unsigned, 2> Defs;
270 Defs.push_back(Reg);
283 // Treat undef use like defs for copy propagation but not for
290 Defs.push_back(Reg);
333 // Any previous copy definition or reading the Defs is no longer available.
334 for (unsigned Reg : Defs)
338 // If MBB doesn't have successors, delete the copies whose defs are not used.
339 // If MBB does have successors, then conservative assume the defs are live-out
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| MachineInstrBundle.cpp | 111 /// bundle, and it copies externally visible defs and uses to the BUNDLE
135 SmallVector<MachineOperand*, 4> Defs;
142 Defs.push_back(&MO);
167 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
168 MachineOperand &MO = *Defs[i];
195 Defs.clear();
277 // Both defs and uses can read virtual registers.
284 // Only defs can write.
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCBoolRetToInt.cpp | 62 SmallPtrSet<Value *, 8> Defs;
65 Defs.insert(V);
71 if (Defs.insert(Op).second)
74 return Defs;
196 auto Defs = findAllDefs(U);
199 if (!std::any_of(Defs.begin(), Defs.end(), isa<Instruction, Value *>))
205 for (Value *V : Defs)
209 for (Value *V : Defs)
220 for (Value *V : Defs)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ScheduleDAGInstrs.h | 107 /// Defs, Uses - Remember where defs and uses of each physical register
111 std::vector<std::vector<SUnit *> > Defs;
115 /// unknown store, as we iterate. As with Defs and Uses, this is here
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| InstrInfoEmitter.cpp | 183 // Emit all of the instruction's implicit uses and defs.
192 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
193 if (!Defs.empty()) {
194 unsigned &IL = EmittedLists[Defs];
195 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
313 // Emit the implicit uses and defs lists...
320 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
|
| /frameworks/compile/mclinker/include/mcld/MC/ |
| ZOption.h | 24 Defs,
|
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 149 /// Defs, Uses - Remember where defs and uses of each register are as we
153 Reg2SUnitsMap Defs;
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| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 51 SmallSet<unsigned, 4> &Defs,
62 SmallSet<unsigned, 4> &Defs,
92 Defs.insert(*Subreg);
126 SmallSet<unsigned, 4> &Defs,
141 if (Uses.count(DstReg) || Defs.count(SrcReg))
183 SmallSet<unsigned, 4> Defs;
196 Defs.clear();
198 TrackDefUses(MI, Defs, Uses, TRI);
239 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
249 TrackDefUses(NMI, Defs, Uses, TRI)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitSimplify.cpp | 157 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
224 RegisterSet Defs;
226 getInstrDefs(I, Defs);
228 NewAVs.insert(Defs);
244 RegisterSet &Defs) {
251 Defs.insert(R);
[all...] |
| HexagonRDFOpt.cpp | 242 NodeList Defs;
247 Defs = DFG.getRelatedRefs(IA, DA);
248 if (!std::all_of(Defs.begin(), Defs.end(), IsDead))
253 // Mark all nodes in Defs for removal.
254 for (auto D : Defs)
|
| /external/lzma/C/ |
| 7z.h | 64 Byte *Defs; /* MSB 0 bit numbering */
70 Byte *Defs; /* MSB 0 bit numbering */
77 #define SzBitWithVals_Check(p, i) ((p)->Defs && ((p)->Defs[(i) >> 3] & (0x80 >> ((i) & 7))) != 0)
|
| /external/lzma/CPP/7zip/Archive/7z/ |
| 7zItem.h | 92 CBoolVector Defs;
97 Defs.ClearAndSetSize(newSize);
103 Defs.Clear();
109 Defs.ReserveDown();
113 bool ValidAndDefined(unsigned i) const { return i < Defs.Size() && Defs[i]; }
118 CBoolVector Defs;
123 Defs.Clear();
129 Defs.ReserveDown();
135 if (index < Defs.Size() && Defs[index])
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 45 SmallSet<unsigned, 4> &Defs,
56 SmallSet<unsigned, 4> &Defs,
85 Defs.insert(Reg);
88 Defs.insert(*Subreg);
109 SmallSet<unsigned, 4> &Defs,
124 if (Uses.count(DstReg) || Defs.count(SrcReg))
166 SmallSet<unsigned, 4> Defs;
179 Defs.clear();
181 TrackDefUses(MI, Defs, Uses, TRI);
218 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses))
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 143 /// Defs, Uses - Remember where defs and uses of each register are as we
147 Reg2SUnitsMap Defs;
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 163 /// Defs, Uses - Remember where defs and uses of each register are as we
167 Reg2SUnitsMap Defs;
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 163 /// Defs, Uses - Remember where defs and uses of each register are as we
167 Reg2SUnitsMap Defs;
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 163 /// Defs, Uses - Remember where defs and uses of each register are as we
167 Reg2SUnitsMap Defs;
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 163 /// Defs, Uses - Remember where defs and uses of each register are as we
167 Reg2SUnitsMap Defs;
|
