1 /* 2 * Copyright (C) 2009 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 18 #define ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 19 20 #include <stdint.h> 21 22 #include <iosfwd> 23 24 #include <android-base/logging.h> 25 26 #include "arch/arm/registers_arm.h" 27 #include "base/casts.h" 28 #include "globals.h" 29 30 namespace art { 31 namespace arm { 32 33 // Defines constants and accessor classes to assemble, disassemble and 34 // simulate ARM instructions. 35 // 36 // Section references in the code refer to the "ARM Architecture 37 // Reference Manual ARMv7-A and ARMv7-R edition", issue C.b (24 July 38 // 2012). 39 // 40 // Constants for specific fields are defined in their respective named enums. 41 // General constants are in an anonymous enum in class Instr. 42 43 // 4 bits option for the dmb instruction. 44 // Order and values follows those of the ARM Architecture Reference Manual. 45 enum DmbOptions { 46 SY = 0xf, 47 ST = 0xe, 48 ISH = 0xb, 49 ISHST = 0xa, 50 NSH = 0x7, 51 NSHST = 0x6 52 }; 53 54 enum ScaleFactor { 55 TIMES_1 = 0, 56 TIMES_2 = 1, 57 TIMES_4 = 2, 58 TIMES_8 = 3 59 }; 60 61 // Values for double-precision floating point registers. 62 enum DRegister { // private marker to avoid generate-operator-out.py from processing. 63 D0 = 0, 64 D1 = 1, 65 D2 = 2, 66 D3 = 3, 67 D4 = 4, 68 D5 = 5, 69 D6 = 6, 70 D7 = 7, 71 D8 = 8, 72 D9 = 9, 73 D10 = 10, 74 D11 = 11, 75 D12 = 12, 76 D13 = 13, 77 D14 = 14, 78 D15 = 15, 79 D16 = 16, 80 D17 = 17, 81 D18 = 18, 82 D19 = 19, 83 D20 = 20, 84 D21 = 21, 85 D22 = 22, 86 D23 = 23, 87 D24 = 24, 88 D25 = 25, 89 D26 = 26, 90 D27 = 27, 91 D28 = 28, 92 D29 = 29, 93 D30 = 30, 94 D31 = 31, 95 kNumberOfDRegisters = 32, 96 kNumberOfOverlappingDRegisters = 16, 97 kNoDRegister = -1, 98 }; 99 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 100 101 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 102 // as defined in section A3.4 103 enum Opcode { 104 kNoOperand = -1, 105 AND = 0, // Logical AND 106 EOR = 1, // Logical Exclusive OR 107 SUB = 2, // Subtract 108 RSB = 3, // Reverse Subtract 109 ADD = 4, // Add 110 ADC = 5, // Add with Carry 111 SBC = 6, // Subtract with Carry 112 RSC = 7, // Reverse Subtract with Carry 113 TST = 8, // Test 114 TEQ = 9, // Test Equivalence 115 CMP = 10, // Compare 116 CMN = 11, // Compare Negated 117 ORR = 12, // Logical (inclusive) OR 118 MOV = 13, // Move 119 BIC = 14, // Bit Clear 120 MVN = 15, // Move Not 121 ORN = 16, // Logical OR NOT. 122 kMaxOperand = 17 123 }; 124 125 // Size (in bytes) of registers. 126 const int kRegisterSize = 4; 127 128 // List of registers used in load/store multiple. 129 typedef uint16_t RegList; 130 131 132 } // namespace arm 133 } // namespace art 134 135 #endif // ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 136
