1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Sparc uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef SPARC_ISELLOWERING_H 16 #define SPARC_ISELLOWERING_H 17 18 #include "llvm/Target/TargetLowering.h" 19 #include "Sparc.h" 20 21 namespace llvm { 22 namespace SPISD { 23 enum { 24 FIRST_NUMBER = ISD::BUILTIN_OP_END, 25 CMPICC, // Compare two GPR operands, set icc. 26 CMPFCC, // Compare two FP operands, set fcc. 27 BRICC, // Branch to dest on icc condition 28 BRFCC, // Branch to dest on fcc condition 29 SELECT_ICC, // Select between two values using the current ICC flags. 30 SELECT_FCC, // Select between two values using the current FCC flags. 31 32 Hi, Lo, // Hi/Lo operations, typically on a global address. 33 34 FTOI, // FP to Int within a FP register. 35 ITOF, // Int to FP within a FP register. 36 37 CALL, // A call instruction. 38 RET_FLAG, // Return with a flag operand. 39 GLOBAL_BASE_REG, // Global base reg for PIC 40 FLUSHW // FLUSH register windows to stack 41 }; 42 } 43 44 class SparcTargetLowering : public TargetLowering { 45 public: 46 SparcTargetLowering(TargetMachine &TM); 47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 48 49 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 50 /// in Mask are known to be either zero or one and return them in the 51 /// KnownZero/KnownOne bitsets. 52 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 53 const APInt &Mask, 54 APInt &KnownZero, 55 APInt &KnownOne, 56 const SelectionDAG &DAG, 57 unsigned Depth = 0) const; 58 59 virtual MachineBasicBlock * 60 EmitInstrWithCustomInserter(MachineInstr *MI, 61 MachineBasicBlock *MBB) const; 62 63 virtual const char *getTargetNodeName(unsigned Opcode) const; 64 65 ConstraintType getConstraintType(const std::string &Constraint) const; 66 std::pair<unsigned, const TargetRegisterClass*> 67 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; 68 69 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 70 71 virtual SDValue 72 LowerFormalArguments(SDValue Chain, 73 CallingConv::ID CallConv, 74 bool isVarArg, 75 const SmallVectorImpl<ISD::InputArg> &Ins, 76 DebugLoc dl, SelectionDAG &DAG, 77 SmallVectorImpl<SDValue> &InVals) const; 78 79 virtual SDValue 80 LowerCall(SDValue Chain, SDValue Callee, 81 CallingConv::ID CallConv, bool isVarArg, 82 bool &isTailCall, 83 const SmallVectorImpl<ISD::OutputArg> &Outs, 84 const SmallVectorImpl<SDValue> &OutVals, 85 const SmallVectorImpl<ISD::InputArg> &Ins, 86 DebugLoc dl, SelectionDAG &DAG, 87 SmallVectorImpl<SDValue> &InVals) const; 88 89 virtual SDValue 90 LowerReturn(SDValue Chain, 91 CallingConv::ID CallConv, bool isVarArg, 92 const SmallVectorImpl<ISD::OutputArg> &Outs, 93 const SmallVectorImpl<SDValue> &OutVals, 94 DebugLoc dl, SelectionDAG &DAG) const; 95 96 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 97 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 98 99 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; 100 }; 101 } // end namespace llvm 102 103 #endif // SPARC_ISELLOWERING_H 104
