1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __HI3798cv200_H__ 8 #define __HI3798cv200_H__ 9 10 /* PL011 */ 11 #define PL011_UART0_BASE (0xF8B00000) 12 #define PL011_BAUDRATE (115200) 13 #define PL011_UART0_CLK_IN_HZ (75000000) 14 15 /* Sys Counter */ 16 #define SYS_COUNTER_FREQ_IN_TICKS (24000000) 17 #define SYS_COUNTER_FREQ_IN_MHZ (24) 18 19 /* Timer */ 20 #define SEC_TIMER0_BASE (0xF8008000) 21 #define TIMER00_LOAD (SEC_TIMER0_BASE + 0x000) 22 #define TIMER00_VALUE (SEC_TIMER0_BASE + 0x004) 23 #define TIMER00_CONTROL (SEC_TIMER0_BASE + 0x008) 24 #define TIMER00_BGLOAD (SEC_TIMER0_BASE + 0x018) 25 26 #define SEC_TIMER2_BASE (0xF8009000) 27 #define TIMER20_LOAD (SEC_TIMER2_BASE + 0x000) 28 #define TIMER20_VALUE (SEC_TIMER2_BASE + 0x004) 29 #define TIMER20_CONTROL (SEC_TIMER2_BASE + 0x008) 30 #define TIMER20_BGLOAD (SEC_TIMER2_BASE + 0x018) 31 32 /* GPIO */ 33 #define GPIO_MAX (12) 34 #define GPIO_BASE(x) (x != 5 ? \ 35 0xf820000 + x * 0x1000 : 0xf8004000) 36 37 /* SCTL */ 38 #define REG_BASE_SCTL (0xF8000000) 39 #define REG_SC_GEN12 (0x00B0) 40 41 /* CRG */ 42 #define REG_BASE_CRG (0xF8A22000) 43 #define REG_CPU_LP (0x48) 44 #define REG_CPU_RST (0x50) 45 #define REG_PERI_CRG39 (0x9C) 46 #define REG_PERI_CRG40 (0xA0) 47 48 /* MCI */ 49 #define REG_BASE_MCI (0xF9830000) 50 #define MCI_CDETECT (0x50) 51 #define MCI_VERID (0x6C) 52 #define MCI_VERID_VALUE (0x5342250A) 53 #define MCI_VERID_VALUE2 (0x5342270A) 54 55 /* EMMC */ 56 #define REG_EMMC_PERI_CRG REG_PERI_CRG40 57 #define REG_SDCARD_PERI_CRG REG_PERI_CRG39 58 #define EMMC_CLK_MASK (0x7 << 8) 59 #define EMMC_SRST_REQ (0x1 << 4) 60 #define EMMC_CKEN (0x1 << 1) 61 #define EMMC_BUS_CKEN (0x1 << 0) 62 #define EMMC_CLK_100M (0 << 8) 63 #define EMMC_CLK_50M (1 << 8) 64 #define EMMC_CLK_25M (2 << 8) 65 66 #define EMMC_DESC_SIZE (0xF0000) 67 #define EMMC_INIT_PARAMS(base) \ 68 { .bus_width = EMMC_BUS_WIDTH_8, \ 69 .clk_rate = 25 * 1000 * 1000, \ 70 .desc_base = (base) - EMMC_DESC_SIZE, \ 71 .desc_size = EMMC_DESC_SIZE, \ 72 .flags = EMMC_FLAG_CMD23, \ 73 .reg_base = REG_BASE_MCI, \ 74 } 75 76 /* GIC-400 */ 77 #define GICD_BASE (0xF1001000) 78 #define GICC_BASE (0xF1002000) 79 #define GICR_BASE (0xF1000000) 80 81 /* FIQ platform related define */ 82 #define HISI_IRQ_SEC_SGI_0 8 83 #define HISI_IRQ_SEC_SGI_1 9 84 #define HISI_IRQ_SEC_SGI_2 10 85 #define HISI_IRQ_SEC_SGI_3 11 86 #define HISI_IRQ_SEC_SGI_4 12 87 #define HISI_IRQ_SEC_SGI_5 13 88 #define HISI_IRQ_SEC_SGI_6 14 89 #define HISI_IRQ_SEC_SGI_7 15 90 #define HISI_IRQ_SEC_PPI_0 29 91 #define HISI_IRQ_SEC_TIMER0 60 92 #define HISI_IRQ_SEC_TIMER1 50 93 #define HISI_IRQ_SEC_TIMER2 52 94 #define HISI_IRQ_SEC_TIMER3 88 95 #define HISI_IRQ_SEC_AXI 110 96 97 /* Watchdog */ 98 #define HISI_WDG0_BASE (0xF8A2C000) 99 100 #endif /* __HI3798cv200_H__ */ 101
