1 /* 2 * Copyright 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 /** 25 * @file 26 * @brief Intel Surface Layout 27 * 28 * Header Layout 29 * ------------- 30 * The header is ordered as: 31 * - forward declarations 32 * - macros that may be overridden at compile-time for specific gens 33 * - enums and constants 34 * - structs and unions 35 * - functions 36 */ 37 38 #ifndef ISL_H 39 #define ISL_H 40 41 #include <assert.h> 42 #include <stdbool.h> 43 #include <stdint.h> 44 45 #include "c99_compat.h" 46 #include "util/macros.h" 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 struct gen_device_info; 53 struct brw_image_param; 54 55 #ifndef ISL_DEV_GEN 56 /** 57 * @brief Get the hardware generation of isl_device. 58 * 59 * You can define this as a compile-time constant in the CFLAGS. For example, 60 * `gcc -DISL_DEV_GEN(dev)=9 ...`. 61 */ 62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen) 63 #define ISL_DEV_GEN_SANITIZE(__dev) 64 #else 65 #define ISL_DEV_GEN_SANITIZE(__dev) \ 66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen)) 67 #endif 68 69 #ifndef ISL_DEV_IS_G4X 70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x) 71 #endif 72 73 #ifndef ISL_DEV_IS_HASWELL 74 /** 75 * @brief Get the hardware generation of isl_device. 76 * 77 * You can define this as a compile-time constant in the CFLAGS. For example, 78 * `gcc -DISL_DEV_GEN(dev)=9 ...`. 79 */ 80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell) 81 #endif 82 83 #ifndef ISL_DEV_IS_BAYTRAIL 84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail) 85 #endif 86 87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL 88 /** 89 * You can define this as a compile-time constant in the CFLAGS. For example, 90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`. 91 */ 92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil) 93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) 94 #else 95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \ 96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil)) 97 #endif 98 99 /** 100 * Hardware enumeration SURFACE_FORMAT. 101 * 102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference: 103 * Enumerations: SURFACE_FORMAT. 104 */ 105 enum isl_format { 106 ISL_FORMAT_R32G32B32A32_FLOAT = 0, 107 ISL_FORMAT_R32G32B32A32_SINT = 1, 108 ISL_FORMAT_R32G32B32A32_UINT = 2, 109 ISL_FORMAT_R32G32B32A32_UNORM = 3, 110 ISL_FORMAT_R32G32B32A32_SNORM = 4, 111 ISL_FORMAT_R64G64_FLOAT = 5, 112 ISL_FORMAT_R32G32B32X32_FLOAT = 6, 113 ISL_FORMAT_R32G32B32A32_SSCALED = 7, 114 ISL_FORMAT_R32G32B32A32_USCALED = 8, 115 ISL_FORMAT_R32G32B32A32_SFIXED = 32, 116 ISL_FORMAT_R64G64_PASSTHRU = 33, 117 ISL_FORMAT_R32G32B32_FLOAT = 64, 118 ISL_FORMAT_R32G32B32_SINT = 65, 119 ISL_FORMAT_R32G32B32_UINT = 66, 120 ISL_FORMAT_R32G32B32_UNORM = 67, 121 ISL_FORMAT_R32G32B32_SNORM = 68, 122 ISL_FORMAT_R32G32B32_SSCALED = 69, 123 ISL_FORMAT_R32G32B32_USCALED = 70, 124 ISL_FORMAT_R32G32B32_SFIXED = 80, 125 ISL_FORMAT_R16G16B16A16_UNORM = 128, 126 ISL_FORMAT_R16G16B16A16_SNORM = 129, 127 ISL_FORMAT_R16G16B16A16_SINT = 130, 128 ISL_FORMAT_R16G16B16A16_UINT = 131, 129 ISL_FORMAT_R16G16B16A16_FLOAT = 132, 130 ISL_FORMAT_R32G32_FLOAT = 133, 131 ISL_FORMAT_R32G32_SINT = 134, 132 ISL_FORMAT_R32G32_UINT = 135, 133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136, 134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137, 135 ISL_FORMAT_L32A32_FLOAT = 138, 136 ISL_FORMAT_R32G32_UNORM = 139, 137 ISL_FORMAT_R32G32_SNORM = 140, 138 ISL_FORMAT_R64_FLOAT = 141, 139 ISL_FORMAT_R16G16B16X16_UNORM = 142, 140 ISL_FORMAT_R16G16B16X16_FLOAT = 143, 141 ISL_FORMAT_A32X32_FLOAT = 144, 142 ISL_FORMAT_L32X32_FLOAT = 145, 143 ISL_FORMAT_I32X32_FLOAT = 146, 144 ISL_FORMAT_R16G16B16A16_SSCALED = 147, 145 ISL_FORMAT_R16G16B16A16_USCALED = 148, 146 ISL_FORMAT_R32G32_SSCALED = 149, 147 ISL_FORMAT_R32G32_USCALED = 150, 148 ISL_FORMAT_R32G32_FLOAT_LD = 151, 149 ISL_FORMAT_R32G32_SFIXED = 160, 150 ISL_FORMAT_R64_PASSTHRU = 161, 151 ISL_FORMAT_B8G8R8A8_UNORM = 192, 152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193, 153 ISL_FORMAT_R10G10B10A2_UNORM = 194, 154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195, 155 ISL_FORMAT_R10G10B10A2_UINT = 196, 156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197, 157 ISL_FORMAT_R8G8B8A8_UNORM = 199, 158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200, 159 ISL_FORMAT_R8G8B8A8_SNORM = 201, 160 ISL_FORMAT_R8G8B8A8_SINT = 202, 161 ISL_FORMAT_R8G8B8A8_UINT = 203, 162 ISL_FORMAT_R16G16_UNORM = 204, 163 ISL_FORMAT_R16G16_SNORM = 205, 164 ISL_FORMAT_R16G16_SINT = 206, 165 ISL_FORMAT_R16G16_UINT = 207, 166 ISL_FORMAT_R16G16_FLOAT = 208, 167 ISL_FORMAT_B10G10R10A2_UNORM = 209, 168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210, 169 ISL_FORMAT_R11G11B10_FLOAT = 211, 170 ISL_FORMAT_R32_SINT = 214, 171 ISL_FORMAT_R32_UINT = 215, 172 ISL_FORMAT_R32_FLOAT = 216, 173 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217, 174 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218, 175 ISL_FORMAT_L32_UNORM = 221, 176 ISL_FORMAT_A32_UNORM = 222, 177 ISL_FORMAT_L16A16_UNORM = 223, 178 ISL_FORMAT_I24X8_UNORM = 224, 179 ISL_FORMAT_L24X8_UNORM = 225, 180 ISL_FORMAT_A24X8_UNORM = 226, 181 ISL_FORMAT_I32_FLOAT = 227, 182 ISL_FORMAT_L32_FLOAT = 228, 183 ISL_FORMAT_A32_FLOAT = 229, 184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230, 185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231, 186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232, 187 ISL_FORMAT_B8G8R8X8_UNORM = 233, 188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234, 189 ISL_FORMAT_R8G8B8X8_UNORM = 235, 190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236, 191 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237, 192 ISL_FORMAT_B10G10R10X2_UNORM = 238, 193 ISL_FORMAT_L16A16_FLOAT = 240, 194 ISL_FORMAT_R32_UNORM = 241, 195 ISL_FORMAT_R32_SNORM = 242, 196 ISL_FORMAT_R10G10B10X2_USCALED = 243, 197 ISL_FORMAT_R8G8B8A8_SSCALED = 244, 198 ISL_FORMAT_R8G8B8A8_USCALED = 245, 199 ISL_FORMAT_R16G16_SSCALED = 246, 200 ISL_FORMAT_R16G16_USCALED = 247, 201 ISL_FORMAT_R32_SSCALED = 248, 202 ISL_FORMAT_R32_USCALED = 249, 203 ISL_FORMAT_B5G6R5_UNORM = 256, 204 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257, 205 ISL_FORMAT_B5G5R5A1_UNORM = 258, 206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259, 207 ISL_FORMAT_B4G4R4A4_UNORM = 260, 208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261, 209 ISL_FORMAT_R8G8_UNORM = 262, 210 ISL_FORMAT_R8G8_SNORM = 263, 211 ISL_FORMAT_R8G8_SINT = 264, 212 ISL_FORMAT_R8G8_UINT = 265, 213 ISL_FORMAT_R16_UNORM = 266, 214 ISL_FORMAT_R16_SNORM = 267, 215 ISL_FORMAT_R16_SINT = 268, 216 ISL_FORMAT_R16_UINT = 269, 217 ISL_FORMAT_R16_FLOAT = 270, 218 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271, 219 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272, 220 ISL_FORMAT_I16_UNORM = 273, 221 ISL_FORMAT_L16_UNORM = 274, 222 ISL_FORMAT_A16_UNORM = 275, 223 ISL_FORMAT_L8A8_UNORM = 276, 224 ISL_FORMAT_I16_FLOAT = 277, 225 ISL_FORMAT_L16_FLOAT = 278, 226 ISL_FORMAT_A16_FLOAT = 279, 227 ISL_FORMAT_L8A8_UNORM_SRGB = 280, 228 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281, 229 ISL_FORMAT_B5G5R5X1_UNORM = 282, 230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283, 231 ISL_FORMAT_R8G8_SSCALED = 284, 232 ISL_FORMAT_R8G8_USCALED = 285, 233 ISL_FORMAT_R16_SSCALED = 286, 234 ISL_FORMAT_R16_USCALED = 287, 235 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290, 236 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291, 237 ISL_FORMAT_A1B5G5R5_UNORM = 292, 238 ISL_FORMAT_A4B4G4R4_UNORM = 293, 239 ISL_FORMAT_L8A8_UINT = 294, 240 ISL_FORMAT_L8A8_SINT = 295, 241 ISL_FORMAT_R8_UNORM = 320, 242 ISL_FORMAT_R8_SNORM = 321, 243 ISL_FORMAT_R8_SINT = 322, 244 ISL_FORMAT_R8_UINT = 323, 245 ISL_FORMAT_A8_UNORM = 324, 246 ISL_FORMAT_I8_UNORM = 325, 247 ISL_FORMAT_L8_UNORM = 326, 248 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327, 249 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328, 250 ISL_FORMAT_R8_SSCALED = 329, 251 ISL_FORMAT_R8_USCALED = 330, 252 ISL_FORMAT_P8_UNORM_PALETTE0 = 331, 253 ISL_FORMAT_L8_UNORM_SRGB = 332, 254 ISL_FORMAT_P8_UNORM_PALETTE1 = 333, 255 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334, 256 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335, 257 ISL_FORMAT_Y8_UNORM = 336, 258 ISL_FORMAT_L8_UINT = 338, 259 ISL_FORMAT_L8_SINT = 339, 260 ISL_FORMAT_I8_UINT = 340, 261 ISL_FORMAT_I8_SINT = 341, 262 ISL_FORMAT_DXT1_RGB_SRGB = 384, 263 ISL_FORMAT_R1_UNORM = 385, 264 ISL_FORMAT_YCRCB_NORMAL = 386, 265 ISL_FORMAT_YCRCB_SWAPUVY = 387, 266 ISL_FORMAT_P2_UNORM_PALETTE0 = 388, 267 ISL_FORMAT_P2_UNORM_PALETTE1 = 389, 268 ISL_FORMAT_BC1_UNORM = 390, 269 ISL_FORMAT_BC2_UNORM = 391, 270 ISL_FORMAT_BC3_UNORM = 392, 271 ISL_FORMAT_BC4_UNORM = 393, 272 ISL_FORMAT_BC5_UNORM = 394, 273 ISL_FORMAT_BC1_UNORM_SRGB = 395, 274 ISL_FORMAT_BC2_UNORM_SRGB = 396, 275 ISL_FORMAT_BC3_UNORM_SRGB = 397, 276 ISL_FORMAT_MONO8 = 398, 277 ISL_FORMAT_YCRCB_SWAPUV = 399, 278 ISL_FORMAT_YCRCB_SWAPY = 400, 279 ISL_FORMAT_DXT1_RGB = 401, 280 ISL_FORMAT_FXT1 = 402, 281 ISL_FORMAT_R8G8B8_UNORM = 403, 282 ISL_FORMAT_R8G8B8_SNORM = 404, 283 ISL_FORMAT_R8G8B8_SSCALED = 405, 284 ISL_FORMAT_R8G8B8_USCALED = 406, 285 ISL_FORMAT_R64G64B64A64_FLOAT = 407, 286 ISL_FORMAT_R64G64B64_FLOAT = 408, 287 ISL_FORMAT_BC4_SNORM = 409, 288 ISL_FORMAT_BC5_SNORM = 410, 289 ISL_FORMAT_R16G16B16_FLOAT = 411, 290 ISL_FORMAT_R16G16B16_UNORM = 412, 291 ISL_FORMAT_R16G16B16_SNORM = 413, 292 ISL_FORMAT_R16G16B16_SSCALED = 414, 293 ISL_FORMAT_R16G16B16_USCALED = 415, 294 ISL_FORMAT_BC6H_SF16 = 417, 295 ISL_FORMAT_BC7_UNORM = 418, 296 ISL_FORMAT_BC7_UNORM_SRGB = 419, 297 ISL_FORMAT_BC6H_UF16 = 420, 298 ISL_FORMAT_PLANAR_420_8 = 421, 299 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424, 300 ISL_FORMAT_ETC1_RGB8 = 425, 301 ISL_FORMAT_ETC2_RGB8 = 426, 302 ISL_FORMAT_EAC_R11 = 427, 303 ISL_FORMAT_EAC_RG11 = 428, 304 ISL_FORMAT_EAC_SIGNED_R11 = 429, 305 ISL_FORMAT_EAC_SIGNED_RG11 = 430, 306 ISL_FORMAT_ETC2_SRGB8 = 431, 307 ISL_FORMAT_R16G16B16_UINT = 432, 308 ISL_FORMAT_R16G16B16_SINT = 433, 309 ISL_FORMAT_R32_SFIXED = 434, 310 ISL_FORMAT_R10G10B10A2_SNORM = 435, 311 ISL_FORMAT_R10G10B10A2_USCALED = 436, 312 ISL_FORMAT_R10G10B10A2_SSCALED = 437, 313 ISL_FORMAT_R10G10B10A2_SINT = 438, 314 ISL_FORMAT_B10G10R10A2_SNORM = 439, 315 ISL_FORMAT_B10G10R10A2_USCALED = 440, 316 ISL_FORMAT_B10G10R10A2_SSCALED = 441, 317 ISL_FORMAT_B10G10R10A2_UINT = 442, 318 ISL_FORMAT_B10G10R10A2_SINT = 443, 319 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444, 320 ISL_FORMAT_R64G64B64_PASSTHRU = 445, 321 ISL_FORMAT_ETC2_RGB8_PTA = 448, 322 ISL_FORMAT_ETC2_SRGB8_PTA = 449, 323 ISL_FORMAT_ETC2_EAC_RGBA8 = 450, 324 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451, 325 ISL_FORMAT_R8G8B8_UINT = 456, 326 ISL_FORMAT_R8G8B8_SINT = 457, 327 ISL_FORMAT_RAW = 511, 328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512, 329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520, 330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521, 331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529, 332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530, 333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545, 334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546, 335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548, 336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561, 337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562, 338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564, 339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566, 340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574, 341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575, 342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576, 343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584, 344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585, 345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593, 346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594, 347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609, 348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610, 349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612, 350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625, 351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626, 352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628, 353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630, 354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638, 355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639, 356 357 /* The formats that follow are internal to ISL and as such don't have an 358 * explicit number. We'll just let the C compiler assign it for us. Any 359 * actual hardware formats *must* come before these in the list. 360 */ 361 362 /* Formats for auxiliary surfaces */ 363 ISL_FORMAT_HIZ, 364 ISL_FORMAT_MCS_2X, 365 ISL_FORMAT_MCS_4X, 366 ISL_FORMAT_MCS_8X, 367 ISL_FORMAT_MCS_16X, 368 ISL_FORMAT_GEN7_CCS_32BPP_X, 369 ISL_FORMAT_GEN7_CCS_64BPP_X, 370 ISL_FORMAT_GEN7_CCS_128BPP_X, 371 ISL_FORMAT_GEN7_CCS_32BPP_Y, 372 ISL_FORMAT_GEN7_CCS_64BPP_Y, 373 ISL_FORMAT_GEN7_CCS_128BPP_Y, 374 ISL_FORMAT_GEN9_CCS_32BPP, 375 ISL_FORMAT_GEN9_CCS_64BPP, 376 ISL_FORMAT_GEN9_CCS_128BPP, 377 378 /* Hardware doesn't understand this out-of-band value */ 379 ISL_FORMAT_UNSUPPORTED = UINT16_MAX, 380 }; 381 382 /** 383 * Numerical base type for channels of isl_format. 384 */ 385 enum isl_base_type { 386 ISL_VOID, 387 ISL_RAW, 388 ISL_UNORM, 389 ISL_SNORM, 390 ISL_UFLOAT, 391 ISL_SFLOAT, 392 ISL_UFIXED, 393 ISL_SFIXED, 394 ISL_UINT, 395 ISL_SINT, 396 ISL_USCALED, 397 ISL_SSCALED, 398 }; 399 400 /** 401 * Colorspace of isl_format. 402 */ 403 enum isl_colorspace { 404 ISL_COLORSPACE_NONE = 0, 405 ISL_COLORSPACE_LINEAR, 406 ISL_COLORSPACE_SRGB, 407 ISL_COLORSPACE_YUV, 408 }; 409 410 /** 411 * Texture compression mode of isl_format. 412 */ 413 enum isl_txc { 414 ISL_TXC_NONE = 0, 415 ISL_TXC_DXT1, 416 ISL_TXC_DXT3, 417 ISL_TXC_DXT5, 418 ISL_TXC_FXT1, 419 ISL_TXC_RGTC1, 420 ISL_TXC_RGTC2, 421 ISL_TXC_BPTC, 422 ISL_TXC_ETC1, 423 ISL_TXC_ETC2, 424 ISL_TXC_ASTC, 425 426 /* Used for auxiliary surface formats */ 427 ISL_TXC_HIZ, 428 ISL_TXC_MCS, 429 ISL_TXC_CCS, 430 }; 431 432 /** 433 * @brief Hardware tile mode 434 * 435 * WARNING: These values differ from the hardware enum values, which are 436 * unstable across hardware generations. 437 * 438 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to 439 * clearly distinguish it from Yf and Ys. 440 */ 441 enum isl_tiling { 442 ISL_TILING_LINEAR = 0, 443 ISL_TILING_W, 444 ISL_TILING_X, 445 ISL_TILING_Y0, /**< Legacy Y tiling */ 446 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */ 447 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */ 448 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */ 449 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */ 450 }; 451 452 /** 453 * @defgroup Tiling Flags 454 * @{ 455 */ 456 typedef uint32_t isl_tiling_flags_t; 457 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR) 458 #define ISL_TILING_W_BIT (1u << ISL_TILING_W) 459 #define ISL_TILING_X_BIT (1u << ISL_TILING_X) 460 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0) 461 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf) 462 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys) 463 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ) 464 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS) 465 #define ISL_TILING_ANY_MASK (~0u) 466 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT) 467 468 /** Any Y tiling, including legacy Y tiling. */ 469 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \ 470 ISL_TILING_Yf_BIT | \ 471 ISL_TILING_Ys_BIT) 472 473 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */ 474 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \ 475 ISL_TILING_Ys_BIT) 476 /** @} */ 477 478 /** 479 * @brief Logical dimension of surface. 480 * 481 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps 482 * as 2D array surfaces. 483 */ 484 enum isl_surf_dim { 485 ISL_SURF_DIM_1D, 486 ISL_SURF_DIM_2D, 487 ISL_SURF_DIM_3D, 488 }; 489 490 /** 491 * @brief Physical layout of the surface's dimensions. 492 */ 493 enum isl_dim_layout { 494 /** 495 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section 496 * 6.17.3: 2D Surfaces. 497 * 498 * On many gens, 1D surfaces share the same layout as 2D surfaces. From 499 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces: 500 * 501 * One-dimensional surfaces are identical to 2D surfaces with height of 502 * one. 503 * 504 * @invariant isl_surf::phys_level0_sa::depth == 1 505 */ 506 ISL_DIM_LAYOUT_GEN4_2D, 507 508 /** 509 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section 510 * 6.17.5: 3D Surfaces. 511 * 512 * @invariant isl_surf::phys_level0_sa::array_len == 1 513 */ 514 ISL_DIM_LAYOUT_GEN4_3D, 515 516 /** 517 * For details, see the Skylake BSpec >> Memory Views >> Common Surface 518 * Formats >> Surface Layout and Tiling >> 1D Surfaces. 519 */ 520 ISL_DIM_LAYOUT_GEN9_1D, 521 }; 522 523 enum isl_aux_usage { 524 /** No Auxiliary surface is used */ 525 ISL_AUX_USAGE_NONE, 526 527 /** The primary surface is a depth surface and the auxiliary surface is HiZ */ 528 ISL_AUX_USAGE_HIZ, 529 530 /** The auxiliary surface is an MCS 531 * 532 * @invariant isl_surf::samples > 1 533 */ 534 ISL_AUX_USAGE_MCS, 535 536 /** The auxiliary surface is a fast-clear-only compression surface 537 * 538 * @invariant isl_surf::samples == 1 539 */ 540 ISL_AUX_USAGE_CCS_D, 541 542 /** The auxiliary surface provides full lossless color compression 543 * 544 * @invariant isl_surf::samples == 1 545 */ 546 ISL_AUX_USAGE_CCS_E, 547 }; 548 549 /* TODO(chadv): Explain */ 550 enum isl_array_pitch_span { 551 ISL_ARRAY_PITCH_SPAN_FULL, 552 ISL_ARRAY_PITCH_SPAN_COMPACT, 553 }; 554 555 /** 556 * @defgroup Surface Usage 557 * @{ 558 */ 559 typedef uint64_t isl_surf_usage_flags_t; 560 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0) 561 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1) 562 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2) 563 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3) 564 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4) 565 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5) 566 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6) 567 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7) 568 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8) 569 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9) 570 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10) 571 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11) 572 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12) 573 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13) 574 #define ISL_SURF_USAGE_MCS_BIT (1u << 14) 575 #define ISL_SURF_USAGE_CCS_BIT (1u << 15) 576 /** @} */ 577 578 /** 579 * @brief A channel select (also known as texture swizzle) value 580 */ 581 enum isl_channel_select { 582 ISL_CHANNEL_SELECT_ZERO = 0, 583 ISL_CHANNEL_SELECT_ONE = 1, 584 ISL_CHANNEL_SELECT_RED = 4, 585 ISL_CHANNEL_SELECT_GREEN = 5, 586 ISL_CHANNEL_SELECT_BLUE = 6, 587 ISL_CHANNEL_SELECT_ALPHA = 7, 588 }; 589 590 /** 591 * Identical to VkSampleCountFlagBits. 592 */ 593 enum isl_sample_count { 594 ISL_SAMPLE_COUNT_1_BIT = 1u, 595 ISL_SAMPLE_COUNT_2_BIT = 2u, 596 ISL_SAMPLE_COUNT_4_BIT = 4u, 597 ISL_SAMPLE_COUNT_8_BIT = 8u, 598 ISL_SAMPLE_COUNT_16_BIT = 16u, 599 }; 600 typedef uint32_t isl_sample_count_mask_t; 601 602 /** 603 * @brief Multisample Format 604 */ 605 enum isl_msaa_layout { 606 /** 607 * @brief Suface is single-sampled. 608 */ 609 ISL_MSAA_LAYOUT_NONE, 610 611 /** 612 * @brief [SNB+] Interleaved Multisample Format 613 * 614 * In this format, multiple samples are interleaved into each cacheline. 615 * In other words, the sample index is swizzled into the low 6 bits of the 616 * surface's virtual address space. 617 * 618 * For example, suppose the surface is legacy Y tiled, is 4x multisampled, 619 * and its pixel format is 32bpp. Then the first cacheline is arranged 620 * thus: 621 * 622 * (0,0,0) (0,1,0) (0,0,1) (1,0,1) 623 * (1,0,0) (1,1,0) (0,1,1) (1,1,1) 624 * 625 * (0,0,2) (1,0,2) (0,0,3) (1,0,3) 626 * (0,1,2) (1,1,2) (0,1,3) (1,1,3) 627 * 628 * The hardware docs refer to this format with multiple terms. In 629 * Sandybridge, this is the only multisample format; so no term is used. 630 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved 631 * Multisample Surface). Later hardware docs additionally refer to this 632 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for 633 * color surfaces). 634 * 635 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled 636 * Surface Behavior". 637 * 638 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved 639 * Multisampled Surfaces". 640 */ 641 ISL_MSAA_LAYOUT_INTERLEAVED, 642 643 /** 644 * @brief [IVB+] Array Multisample Format 645 * 646 * In this format, the surface's physical layout resembles that of a 647 * 2D array surface. 648 * 649 * Suppose the multisample surface's logical extent is (w, h) and its 650 * sample count is N. Then surface's physical extent is the same as 651 * a singlesample 2D surface whose logical extent is (w, h) and array 652 * length is N. Array slice `i` contains the pixel values for sample 653 * index `i`. 654 * 655 * The Ivybridge docs refer to surfaces in this format as UMS 656 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample 657 * Surface). The Broadwell docs additionally refer to this format as 658 * MSFMT_MSS (MSS=Multisample Surface Storage). 659 * 660 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed 661 * Multisample Surfaces". 662 * 663 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed 664 * Multisample Surfaces". 665 */ 666 ISL_MSAA_LAYOUT_ARRAY, 667 }; 668 669 670 struct isl_device { 671 const struct gen_device_info *info; 672 bool use_separate_stencil; 673 bool has_bit6_swizzling; 674 675 /** 676 * Describes the layout of a RENDER_SURFACE_STATE structure for the 677 * current gen. 678 */ 679 struct { 680 uint8_t size; 681 uint8_t align; 682 uint8_t addr_offset; 683 uint8_t aux_addr_offset; 684 } ss; 685 }; 686 687 struct isl_extent2d { 688 union { uint32_t w, width; }; 689 union { uint32_t h, height; }; 690 }; 691 692 struct isl_extent3d { 693 union { uint32_t w, width; }; 694 union { uint32_t h, height; }; 695 union { uint32_t d, depth; }; 696 }; 697 698 struct isl_extent4d { 699 union { uint32_t w, width; }; 700 union { uint32_t h, height; }; 701 union { uint32_t d, depth; }; 702 union { uint32_t a, array_len; }; 703 }; 704 705 struct isl_channel_layout { 706 enum isl_base_type type; 707 uint8_t bits; /**< Size in bits */ 708 }; 709 710 /** 711 * Each format has 3D block extent (width, height, depth). The block extent of 712 * compressed formats is that of the format's compression block. For example, 713 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block 714 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is 715 * is (w=1, h=1, d=1). 716 */ 717 struct isl_format_layout { 718 enum isl_format format; 719 const char *name; 720 721 uint16_t bpb; /**< Bits per block */ 722 uint8_t bw; /**< Block width, in pixels */ 723 uint8_t bh; /**< Block height, in pixels */ 724 uint8_t bd; /**< Block depth, in pixels */ 725 726 struct { 727 struct isl_channel_layout r; /**< Red channel */ 728 struct isl_channel_layout g; /**< Green channel */ 729 struct isl_channel_layout b; /**< Blue channel */ 730 struct isl_channel_layout a; /**< Alpha channel */ 731 struct isl_channel_layout l; /**< Luminance channel */ 732 struct isl_channel_layout i; /**< Intensity channel */ 733 struct isl_channel_layout p; /**< Palette channel */ 734 } channels; 735 736 enum isl_colorspace colorspace; 737 enum isl_txc txc; 738 }; 739 740 struct isl_tile_info { 741 enum isl_tiling tiling; 742 743 /* The size (in bits per block) of a single surface element 744 * 745 * For surfaces with power-of-two formats, this is the same as 746 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller. 747 * The logical_extent_el field is in terms of elements of this size. 748 * 749 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which 750 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none 751 * of the tiling formats can actually hold an integer number of 96-bit 752 * surface elements so isl_tiling_get_info returns an isl_tile_info for a 753 * 32-bit element size. It is the responsibility of the caller to 754 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute 755 * the width of a surface in tiles, you would do: 756 * 757 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb), 758 * tile_info.logical_extent_el.width); 759 */ 760 uint32_t format_bpb; 761 762 /** The logical size of the tile in units of format_bpb size elements 763 * 764 * This field determines how a given surface is cut up into tiles. It is 765 * used to compute the size of a surface in tiles and can be used to 766 * determine the location of the tile containing any given surface element. 767 * The exact value of this field depends heavily on the bits-per-block of 768 * the format being used. 769 */ 770 struct isl_extent2d logical_extent_el; 771 772 /** The physical size of the tile in bytes and rows of bytes 773 * 774 * This field determines how the tiles of a surface are physically layed 775 * out in memory. The logical and physical tile extent are frequently the 776 * same but this is not always the case. For instance, a W-tile (which is 777 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but 778 * its physical size is 128B x 32rows, the same as a Y-tile. 779 * 780 * @see isl_surf::row_pitch 781 */ 782 struct isl_extent2d phys_extent_B; 783 }; 784 785 /** 786 * @brief Input to surface initialization 787 * 788 * @invariant width >= 1 789 * @invariant height >= 1 790 * @invariant depth >= 1 791 * @invariant levels >= 1 792 * @invariant samples >= 1 793 * @invariant array_len >= 1 794 * 795 * @invariant if 1D then height == 1 and depth == 1 and samples == 1 796 * @invariant if 2D then depth == 1 797 * @invariant if 3D then array_len == 1 and samples == 1 798 */ 799 struct isl_surf_init_info { 800 enum isl_surf_dim dim; 801 enum isl_format format; 802 803 uint32_t width; 804 uint32_t height; 805 uint32_t depth; 806 uint32_t levels; 807 uint32_t array_len; 808 uint32_t samples; 809 810 /** Lower bound for isl_surf::alignment, in bytes. */ 811 uint32_t min_alignment; 812 813 /** Lower bound for isl_surf::pitch, in bytes. */ 814 uint32_t min_pitch; 815 816 isl_surf_usage_flags_t usage; 817 818 /** Flags that alter how ISL selects isl_surf::tiling. */ 819 isl_tiling_flags_t tiling_flags; 820 }; 821 822 struct isl_surf { 823 enum isl_surf_dim dim; 824 enum isl_dim_layout dim_layout; 825 enum isl_msaa_layout msaa_layout; 826 enum isl_tiling tiling; 827 enum isl_format format; 828 829 /** 830 * Alignment of the upper-left sample of each subimage, in units of surface 831 * elements. 832 */ 833 struct isl_extent3d image_alignment_el; 834 835 /** 836 * Logical extent of the surface's base level, in units of pixels. This is 837 * identical to the extent defined in isl_surf_init_info. 838 */ 839 struct isl_extent4d logical_level0_px; 840 841 /** 842 * Physical extent of the surface's base level, in units of physical 843 * surface samples and aligned to the format's compression block. 844 * 845 * Consider isl_dim_layout as an operator that transforms a logical surface 846 * layout to a physical surface layout. Then 847 * 848 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px) 849 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout 850 */ 851 struct isl_extent4d phys_level0_sa; 852 853 uint32_t levels; 854 uint32_t samples; 855 856 /** Total size of the surface, in bytes. */ 857 uint32_t size; 858 859 /** Required alignment for the surface's base address. */ 860 uint32_t alignment; 861 862 /** 863 * The interpretation of this field depends on the value of 864 * isl_tile_info::physical_extent_B. In particular, the width of the 865 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width 866 * and the distance in bytes between vertically adjacent tiles in the image 867 * is given by row_pitch * isl_tile_info::physical_extent_B.height. 868 * 869 * For linear images where isl_tile_info::physical_extent_B.height == 1, 870 * this cleanly reduces to being the distance, in bytes, between vertically 871 * adjacent surface elements. 872 * 873 * @see isl_tile_info::phys_extent_B; 874 */ 875 uint32_t row_pitch; 876 877 /** 878 * Pitch between physical array slices, in rows of surface elements. 879 */ 880 uint32_t array_pitch_el_rows; 881 882 enum isl_array_pitch_span array_pitch_span; 883 884 /** Copy of isl_surf_init_info::usage. */ 885 isl_surf_usage_flags_t usage; 886 }; 887 888 struct isl_swizzle { 889 enum isl_channel_select r:4; 890 enum isl_channel_select g:4; 891 enum isl_channel_select b:4; 892 enum isl_channel_select a:4; 893 }; 894 895 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \ 896 .r = ISL_CHANNEL_SELECT_##R, \ 897 .g = ISL_CHANNEL_SELECT_##G, \ 898 .b = ISL_CHANNEL_SELECT_##B, \ 899 .a = ISL_CHANNEL_SELECT_##A, \ 900 }) 901 902 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA) 903 904 struct isl_view { 905 /** 906 * Indicates the usage of the particular view 907 * 908 * Normally, this is one bit. However, for a cube map texture, it 909 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT. 910 */ 911 isl_surf_usage_flags_t usage; 912 913 /** 914 * The format to use in the view 915 * 916 * This may differ from the format of the actual isl_surf but must have 917 * the same block size. 918 */ 919 enum isl_format format; 920 921 uint32_t base_level; 922 uint32_t levels; 923 924 /** 925 * Base array layer 926 * 927 * For cube maps, both base_array_layer and array_len should be 928 * specified in terms of 2-D layers and must be a multiple of 6. 929 * 930 * 3-D textures are effectively treated as 2-D arrays when used as a 931 * storage image or render target. If `usage` contains 932 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then 933 * base_array_layer and array_len are applied. If the surface is only used 934 * for texturing, they are ignored. 935 */ 936 uint32_t base_array_layer; 937 uint32_t array_len; 938 939 struct isl_swizzle swizzle; 940 }; 941 942 union isl_color_value { 943 float f32[4]; 944 uint32_t u32[4]; 945 int32_t i32[4]; 946 }; 947 948 struct isl_surf_fill_state_info { 949 const struct isl_surf *surf; 950 const struct isl_view *view; 951 952 /** 953 * The address of the surface in GPU memory. 954 */ 955 uint64_t address; 956 957 /** 958 * The Memory Object Control state for the filled surface state. 959 * 960 * The exact format of this value depends on hardware generation. 961 */ 962 uint32_t mocs; 963 964 /** 965 * The auxilary surface or NULL if no auxilary surface is to be used. 966 */ 967 const struct isl_surf *aux_surf; 968 enum isl_aux_usage aux_usage; 969 uint64_t aux_address; 970 971 /** 972 * The clear color for this surface 973 * 974 * Valid values depend on hardware generation. 975 */ 976 union isl_color_value clear_color; 977 978 /* Intra-tile offset */ 979 uint16_t x_offset_sa, y_offset_sa; 980 }; 981 982 struct isl_buffer_fill_state_info { 983 /** 984 * The address of the surface in GPU memory. 985 */ 986 uint64_t address; 987 988 /** 989 * The size of the buffer 990 */ 991 uint64_t size; 992 993 /** 994 * The Memory Object Control state for the filled surface state. 995 * 996 * The exact format of this value depends on hardware generation. 997 */ 998 uint32_t mocs; 999 1000 /** 1001 * The format to use in the surface state 1002 * 1003 * This may differ from the format of the actual isl_surf but have the 1004 * same block size. 1005 */ 1006 enum isl_format format; 1007 1008 uint32_t stride; 1009 }; 1010 1011 extern const struct isl_format_layout isl_format_layouts[]; 1012 1013 void 1014 isl_device_init(struct isl_device *dev, 1015 const struct gen_device_info *info, 1016 bool has_bit6_swizzling); 1017 1018 isl_sample_count_mask_t ATTRIBUTE_CONST 1019 isl_device_get_sample_counts(struct isl_device *dev); 1020 1021 static inline const struct isl_format_layout * ATTRIBUTE_CONST 1022 isl_format_get_layout(enum isl_format fmt) 1023 { 1024 return &isl_format_layouts[fmt]; 1025 } 1026 1027 static inline const char * ATTRIBUTE_CONST 1028 isl_format_get_name(enum isl_format fmt) 1029 { 1030 return isl_format_layouts[fmt].name; 1031 } 1032 1033 bool isl_format_supports_rendering(const struct gen_device_info *devinfo, 1034 enum isl_format format); 1035 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo, 1036 enum isl_format format); 1037 bool isl_format_supports_sampling(const struct gen_device_info *devinfo, 1038 enum isl_format format); 1039 bool isl_format_supports_filtering(const struct gen_device_info *devinfo, 1040 enum isl_format format); 1041 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo, 1042 enum isl_format format); 1043 bool isl_format_supports_lossless_compression(const struct gen_device_info *devinfo, 1044 enum isl_format format); 1045 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo, 1046 enum isl_format format); 1047 1048 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST; 1049 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST; 1050 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST; 1051 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST; 1052 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST; 1053 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST; 1054 1055 static inline bool 1056 isl_format_has_normalized_channel(enum isl_format fmt) 1057 { 1058 return isl_format_has_unorm_channel(fmt) || 1059 isl_format_has_snorm_channel(fmt); 1060 } 1061 1062 static inline bool 1063 isl_format_has_float_channel(enum isl_format fmt) 1064 { 1065 return isl_format_has_ufloat_channel(fmt) || 1066 isl_format_has_sfloat_channel(fmt); 1067 } 1068 1069 static inline bool 1070 isl_format_has_int_channel(enum isl_format fmt) 1071 { 1072 return isl_format_has_uint_channel(fmt) || 1073 isl_format_has_sint_channel(fmt); 1074 } 1075 1076 unsigned isl_format_get_num_channels(enum isl_format fmt); 1077 1078 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil); 1079 1080 static inline bool 1081 isl_format_is_compressed(enum isl_format fmt) 1082 { 1083 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); 1084 1085 return fmtl->txc != ISL_TXC_NONE; 1086 } 1087 1088 static inline bool 1089 isl_format_has_bc_compression(enum isl_format fmt) 1090 { 1091 switch (isl_format_get_layout(fmt)->txc) { 1092 case ISL_TXC_DXT1: 1093 case ISL_TXC_DXT3: 1094 case ISL_TXC_DXT5: 1095 return true; 1096 case ISL_TXC_NONE: 1097 case ISL_TXC_FXT1: 1098 case ISL_TXC_RGTC1: 1099 case ISL_TXC_RGTC2: 1100 case ISL_TXC_BPTC: 1101 case ISL_TXC_ETC1: 1102 case ISL_TXC_ETC2: 1103 case ISL_TXC_ASTC: 1104 return false; 1105 1106 case ISL_TXC_HIZ: 1107 case ISL_TXC_MCS: 1108 case ISL_TXC_CCS: 1109 unreachable("Should not be called on an aux surface"); 1110 } 1111 1112 unreachable("bad texture compression mode"); 1113 return false; 1114 } 1115 1116 static inline bool 1117 isl_format_is_yuv(enum isl_format fmt) 1118 { 1119 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); 1120 1121 return fmtl->colorspace == ISL_COLORSPACE_YUV; 1122 } 1123 1124 static inline bool 1125 isl_format_block_is_1x1x1(enum isl_format fmt) 1126 { 1127 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); 1128 1129 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1; 1130 } 1131 1132 static inline bool 1133 isl_format_is_rgb(enum isl_format fmt) 1134 { 1135 return isl_format_layouts[fmt].channels.r.bits > 0 && 1136 isl_format_layouts[fmt].channels.g.bits > 0 && 1137 isl_format_layouts[fmt].channels.b.bits > 0 && 1138 isl_format_layouts[fmt].channels.a.bits == 0; 1139 } 1140 1141 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST; 1142 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST; 1143 1144 bool isl_is_storage_image_format(enum isl_format fmt); 1145 1146 enum isl_format 1147 isl_lower_storage_image_format(const struct gen_device_info *devinfo, 1148 enum isl_format fmt); 1149 1150 /* Returns true if this hardware supports typed load/store on a format with 1151 * the same size as the given format. 1152 */ 1153 bool 1154 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo, 1155 enum isl_format fmt); 1156 1157 static inline bool 1158 isl_tiling_is_any_y(enum isl_tiling tiling) 1159 { 1160 return (1u << tiling) & ISL_TILING_ANY_Y_MASK; 1161 } 1162 1163 static inline bool 1164 isl_tiling_is_std_y(enum isl_tiling tiling) 1165 { 1166 return (1u << tiling) & ISL_TILING_STD_Y_MASK; 1167 } 1168 1169 struct isl_extent2d ATTRIBUTE_CONST 1170 isl_get_interleaved_msaa_px_size_sa(uint32_t samples); 1171 1172 static inline bool 1173 isl_surf_usage_is_display(isl_surf_usage_flags_t usage) 1174 { 1175 return usage & ISL_SURF_USAGE_DISPLAY_BIT; 1176 } 1177 1178 static inline bool 1179 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage) 1180 { 1181 return usage & ISL_SURF_USAGE_DEPTH_BIT; 1182 } 1183 1184 static inline bool 1185 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage) 1186 { 1187 return usage & ISL_SURF_USAGE_STENCIL_BIT; 1188 } 1189 1190 static inline bool 1191 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage) 1192 { 1193 return (usage & ISL_SURF_USAGE_DEPTH_BIT) && 1194 (usage & ISL_SURF_USAGE_STENCIL_BIT); 1195 } 1196 1197 static inline bool 1198 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage) 1199 { 1200 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT); 1201 } 1202 1203 static inline bool 1204 isl_surf_info_is_z16(const struct isl_surf_init_info *info) 1205 { 1206 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && 1207 (info->format == ISL_FORMAT_R16_UNORM); 1208 } 1209 1210 static inline bool 1211 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info) 1212 { 1213 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && 1214 (info->format == ISL_FORMAT_R32_FLOAT); 1215 } 1216 1217 static inline struct isl_extent2d 1218 isl_extent2d(uint32_t width, uint32_t height) 1219 { 1220 struct isl_extent2d e = { { 0 } }; 1221 1222 e.width = width; 1223 e.height = height; 1224 1225 return e; 1226 } 1227 1228 static inline struct isl_extent3d 1229 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth) 1230 { 1231 struct isl_extent3d e = { { 0 } }; 1232 1233 e.width = width; 1234 e.height = height; 1235 e.depth = depth; 1236 1237 return e; 1238 } 1239 1240 static inline struct isl_extent4d 1241 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth, 1242 uint32_t array_len) 1243 { 1244 struct isl_extent4d e = { { 0 } }; 1245 1246 e.width = width; 1247 e.height = height; 1248 e.depth = depth; 1249 e.array_len = array_len; 1250 1251 return e; 1252 } 1253 1254 #define isl_surf_init(dev, surf, ...) \ 1255 isl_surf_init_s((dev), (surf), \ 1256 &(struct isl_surf_init_info) { __VA_ARGS__ }); 1257 1258 bool 1259 isl_surf_init_s(const struct isl_device *dev, 1260 struct isl_surf *surf, 1261 const struct isl_surf_init_info *restrict info); 1262 1263 void 1264 isl_surf_get_tile_info(const struct isl_device *dev, 1265 const struct isl_surf *surf, 1266 struct isl_tile_info *tile_info); 1267 1268 void 1269 isl_surf_get_hiz_surf(const struct isl_device *dev, 1270 const struct isl_surf *surf, 1271 struct isl_surf *hiz_surf); 1272 1273 void 1274 isl_surf_get_mcs_surf(const struct isl_device *dev, 1275 const struct isl_surf *surf, 1276 struct isl_surf *mcs_surf); 1277 1278 bool 1279 isl_surf_get_ccs_surf(const struct isl_device *dev, 1280 const struct isl_surf *surf, 1281 struct isl_surf *ccs_surf); 1282 1283 #define isl_surf_fill_state(dev, state, ...) \ 1284 isl_surf_fill_state_s((dev), (state), \ 1285 &(struct isl_surf_fill_state_info) { __VA_ARGS__ }); 1286 1287 void 1288 isl_surf_fill_state_s(const struct isl_device *dev, void *state, 1289 const struct isl_surf_fill_state_info *restrict info); 1290 1291 #define isl_buffer_fill_state(dev, state, ...) \ 1292 isl_buffer_fill_state_s((dev), (state), \ 1293 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ }); 1294 1295 void 1296 isl_buffer_fill_state_s(const struct isl_device *dev, void *state, 1297 const struct isl_buffer_fill_state_info *restrict info); 1298 1299 void 1300 isl_surf_fill_image_param(const struct isl_device *dev, 1301 struct brw_image_param *param, 1302 const struct isl_surf *surf, 1303 const struct isl_view *view); 1304 1305 void 1306 isl_buffer_fill_image_param(const struct isl_device *dev, 1307 struct brw_image_param *param, 1308 enum isl_format format, 1309 uint64_t size); 1310 1311 /** 1312 * Alignment of the upper-left sample of each subimage, in units of surface 1313 * elements. 1314 */ 1315 static inline struct isl_extent3d 1316 isl_surf_get_image_alignment_el(const struct isl_surf *surf) 1317 { 1318 return surf->image_alignment_el; 1319 } 1320 1321 /** 1322 * Alignment of the upper-left sample of each subimage, in units of surface 1323 * samples. 1324 */ 1325 static inline struct isl_extent3d 1326 isl_surf_get_image_alignment_sa(const struct isl_surf *surf) 1327 { 1328 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); 1329 1330 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w, 1331 fmtl->bh * surf->image_alignment_el.h, 1332 fmtl->bd * surf->image_alignment_el.d); 1333 } 1334 1335 /** 1336 * Pitch between vertically adjacent surface elements, in bytes. 1337 */ 1338 static inline uint32_t 1339 isl_surf_get_row_pitch(const struct isl_surf *surf) 1340 { 1341 return surf->row_pitch; 1342 } 1343 1344 /** 1345 * Pitch between vertically adjacent surface elements, in units of surface elements. 1346 */ 1347 static inline uint32_t 1348 isl_surf_get_row_pitch_el(const struct isl_surf *surf) 1349 { 1350 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); 1351 1352 assert(surf->row_pitch % (fmtl->bpb / 8) == 0); 1353 return surf->row_pitch / (fmtl->bpb / 8); 1354 } 1355 1356 /** 1357 * Pitch between physical array slices, in rows of surface elements. 1358 */ 1359 static inline uint32_t 1360 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf) 1361 { 1362 return surf->array_pitch_el_rows; 1363 } 1364 1365 /** 1366 * Pitch between physical array slices, in units of surface elements. 1367 */ 1368 static inline uint32_t 1369 isl_surf_get_array_pitch_el(const struct isl_surf *surf) 1370 { 1371 return isl_surf_get_array_pitch_el_rows(surf) * 1372 isl_surf_get_row_pitch_el(surf); 1373 } 1374 1375 /** 1376 * Pitch between physical array slices, in rows of surface samples. 1377 */ 1378 static inline uint32_t 1379 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf) 1380 { 1381 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); 1382 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf); 1383 } 1384 1385 /** 1386 * Pitch between physical array slices, in bytes. 1387 */ 1388 static inline uint32_t 1389 isl_surf_get_array_pitch(const struct isl_surf *surf) 1390 { 1391 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch; 1392 } 1393 1394 /** 1395 * Calculate the offset, in units of surface samples, to a subimage in the 1396 * surface. 1397 * 1398 * @invariant level < surface levels 1399 * @invariant logical_array_layer < logical array length of surface 1400 * @invariant logical_z_offset_px < logical depth of surface at level 1401 */ 1402 void 1403 isl_surf_get_image_offset_sa(const struct isl_surf *surf, 1404 uint32_t level, 1405 uint32_t logical_array_layer, 1406 uint32_t logical_z_offset_px, 1407 uint32_t *x_offset_sa, 1408 uint32_t *y_offset_sa); 1409 1410 /** 1411 * Calculate the offset, in units of surface elements, to a subimage in the 1412 * surface. 1413 * 1414 * @invariant level < surface levels 1415 * @invariant logical_array_layer < logical array length of surface 1416 * @invariant logical_z_offset_px < logical depth of surface at level 1417 */ 1418 void 1419 isl_surf_get_image_offset_el(const struct isl_surf *surf, 1420 uint32_t level, 1421 uint32_t logical_array_layer, 1422 uint32_t logical_z_offset_px, 1423 uint32_t *x_offset_el, 1424 uint32_t *y_offset_el); 1425 1426 /** 1427 * @brief Calculate the intratile offsets to a surface. 1428 * 1429 * In @a base_address_offset return the offset from the base of the surface to 1430 * the base address of the first tile of the subimage. In @a x_offset_B and 1431 * @a y_offset_rows, return the offset, in units of bytes and rows, from the 1432 * tile's base to the subimage's first surface element. The x and y offsets 1433 * are intratile offsets; that is, they do not exceed the boundary of the 1434 * surface's tiling format. 1435 */ 1436 void 1437 isl_tiling_get_intratile_offset_el(const struct isl_device *dev, 1438 enum isl_tiling tiling, 1439 uint8_t bs, 1440 uint32_t row_pitch, 1441 uint32_t total_x_offset_el, 1442 uint32_t total_y_offset_el, 1443 uint32_t *base_address_offset, 1444 uint32_t *x_offset_el, 1445 uint32_t *y_offset_el); 1446 1447 static inline void 1448 isl_tiling_get_intratile_offset_sa(const struct isl_device *dev, 1449 enum isl_tiling tiling, 1450 enum isl_format format, 1451 uint32_t row_pitch, 1452 uint32_t total_x_offset_sa, 1453 uint32_t total_y_offset_sa, 1454 uint32_t *base_address_offset, 1455 uint32_t *x_offset_sa, 1456 uint32_t *y_offset_sa) 1457 { 1458 const struct isl_format_layout *fmtl = isl_format_get_layout(format); 1459 1460 assert(fmtl->bpb % 8 == 0); 1461 1462 /* For computing the intratile offsets, we actually want a strange unit 1463 * which is samples for multisampled surfaces but elements for compressed 1464 * surfaces. 1465 */ 1466 assert(total_x_offset_sa % fmtl->bw == 0); 1467 assert(total_y_offset_sa % fmtl->bh == 0); 1468 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw; 1469 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh; 1470 1471 isl_tiling_get_intratile_offset_el(dev, tiling, fmtl->bpb / 8, row_pitch, 1472 total_x_offset, total_y_offset, 1473 base_address_offset, 1474 x_offset_sa, y_offset_sa); 1475 *x_offset_sa *= fmtl->bw; 1476 *y_offset_sa *= fmtl->bh; 1477 } 1478 1479 /** 1480 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat 1481 * 1482 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT 1483 * @pre surf->format must be a valid format for depth surfaces 1484 */ 1485 uint32_t 1486 isl_surf_get_depth_format(const struct isl_device *dev, 1487 const struct isl_surf *surf); 1488 1489 #ifdef __cplusplus 1490 } 1491 #endif 1492 1493 #endif /* ISL_H */ 1494
