1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __ARCH_H__ 8 #define __ARCH_H__ 9 10 #include <utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(0x18) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(0x4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (U(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK U(0xff) 34 #define MPIDR_AFF0_SHIFT U(0) 35 #define MPIDR_AFF1_SHIFT U(8) 36 #define MPIDR_AFF2_SHIFT U(16) 37 #define MPIDR_AFF3_SHIFT U(32) 38 #define MPIDR_AFFINITY_MASK U(0xff00ffffff) 39 #define MPIDR_AFFLVL_SHIFT U(3) 40 #define MPIDR_AFFLVL0 U(0) 41 #define MPIDR_AFFLVL1 U(1) 42 #define MPIDR_AFFLVL2 U(2) 43 #define MPIDR_AFFLVL3 U(3) 44 #define MPIDR_AFFLVL0_VAL(mpidr) \ 45 ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 46 #define MPIDR_AFFLVL1_VAL(mpidr) \ 47 ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 48 #define MPIDR_AFFLVL2_VAL(mpidr) \ 49 ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 50 #define MPIDR_AFFLVL3_VAL(mpidr) \ 51 ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 52 /* 53 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 54 * add one while using this macro to define array sizes. 55 * TODO: Support only the first 3 affinity levels for now. 56 */ 57 #define MPIDR_MAX_AFFLVL U(2) 58 59 /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ 60 #define FIRST_MPIDR U(0) 61 62 /******************************************************************************* 63 * Definitions for CPU system register interface to GICv3 64 ******************************************************************************/ 65 #define ICC_SRE_EL1 S3_0_C12_C12_5 66 #define ICC_SRE_EL2 S3_4_C12_C9_5 67 #define ICC_SRE_EL3 S3_6_C12_C12_5 68 #define ICC_CTLR_EL1 S3_0_C12_C12_4 69 #define ICC_CTLR_EL3 S3_6_C12_C12_4 70 #define ICC_PMR_EL1 S3_0_C4_C6_0 71 #define ICC_RPR_EL1 S3_0_C12_C11_3 72 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 73 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 74 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 75 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 76 #define ICC_IAR0_EL1 S3_0_c12_c8_0 77 #define ICC_IAR1_EL1 S3_0_c12_c12_0 78 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 79 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 80 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 81 82 /******************************************************************************* 83 * Generic timer memory mapped registers & offsets 84 ******************************************************************************/ 85 #define CNTCR_OFF U(0x000) 86 #define CNTFID_OFF U(0x020) 87 88 #define CNTCR_EN (U(1) << 0) 89 #define CNTCR_HDBG (U(1) << 1) 90 #define CNTCR_FCREQ(x) ((x) << 8) 91 92 /******************************************************************************* 93 * System register bit definitions 94 ******************************************************************************/ 95 /* CLIDR definitions */ 96 #define LOUIS_SHIFT U(21) 97 #define LOC_SHIFT U(24) 98 #define CLIDR_FIELD_WIDTH U(3) 99 100 /* CSSELR definitions */ 101 #define LEVEL_SHIFT U(1) 102 103 /* D$ set/way op type defines */ 104 #define DCISW U(0x0) 105 #define DCCISW U(0x1) 106 #define DCCSW U(0x2) 107 108 /* ID_AA64PFR0_EL1 definitions */ 109 #define ID_AA64PFR0_EL0_SHIFT U(0) 110 #define ID_AA64PFR0_EL1_SHIFT U(4) 111 #define ID_AA64PFR0_EL2_SHIFT U(8) 112 #define ID_AA64PFR0_EL3_SHIFT U(12) 113 #define ID_AA64PFR0_ELX_MASK U(0xf) 114 115 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 116 #define ID_AA64DFR0_PMS_SHIFT U(32) 117 #define ID_AA64DFR0_PMS_LENGTH U(4) 118 #define ID_AA64DFR0_PMS_MASK U(0xf) 119 120 #define EL_IMPL_NONE U(0) 121 #define EL_IMPL_A64ONLY U(1) 122 #define EL_IMPL_A64_A32 U(2) 123 124 #define ID_AA64PFR0_GIC_SHIFT U(24) 125 #define ID_AA64PFR0_GIC_WIDTH U(4) 126 #define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1) 127 128 /* ID_AA64MMFR0_EL1 definitions */ 129 #define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf) 130 131 #define PARANGE_0000 U(32) 132 #define PARANGE_0001 U(36) 133 #define PARANGE_0010 U(40) 134 #define PARANGE_0011 U(42) 135 #define PARANGE_0100 U(44) 136 #define PARANGE_0101 U(48) 137 138 /* ID_PFR1_EL1 definitions */ 139 #define ID_PFR1_VIRTEXT_SHIFT U(12) 140 #define ID_PFR1_VIRTEXT_MASK U(0xf) 141 #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ 142 & ID_PFR1_VIRTEXT_MASK) 143 144 /* SCTLR definitions */ 145 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 146 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 147 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 148 149 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 150 (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) 151 #define SCTLR_AARCH32_EL1_RES1 \ 152 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 153 (U(1) << 4) | (U(1) << 3)) 154 155 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 156 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 157 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 158 159 #define SCTLR_M_BIT (U(1) << 0) 160 #define SCTLR_A_BIT (U(1) << 1) 161 #define SCTLR_C_BIT (U(1) << 2) 162 #define SCTLR_SA_BIT (U(1) << 3) 163 #define SCTLR_CP15BEN_BIT (U(1) << 5) 164 #define SCTLR_I_BIT (U(1) << 12) 165 #define SCTLR_NTWI_BIT (U(1) << 16) 166 #define SCTLR_NTWE_BIT (U(1) << 18) 167 #define SCTLR_WXN_BIT (U(1) << 19) 168 #define SCTLR_EE_BIT (U(1) << 25) 169 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 170 171 /* CPACR_El1 definitions */ 172 #define CPACR_EL1_FPEN(x) ((x) << 20) 173 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 174 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 175 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 176 177 /* SCR definitions */ 178 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 179 #define SCR_TWE_BIT (U(1) << 13) 180 #define SCR_TWI_BIT (U(1) << 12) 181 #define SCR_ST_BIT (U(1) << 11) 182 #define SCR_RW_BIT (U(1) << 10) 183 #define SCR_SIF_BIT (U(1) << 9) 184 #define SCR_HCE_BIT (U(1) << 8) 185 #define SCR_SMD_BIT (U(1) << 7) 186 #define SCR_EA_BIT (U(1) << 3) 187 #define SCR_FIQ_BIT (U(1) << 2) 188 #define SCR_IRQ_BIT (U(1) << 1) 189 #define SCR_NS_BIT (U(1) << 0) 190 #define SCR_VALID_BIT_MASK U(0x2f8f) 191 #define SCR_RESET_VAL SCR_RES1_BITS 192 193 /* MDCR_EL3 definitions */ 194 #define MDCR_SPD32(x) ((x) << 14) 195 #define MDCR_SPD32_LEGACY U(0x0) 196 #define MDCR_SPD32_DISABLE U(0x2) 197 #define MDCR_SPD32_ENABLE U(0x3) 198 #define MDCR_SDD_BIT (U(1) << 16) 199 #define MDCR_NSPB(x) ((x) << 12) 200 #define MDCR_NSPB_EL1 U(0x3) 201 #define MDCR_TDOSA_BIT (U(1) << 10) 202 #define MDCR_TDA_BIT (U(1) << 9) 203 #define MDCR_TPM_BIT (U(1) << 6) 204 #define MDCR_EL3_RESET_VAL U(0x0) 205 206 #if !ERROR_DEPRECATED 207 #define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 208 #endif 209 210 /* MDCR_EL2 definitions */ 211 #define MDCR_EL2_TPMS (U(1) << 14) 212 #define MDCR_EL2_E2PB(x) ((x) << 12) 213 #define MDCR_EL2_E2PB_EL1 U(0x3) 214 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 215 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 216 #define MDCR_EL2_TDA_BIT (U(1) << 9) 217 #define MDCR_EL2_TDE_BIT (U(1) << 8) 218 #define MDCR_EL2_HPME_BIT (U(1) << 7) 219 #define MDCR_EL2_TPM_BIT (U(1) << 6) 220 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 221 #define MDCR_EL2_RESET_VAL U(0x0) 222 223 /* HSTR_EL2 definitions */ 224 #define HSTR_EL2_RESET_VAL U(0x0) 225 #define HSTR_EL2_T_MASK U(0xff) 226 227 /* CNTHP_CTL_EL2 definitions */ 228 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 229 #define CNTHP_CTL_RESET_VAL U(0x0) 230 231 /* VTTBR_EL2 definitions */ 232 #define VTTBR_RESET_VAL ULL(0x0) 233 #define VTTBR_VMID_MASK ULL(0xff) 234 #define VTTBR_VMID_SHIFT U(48) 235 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 236 #define VTTBR_BADDR_SHIFT U(0) 237 238 /* HCR definitions */ 239 #define HCR_RW_SHIFT U(31) 240 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 241 #define HCR_AMO_BIT (U(1) << 5) 242 #define HCR_IMO_BIT (U(1) << 4) 243 #define HCR_FMO_BIT (U(1) << 3) 244 245 /* ISR definitions */ 246 #define ISR_A_SHIFT U(8) 247 #define ISR_I_SHIFT U(7) 248 #define ISR_F_SHIFT U(6) 249 250 /* CNTHCTL_EL2 definitions */ 251 #define CNTHCTL_RESET_VAL U(0x0) 252 #define EVNTEN_BIT (U(1) << 2) 253 #define EL1PCEN_BIT (U(1) << 1) 254 #define EL1PCTEN_BIT (U(1) << 0) 255 256 /* CNTKCTL_EL1 definitions */ 257 #define EL0PTEN_BIT (U(1) << 9) 258 #define EL0VTEN_BIT (U(1) << 8) 259 #define EL0PCTEN_BIT (U(1) << 0) 260 #define EL0VCTEN_BIT (U(1) << 1) 261 #define EVNTEN_BIT (U(1) << 2) 262 #define EVNTDIR_BIT (U(1) << 3) 263 #define EVNTI_SHIFT U(4) 264 #define EVNTI_MASK U(0xf) 265 266 /* CPTR_EL3 definitions */ 267 #define TCPAC_BIT (U(1) << 31) 268 #define TTA_BIT (U(1) << 20) 269 #define TFP_BIT (U(1) << 10) 270 #define CPTR_EL3_RESET_VAL U(0x0) 271 272 /* CPTR_EL2 definitions */ 273 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 274 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 275 #define CPTR_EL2_TTA_BIT (U(1) << 20) 276 #define CPTR_EL2_TFP_BIT (U(1) << 10) 277 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 278 279 /* CPSR/SPSR definitions */ 280 #define DAIF_FIQ_BIT (U(1) << 0) 281 #define DAIF_IRQ_BIT (U(1) << 1) 282 #define DAIF_ABT_BIT (U(1) << 2) 283 #define DAIF_DBG_BIT (U(1) << 3) 284 #define SPSR_DAIF_SHIFT U(6) 285 #define SPSR_DAIF_MASK U(0xf) 286 287 #define SPSR_AIF_SHIFT U(6) 288 #define SPSR_AIF_MASK U(0x7) 289 290 #define SPSR_E_SHIFT U(9) 291 #define SPSR_E_MASK U(0x1) 292 #define SPSR_E_LITTLE U(0x0) 293 #define SPSR_E_BIG U(0x1) 294 295 #define SPSR_T_SHIFT U(5) 296 #define SPSR_T_MASK U(0x1) 297 #define SPSR_T_ARM U(0x0) 298 #define SPSR_T_THUMB U(0x1) 299 300 #define DISABLE_ALL_EXCEPTIONS \ 301 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 302 303 /* 304 * RMR_EL3 definitions 305 */ 306 #define RMR_EL3_RR_BIT (U(1) << 1) 307 #define RMR_EL3_AA64_BIT (U(1) << 0) 308 309 /* 310 * HI-VECTOR address for AArch32 state 311 */ 312 #define HI_VECTOR_BASE U(0xFFFF0000) 313 314 /* 315 * TCR defintions 316 */ 317 #define TCR_EL3_RES1 ((U(1) << 31) | (U(1) << 23)) 318 #define TCR_EL1_IPS_SHIFT U(32) 319 #define TCR_EL3_PS_SHIFT U(16) 320 321 #define TCR_TxSZ_MIN U(16) 322 #define TCR_TxSZ_MAX U(39) 323 324 /* (internal) physical address size bits in EL3/EL1 */ 325 #define TCR_PS_BITS_4GB U(0x0) 326 #define TCR_PS_BITS_64GB U(0x1) 327 #define TCR_PS_BITS_1TB U(0x2) 328 #define TCR_PS_BITS_4TB U(0x3) 329 #define TCR_PS_BITS_16TB U(0x4) 330 #define TCR_PS_BITS_256TB U(0x5) 331 332 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 333 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 334 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 335 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 336 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 337 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 338 339 #define TCR_RGN_INNER_NC (U(0x0) << 8) 340 #define TCR_RGN_INNER_WBA (U(0x1) << 8) 341 #define TCR_RGN_INNER_WT (U(0x2) << 8) 342 #define TCR_RGN_INNER_WBNA (U(0x3) << 8) 343 344 #define TCR_RGN_OUTER_NC (U(0x0) << 10) 345 #define TCR_RGN_OUTER_WBA (U(0x1) << 10) 346 #define TCR_RGN_OUTER_WT (U(0x2) << 10) 347 #define TCR_RGN_OUTER_WBNA (U(0x3) << 10) 348 349 #define TCR_SH_NON_SHAREABLE (U(0x0) << 12) 350 #define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12) 351 #define TCR_SH_INNER_SHAREABLE (U(0x3) << 12) 352 353 #define TCR_EPD1_BIT (U(1) << 23) 354 355 #define MODE_SP_SHIFT U(0x0) 356 #define MODE_SP_MASK U(0x1) 357 #define MODE_SP_EL0 U(0x0) 358 #define MODE_SP_ELX U(0x1) 359 360 #define MODE_RW_SHIFT U(0x4) 361 #define MODE_RW_MASK U(0x1) 362 #define MODE_RW_64 U(0x0) 363 #define MODE_RW_32 U(0x1) 364 365 #define MODE_EL_SHIFT U(0x2) 366 #define MODE_EL_MASK U(0x3) 367 #define MODE_EL3 U(0x3) 368 #define MODE_EL2 U(0x2) 369 #define MODE_EL1 U(0x1) 370 #define MODE_EL0 U(0x0) 371 372 #define MODE32_SHIFT U(0) 373 #define MODE32_MASK U(0xf) 374 #define MODE32_usr U(0x0) 375 #define MODE32_fiq U(0x1) 376 #define MODE32_irq U(0x2) 377 #define MODE32_svc U(0x3) 378 #define MODE32_mon U(0x6) 379 #define MODE32_abt U(0x7) 380 #define MODE32_hyp U(0xa) 381 #define MODE32_und U(0xb) 382 #define MODE32_sys U(0xf) 383 384 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 385 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 386 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 387 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 388 389 #define SPSR_64(el, sp, daif) \ 390 (MODE_RW_64 << MODE_RW_SHIFT | \ 391 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ 392 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ 393 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) 394 395 #define SPSR_MODE32(mode, isa, endian, aif) \ 396 ((MODE_RW_32 << MODE_RW_SHIFT) | \ 397 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 398 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 399 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 400 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) 401 402 /* 403 * TTBR Definitions 404 */ 405 #define TTBR_CNP_BIT 0x1 406 407 /* 408 * CTR_EL0 definitions 409 */ 410 #define CTR_CWG_SHIFT U(24) 411 #define CTR_CWG_MASK U(0xf) 412 #define CTR_ERG_SHIFT U(20) 413 #define CTR_ERG_MASK U(0xf) 414 #define CTR_DMINLINE_SHIFT U(16) 415 #define CTR_DMINLINE_MASK U(0xf) 416 #define CTR_L1IP_SHIFT U(14) 417 #define CTR_L1IP_MASK U(0x3) 418 #define CTR_IMINLINE_SHIFT U(0) 419 #define CTR_IMINLINE_MASK U(0xf) 420 421 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 422 423 /* Physical timer control register bit fields shifts and masks */ 424 #define CNTP_CTL_ENABLE_SHIFT U(0) 425 #define CNTP_CTL_IMASK_SHIFT U(1) 426 #define CNTP_CTL_ISTATUS_SHIFT U(2) 427 428 #define CNTP_CTL_ENABLE_MASK U(1) 429 #define CNTP_CTL_IMASK_MASK U(1) 430 #define CNTP_CTL_ISTATUS_MASK U(1) 431 432 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 433 CNTP_CTL_ENABLE_MASK) 434 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 435 CNTP_CTL_IMASK_MASK) 436 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 437 CNTP_CTL_ISTATUS_MASK) 438 439 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 440 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 441 442 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 443 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 444 445 /* Exception Syndrome register bits and bobs */ 446 #define ESR_EC_SHIFT U(26) 447 #define ESR_EC_MASK U(0x3f) 448 #define ESR_EC_LENGTH U(6) 449 #define EC_UNKNOWN U(0x0) 450 #define EC_WFE_WFI U(0x1) 451 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 452 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 453 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 454 #define EC_AARCH32_CP14_LDC_STC U(0x6) 455 #define EC_FP_SIMD U(0x7) 456 #define EC_AARCH32_CP10_MRC U(0x8) 457 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 458 #define EC_ILLEGAL U(0xe) 459 #define EC_AARCH32_SVC U(0x11) 460 #define EC_AARCH32_HVC U(0x12) 461 #define EC_AARCH32_SMC U(0x13) 462 #define EC_AARCH64_SVC U(0x15) 463 #define EC_AARCH64_HVC U(0x16) 464 #define EC_AARCH64_SMC U(0x17) 465 #define EC_AARCH64_SYS U(0x18) 466 #define EC_IABORT_LOWER_EL U(0x20) 467 #define EC_IABORT_CUR_EL U(0x21) 468 #define EC_PC_ALIGN U(0x22) 469 #define EC_DABORT_LOWER_EL U(0x24) 470 #define EC_DABORT_CUR_EL U(0x25) 471 #define EC_SP_ALIGN U(0x26) 472 #define EC_AARCH32_FP U(0x28) 473 #define EC_AARCH64_FP U(0x2c) 474 #define EC_SERROR U(0x2f) 475 476 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 477 478 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 479 #define RMR_RESET_REQUEST_SHIFT U(0x1) 480 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 481 482 /******************************************************************************* 483 * Definitions of register offsets, fields and macros for CPU system 484 * instructions. 485 ******************************************************************************/ 486 487 #define TLBI_ADDR_SHIFT U(12) 488 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 489 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 490 491 /******************************************************************************* 492 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 493 * system level implementation of the Generic Timer. 494 ******************************************************************************/ 495 #define CNTNSAR U(0x4) 496 #define CNTNSAR_NS_SHIFT(x) (x) 497 498 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 499 #define CNTACR_RPCT_SHIFT U(0x0) 500 #define CNTACR_RVCT_SHIFT U(0x1) 501 #define CNTACR_RFRQ_SHIFT U(0x2) 502 #define CNTACR_RVOFF_SHIFT U(0x3) 503 #define CNTACR_RWVT_SHIFT U(0x4) 504 #define CNTACR_RWPT_SHIFT U(0x5) 505 506 /* PMCR_EL0 definitions */ 507 #define PMCR_EL0_RESET_VAL U(0x0) 508 #define PMCR_EL0_N_SHIFT U(11) 509 #define PMCR_EL0_N_MASK U(0x1f) 510 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 511 #define PMCR_EL0_LC_BIT (U(1) << 6) 512 #define PMCR_EL0_DP_BIT (U(1) << 5) 513 #define PMCR_EL0_X_BIT (U(1) << 4) 514 #define PMCR_EL0_D_BIT (U(1) << 3) 515 516 /******************************************************************************* 517 * Definitions of MAIR encodings for device and normal memory 518 ******************************************************************************/ 519 /* 520 * MAIR encodings for device memory attributes. 521 */ 522 #define MAIR_DEV_nGnRnE ULL(0x0) 523 #define MAIR_DEV_nGnRE ULL(0x4) 524 #define MAIR_DEV_nGRE ULL(0x8) 525 #define MAIR_DEV_GRE ULL(0xc) 526 527 /* 528 * MAIR encodings for normal memory attributes. 529 * 530 * Cache Policy 531 * WT: Write Through 532 * WB: Write Back 533 * NC: Non-Cacheable 534 * 535 * Transient Hint 536 * NTR: Non-Transient 537 * TR: Transient 538 * 539 * Allocation Policy 540 * RA: Read Allocate 541 * WA: Write Allocate 542 * RWA: Read and Write Allocate 543 * NA: No Allocation 544 */ 545 #define MAIR_NORM_WT_TR_WA ULL(0x1) 546 #define MAIR_NORM_WT_TR_RA ULL(0x2) 547 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 548 #define MAIR_NORM_NC ULL(0x4) 549 #define MAIR_NORM_WB_TR_WA ULL(0x5) 550 #define MAIR_NORM_WB_TR_RA ULL(0x6) 551 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 552 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 553 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 554 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 555 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 556 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 557 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 558 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 559 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 560 561 #define MAIR_NORM_OUTER_SHIFT 4 562 563 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 564 565 #endif /* __ARCH_H__ */ 566
