/external/llvm/lib/IR/ |
ProfileSummary.cpp | 132 ConstantAsMetadata *Op1 = 137 if (!Op0 || !Op1 || !Op2) 140 cast<ConstantInt>(Op1->getValue())->getZExtValue(),
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/external/llvm/lib/CodeGen/GlobalISel/ |
IRTranslator.cpp | 70 unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1)); 72 MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1);
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/external/llvm/lib/Target/BPF/MCTargetDesc/ |
BPFMCCodeEmitter.cpp | 158 const MCOperand Op1 = MI.getOperand(1); 159 assert(Op1.isReg() && "First operand is not register."); 160 Encoding = MRI.getEncodingValue(Op1.getReg());
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/external/llvm/lib/Target/Lanai/ |
LanaiISelDAGToDAG.cpp | 254 SDValue Op0, Op1, AluOp; 259 if (!selectAddrRr(Op, Op0, Op1, AluOp) && 260 !selectAddrRi(Op, Op0, Op1, AluOp)) 266 OutOps.push_back(Op1);
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LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { 171 if (Op1.getType() != Op2.getType()) 174 switch (Op1.getType()) { 176 return Op1.getReg() == Op2.getReg(); 178 return Op1.getImm() == Op2.getImm(); 294 MachineOperand &Op1 = AluIter->getOperand(1); 299 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1))
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/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyPeephole.cpp | 143 MachineOperand &Op1 = MI.getOperand(1); 144 if (Op1.isSymbol()) { 145 StringRef Name(Op1.getSymbolName());
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WebAssemblyStoreResults.cpp | 157 MachineOperand &Op1 = MI.getOperand(1); 158 if (!Op1.isSymbol()) 161 StringRef Name(Op1.getSymbolName());
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 193 SDValue Op0, Op1; 197 if (!SelectADDRrr(Op, Op0, Op1)) 198 SelectADDRri(Op, Op0, Op1); 203 OutOps.push_back(Op1);
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/external/llvm/lib/ExecutionEngine/Interpreter/ |
Execution.cpp | [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.cpp | 85 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 96 Ops[2].getAsInteger(10, Op1); 100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 108 uint32_t Op1 = (Bits >> 11) & 0x7; 113 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
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/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 285 MachineOperand Op1 = MI.getOperand(S1); 288 ChangeOpInto(MI.getOperand(S2), Op1);
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/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
LanaiMCCodeEmitter.cpp | 192 const MCOperand Op1 = Inst.getOperand(OpNo + 0); 196 assert(Op1.isReg() && "First operand is not register."); 202 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18); 224 const MCOperand Op1 = Inst.getOperand(OpNo + 0); 228 assert(Op1.isReg() && "First operand is not register."); 229 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15); 263 const MCOperand Op1 = Inst.getOperand(OpNo + 0); 267 assert(Op1.isReg() && "First operand is not register."); 273 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12);
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
PTXISelLowering.cpp | 150 SDValue Op1 = Op.getOperand(1); 158 if (Op1.getOpcode() == ISD::Constant && 159 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 160 cast<ConstantSDNode>(Op1)->isNullValue()) && 163 return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1); 166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
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/external/capstone/arch/AArch64/ |
AArch64BaseInfo.c | 633 uint32_t Op0, Op1, CRn, CRm, Op2; 669 Op1 = (Bits >> 11) & 0x7; 685 Op1S = utostr(Op1, false); [all...] |
/external/capstone/arch/XCore/ |
XCoreDisassembler.c | 192 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) 209 *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2); 216 unsigned *Op1, unsigned *Op2, unsigned *Op3) 226 *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2); 309 unsigned Op1, Op2; 310 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); 314 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 323 unsigned Op1, Op2; 324 DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); 328 MCOperand_CreateImm0(Inst, Op1); [all...] |
/external/llvm/lib/DebugInfo/DWARF/ |
DWARFDebugFrame.cpp | 113 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK; 118 addInstruction(Primary, Op1); 121 addInstruction(Primary, Op1, Data.getULEB128(Offset)); 171 auto op1 = Data.getULEB128(Offset); local 173 addInstruction(Opcode, op1, op2); 181 auto op1 = Data.getULEB128(Offset); local 183 addInstruction(Opcode, op1, op2);
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/external/llvm/lib/Target/MSP430/ |
MSP430ISelDAGToDAG.cpp | 285 SDValue Op0, Op1; 289 if (!SelectAddr(Op, Op0, Op1)) 295 OutOps.push_back(Op1);
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/external/llvm/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 391 SDValue Op0, Op1; 397 if (!SelectADDRrr(Op, Op0, Op1)) 398 SelectADDRri(Op, Op0, Op1); 403 OutOps.push_back(Op1);
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/external/llvm/lib/Target/SystemZ/ |
SystemZTDC.cpp | 288 Value *Op0, *Op1; 292 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))]; 293 if (Op0 != Op1)
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/external/llvm/lib/Target/X86/ |
X86OptimizeLEAs.cpp | 367 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); 370 assert(isSimilarDispOp(Op1, Op2) && 376 if (Op1.isJTI()) 378 return Op1.isImm() ? Op1.getImm() - Op2.getImm() 379 : Op1.getOffset() - Op2.getOffset();
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/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 347 unsigned Op1, Op2; 348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 360 unsigned Op1, Op2; 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 365 Inst.addOperand(MCOperand::createImm(Op1)); [all...] |
/external/llvm/lib/Transforms/Scalar/ |
CorrelatedValuePropagation.cpp | 185 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1)); 186 if (!Op1) return false; 198 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, C); 394 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1)); 395 if (!Op1) return nullptr; 398 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, At);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 272 SDValue Op1 = Op.getOperand(1); 287 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); 294 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); 296 return DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
MSP430ISelDAGToDAG.cpp | 288 SDValue Op0, Op1; 292 if (!SelectAddr(Op, Op0, Op1)) 298 OutOps.push_back(Op1);
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
MipsISelDAGToDAG.cpp | 245 SDValue Op1 = Node->getOperand(0); 251 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
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