| /external/icu/icu4c/source/test/intltest/ |
| tscoll.h | 28 struct Order
30 int32_t order; member in struct:IntlTestCollator::Order
53 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
43 // The remaining allocation order may depend on the hint.
44 ArrayRef<unsigned> Order =
47 if (Order.empty())
50 // Copy the allocation order with reserved registers removed.
52 unsigned *P = new unsigned[Order.size()];
54 for (unsigned i = 0; i != Order.size(); ++i)
55 if (!RCI.isReserved(Order[i])
[all...] |
| RegisterClassInfo.h | 32 OwningArrayPtr<unsigned> Order;
36 return makeArrayRef(Order.get(), NumRegs);
84 /// getOrder - Returns the preferred allocation order for RC. The order
122 /// Allocatable registers may show up in the allocation order of some virtual
|
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
31 ArrayRef<MCPhysReg> Order;
44 /// Get the allocation order without reordered hints.
45 ArrayRef<MCPhysReg> getOrder() const { return Order; }
47 /// Return the next physical register in the allocation order, or 0.
54 Limit = Order.size();
56 unsigned Reg = Order[Pos++];
64 /// Limit'th register in the RegisterClassInfo allocation order
[all...] |
| /external/lzma/CPP/7zip/Compress/ |
| PpmdEncoder.h | 21 int Order;
27 Order = -1;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| TargetRegisterInfo.cpp | 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
77 for (unsigned i = 0; i != Order.size(); ++i)
78 R.set(Order[i]);
|
| /prebuilts/go/darwin-x86/src/compress/lzw/ |
| reader.go | 19 // modulo LSB/MSB packing order.
28 // Order specifies the bit ordering in an LZW data stream.
29 type Order int
33 LSB Order = iota
239 func NewReader(r io.Reader, order Order, litWidth int) io.ReadCloser {
241 switch order {
247 d.err = errors.New("lzw: unknown order")
|
| /prebuilts/go/linux-x86/src/compress/lzw/ |
| reader.go | 19 // modulo LSB/MSB packing order.
28 // Order specifies the bit ordering in an LZW data stream.
29 type Order int
33 LSB Order = iota
239 func NewReader(r io.Reader, order Order, litWidth int) io.ReadCloser {
241 switch order {
247 d.err = errors.New("lzw: unknown order")
|
| /external/aac/libAACdec/src/ |
| aacdec_tns.h | 115 encoders also do order 20 for AAC-LC :( 15 for USAC (AOT 42)
120 #error USAC: TNS filter order up 15 can be signaled!
132 UCHAR Order;
|
| /external/webrtc/webrtc/base/ |
| bytebuffer.h | 26 ORDER_NETWORK = 0, // Default, use network byte order (big endian).
27 ORDER_HOST, // Use the native order of the host.
30 // |byte_order| defines order of bytes in the buffer.
46 ByteOrder Order() const { return byte_order_; }
|
| /build/blueprint/proptools/ |
| extend.go | 107 // The order function is called on each non-filtered property to determine if it should be appended
119 order ExtendPropertyOrderFunc) error {
120 return extendProperties(dst, src, filter, order)
132 // The order function is called on each non-filtered property to determine if it should be appended
144 filter ExtendPropertyFilterFunc, order ExtendPropertyOrderFunc) error {
145 return extendMatchingProperties(dst, src, filter, order)
148 type Order int
151 Append Order = iota
161 dstValue, srcValue interface{}) (Order, error)
165 dstValue, srcValue interface{}) (Order, error)
[all...] |
| /external/gemmlowp/test/ |
| test.h | 52 static const MapOrder Order = tOrder;
|
| /prebuilts/go/darwin-x86/src/vendor/golang_org/x/text/unicode/bidi/ |
| bidi.go | 116 // Order computes the visual ordering of all the runs in a Paragraph.
117 func (p *Paragraph) Order() (Ordering, error) {
127 // An Ordering holds the computed visual order of runs of a Paragraph. Calling
150 // // Reorder creates a reader that reads the runes in visual order per character.
160 // String returns the text of the run in its original order.
165 // Bytes returns the text of the run in its original order.
171 // - Display order
186 // AppendReverse reverses the order of characters of in, appends them to out,
193 // ReverseString reverses the order of characters in s and returns a new string.
|
| /prebuilts/go/linux-x86/src/vendor/golang_org/x/text/unicode/bidi/ |
| bidi.go | 116 // Order computes the visual ordering of all the runs in a Paragraph.
117 func (p *Paragraph) Order() (Ordering, error) {
127 // An Ordering holds the computed visual order of runs of a Paragraph. Calling
150 // // Reorder creates a reader that reads the runes in visual order per character.
160 // String returns the text of the run in its original order.
165 // Bytes returns the text of the run in its original order.
171 // - Display order
186 // AppendReverse reverses the order of characters of in, appends them to out,
193 // ReverseString reverses the order of characters in s and returns a new string.
|
| /device/linaro/bootloader/edk2/SecurityPkg/UserIdentification/UserProfileManagerDxe/ |
| ModifyAccessPolicy.c | 78 // Save access of boot order.
316 CHAR16 *Order;
343 Order = AllocateZeroPool (OrderSize);
344 if (Order == NULL) {
353 Order
398 UnicodeSPrint (VarName, sizeof (VarName), L"Driver%04x", Order[Index]);
431 KEY_MODIFY_USER | KEY_MODIFY_AP_DP | KEY_LOAD_PERMIT_MODIFY | Order[Index],
456 FreePool (Order);
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 33 std::unique_ptr<MCPhysReg[]> Order;
40 return makeArrayRef(Order.get(), NumRegs);
90 /// getOrder - Returns the preferred allocation order for RC. The order
116 /// Get the minimum register cost in RC's allocation order.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
59 : Var(Var), Expr(Expr), Offset(off), DL(std::move(dl)), Order(O),
69 : Var(Var), Expr(Expr), Offset(off), DL(std::move(dl)), Order(O),
78 : Var(Var), Expr(Expr), Offset(off), DL(std::move(dl)), Order(O),
114 // Returns the SDNodeOrder. This is the order of the preceding node in the
116 unsigned getOrder() const { return Order; }
|
| /external/lzma/CS/7zip/ |
| ICoder.cs | 93 /// Specifies order for PPM methods.
95 Order,
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
|
| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 38 private enum Order {
47 private final List<Order> mHistory = new ArrayList<Order>();
48 private final List<Order> mExpectedOrder = new ArrayList<Order>();
50 public MockVCardInterpreter addExpectedOrder(Order order) {
51 mExpectedOrder.add(order);
55 private void inspectOrder(Order order) {
[all...] |
| /packages/apps/DeskClock/src/com/android/deskclock/data/ |
| Weekdays.java | 52 public enum Order {
59 Order(Integer... calendarDays) {
276 * @param order the order in which to present the weekdays
277 * @return the enabled weekdays in the given {@code order}
279 public String toString(Context context, Order order) {
280 return toString(context, order, false /* forceLongNames */);
285 * @param order the order in which to present the weekday
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 38 std::unique_ptr<MCPhysReg[]> Order;
43 return makeArrayRef(Order.get(), NumRegs);
94 /// getOrder - Returns the preferred allocation order for RC. The order
120 /// Get the minimum register cost in RC's allocation order.
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 38 std::unique_ptr<MCPhysReg[]> Order;
43 return makeArrayRef(Order.get(), NumRegs);
94 /// getOrder - Returns the preferred allocation order for RC. The order
120 /// Get the minimum register cost in RC's allocation order.
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 38 std::unique_ptr<MCPhysReg[]> Order;
43 return makeArrayRef(Order.get(), NumRegs);
94 /// getOrder - Returns the preferred allocation order for RC. The order
120 /// Get the minimum register cost in RC's allocation order.
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 38 std::unique_ptr<MCPhysReg[]> Order;
43 return makeArrayRef(Order.get(), NumRegs);
94 /// getOrder - Returns the preferred allocation order for RC. The order
120 /// Get the minimum register cost in RC's allocation order.
|
