1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SOC_H__ 8 #define __SOC_H__ 9 10 #include <utils.h> 11 12 #define GLB_SRST_FST_CFG_VAL 0xfdb9 13 #define GLB_SRST_SND_CFG_VAL 0xeca8 14 15 #define PMUCRU_PPLL_CON(n) ((n) * 4) 16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 17 #define PLL_MODE_MSK 0x03 18 #define PLL_MODE_SHIFT 0x08 19 #define PLL_BYPASS_MSK 0x01 20 #define PLL_BYPASS_SHIFT 0x01 21 #define PLL_PWRDN_MSK 0x01 22 #define PLL_PWRDN_SHIFT 0x0 23 #define PLL_BYPASS BIT(1) 24 #define PLL_PWRDN BIT(0) 25 26 #define NO_PLL_BYPASS (0x00) 27 #define NO_PLL_PWRDN (0x00) 28 29 #define FBDIV(n) ((0xfff << 16) | n) 30 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) 31 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) 32 #define REFDIV(n) ((0x3F << 16) | n) 33 #define PLL_LOCK(n) ((n >> 31) & 0x1) 34 35 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 36 PLL_MODE_MSK, PLL_MODE_SHIFT) 37 38 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 39 PLL_MODE_MSK, PLL_MODE_SHIFT) 40 41 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) 42 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) 43 44 #define PLL_CON_COUNT 0x06 45 #define CRU_CLKSEL_COUNT 108 46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) 47 48 #define PMUCRU_CLKSEL_CONUT 0x06 49 #define PMUCRU_CLKSEL_OFFSET 0x080 50 #define REG_SIZE 0x04 51 #define REG_SOC_WMSK 0xffff0000 52 #define CLK_GATE_MASK 0x01 53 54 #define PMUCRU_GATE_COUNT 0x03 55 #define CRU_GATE_COUNT 0x23 56 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) 57 #define CRU_GATE_CON(n) (0x300 + (n) * 4) 58 59 #define PMUCRU_RSTNHOLD_CON0 0x120 60 enum { 61 PRESETN_NOC_PMU_HOLD = 1, 62 PRESETN_INTMEM_PMU_HOLD, 63 HRESETN_CM0S_PMU_HOLD, 64 HRESETN_CM0S_NOC_PMU_HOLD, 65 DRESETN_CM0S_PMU_HOLD, 66 POESETN_CM0S_PMU_HOLD, 67 PRESETN_SPI3_HOLD, 68 RESETN_SPI3_HOLD, 69 PRESETN_TIMER_PMU_0_1_HOLD, 70 RESETN_TIMER_PMU_0_HOLD, 71 RESETN_TIMER_PMU_1_HOLD, 72 PRESETN_UART_M0_PMU_HOLD, 73 RESETN_UART_M0_PMU_HOLD, 74 PRESETN_WDT_PMU_HOLD 75 }; 76 77 #define PMUCRU_RSTNHOLD_CON1 0x124 78 enum { 79 PRESETN_I2C0_HOLD, 80 PRESETN_I2C4_HOLD, 81 PRESETN_I2C8_HOLD, 82 PRESETN_MAILBOX_PMU_HOLD, 83 PRESETN_RKPWM_PMU_HOLD, 84 PRESETN_PMUGRF_HOLD, 85 PRESETN_SGRF_HOLD, 86 PRESETN_GPIO0_HOLD, 87 PRESETN_GPIO1_HOLD, 88 PRESETN_CRU_PMU_HOLD, 89 PRESETN_INTR_ARB_HOLD, 90 PRESETN_PVTM_PMU_HOLD, 91 RESETN_I2C0_HOLD, 92 RESETN_I2C4_HOLD, 93 RESETN_I2C8_HOLD 94 }; 95 96 enum plls_id { 97 ALPLL_ID = 0, 98 ABPLL_ID, 99 DPLL_ID, 100 CPLL_ID, 101 GPLL_ID, 102 NPLL_ID, 103 VPLL_ID, 104 PPLL_ID, 105 END_PLL_ID, 106 }; 107 108 #define CLST_L_CPUS_MSK (0xf) 109 #define CLST_B_CPUS_MSK (0x3) 110 111 enum pll_work_mode { 112 SLOW_MODE = 0x00, 113 NORMAL_MODE = 0x01, 114 DEEP_SLOW_MODE = 0x02, 115 }; 116 117 enum glb_sft_reset { 118 PMU_RST_BY_FIRST_SFT, 119 PMU_RST_BY_SECOND_SFT = BIT(2), 120 PMU_RST_NOT_BY_SFT = BIT(3), 121 }; 122 123 struct pll_div { 124 uint32_t mhz; 125 uint32_t refdiv; 126 uint32_t fbdiv; 127 uint32_t postdiv1; 128 uint32_t postdiv2; 129 uint32_t frac; 130 uint32_t freq; 131 }; 132 133 struct deepsleep_data_s { 134 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 135 uint32_t cru_gate_con[CRU_GATE_COUNT]; 136 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; 137 uint32_t pmucru_rstnhold_con0; 138 uint32_t pmucru_rstnhold_con1; 139 }; 140 141 /************************************************** 142 * pmugrf reg, offset 143 **************************************************/ 144 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) 145 146 /************************************************** 147 * DCF reg, offset 148 **************************************************/ 149 #define DCF_DCF_CTRL 0x0 150 #define DCF_DCF_ADDR 0x8 151 #define DCF_DCF_ISR 0xc 152 #define DCF_DCF_TOSET 0x14 153 #define DCF_DCF_TOCMD 0x18 154 #define DCF_DCF_CMD_CFG 0x1c 155 156 /* DCF_DCF_ISR */ 157 #define DCF_TIMEOUT (1 << 2) 158 #define DCF_ERR (1 << 1) 159 #define DCF_DONE (1 << 0) 160 161 /* DCF_DCF_CTRL */ 162 #define DCF_VOP_HW_EN (1 << 2) 163 #define DCF_STOP (1 << 1) 164 #define DCF_START (1 << 0) 165 166 #define CYCL_24M_CNT_US(us) (24 * us) 167 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 168 #define CYCL_32K_CNT_MS(ms) (ms * 32) 169 170 /************************************************** 171 * cru reg, offset 172 **************************************************/ 173 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 174 175 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 176 /* reset release*/ 177 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 178 179 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 180 /* reset release*/ 181 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 182 183 #define CRU_GLB_RST_CON 0x0510 184 #define CRU_GLB_SRST_FST 0x0500 185 #define CRU_GLB_SRST_SND 0x0504 186 187 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 188 #define PCLK_GPIO2_GATE_SHIFT 3 189 #define PCLK_GPIO3_GATE_SHIFT 4 190 #define PCLK_GPIO4_GATE_SHIFT 5 191 192 /************************************************** 193 * pmu cru reg, offset 194 **************************************************/ 195 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 196 /* reset hold*/ 197 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 198 /* reset hold release*/ 199 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 200 201 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 202 #define CRU_PMU_WDTRST_EN 0x0 203 204 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 205 #define CRU_PMU_FIRST_SFTRST_EN 0x0 206 207 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 208 #define PCLK_GPIO0_GATE_SHIFT 3 209 #define PCLK_GPIO1_GATE_SHIFT 4 210 211 #define CPU_BOOT_ADDR_WMASK 0xffff0000 212 #define CPU_BOOT_ADDR_ALIGN 16 213 214 #define GRF_IOMUX_2BIT_MASK 0x3 215 #define GRF_IOMUX_GPIO 0x0 216 217 #define GRF_GPIO4C2_IOMUX_SHIFT 4 218 #define GRF_GPIO4C2_IOMUX_PWM 0x1 219 #define GRF_GPIO4C6_IOMUX_SHIFT 12 220 #define GRF_GPIO4C6_IOMUX_PWM 0x1 221 222 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) 223 #define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) 224 #define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) 225 #define PWM_CTRL(n) (0x000c + 0x10 * (n)) 226 227 #define PWM_DISABLE (0 << 0) 228 #define PWM_ENABLE (1 << 0) 229 230 /* grf reg offset */ 231 #define GRF_USBPHY0_CTRL0 0x4480 232 #define GRF_USBPHY0_CTRL2 0x4488 233 #define GRF_USBPHY0_CTRL3 0x448c 234 #define GRF_USBPHY0_CTRL12 0x44b0 235 #define GRF_USBPHY0_CTRL13 0x44b4 236 #define GRF_USBPHY0_CTRL15 0x44bc 237 #define GRF_USBPHY0_CTRL16 0x44c0 238 239 #define GRF_USBPHY1_CTRL0 0x4500 240 #define GRF_USBPHY1_CTRL2 0x4508 241 #define GRF_USBPHY1_CTRL3 0x450c 242 #define GRF_USBPHY1_CTRL12 0x4530 243 #define GRF_USBPHY1_CTRL13 0x4534 244 #define GRF_USBPHY1_CTRL15 0x453c 245 #define GRF_USBPHY1_CTRL16 0x4540 246 247 #define GRF_GPIO2A_IOMUX 0xe000 248 #define GRF_GPIO2D_HE 0xe18c 249 #define GRF_DDRC0_CON0 0xe380 250 #define GRF_DDRC0_CON1 0xe384 251 #define GRF_DDRC1_CON0 0xe388 252 #define GRF_DDRC1_CON1 0xe38c 253 #define GRF_SOC_CON_BASE 0xe200 254 #define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4) 255 #define GRF_IO_VSEL 0xe640 256 257 #define CRU_CLKSEL_CON0 0x0100 258 #define CRU_CLKSEL_CON6 0x0118 259 #define CRU_SDIO0_CON1 0x058c 260 #define PMUCRU_CLKSEL_CON0 0x0080 261 #define PMUCRU_CLKGATE_CON2 0x0108 262 #define PMUCRU_SOFTRST_CON0 0x0110 263 #define PMUCRU_GATEDIS_CON0 0x0130 264 #define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4) 265 266 /* 267 * When system reset in running state, we want the cpus to be reboot 268 * from maskrom (system reboot), 269 * the pmusgrf reset-hold bits needs to be released. 270 * When system wake up from system deep suspend, some soc will be reset 271 * when waked up, 272 * we want the bootcpu to be reboot from pmusram, 273 * the pmusgrf reset-hold bits needs to be held. 274 */ 275 static inline void pmu_sgrf_rst_hld_release(void) 276 { 277 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 278 CRU_PMU_SGRF_RST_RLS); 279 } 280 281 static inline void pmu_sgrf_rst_hld(void) 282 { 283 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 284 CRU_PMU_SGRF_RST_HOLD); 285 } 286 287 /* export related and operating SoC APIs */ 288 void __dead2 soc_global_soft_reset(void); 289 void disable_dvfs_plls(void); 290 void disable_nodvfs_plls(void); 291 void enable_dvfs_plls(void); 292 void enable_nodvfs_plls(void); 293 void prepare_abpll_for_ddrctrl(void); 294 void restore_abpll(void); 295 void clk_gate_con_save(void); 296 void clk_gate_con_disable(void); 297 void clk_gate_con_restore(void); 298 void set_pmu_rsthold(void); 299 void restore_pmu_rsthold(void); 300 #endif /* __SOC_H__ */ 301
