1 /* ppc.h -- Header file for PowerPC opcode table 2 Copyright (C) 1994-2016 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 3, 10 or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING3. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #ifndef PPC_H 23 #define PPC_H 24 25 #include "bfd_stdint.h" 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 typedef uint64_t ppc_cpu_t; 32 33 /* The opcode table is an array of struct powerpc_opcode. */ 34 35 struct powerpc_opcode 36 { 37 /* The opcode name. */ 38 const char *name; 39 40 /* The opcode itself. Those bits which will be filled in with 41 operands are zeroes. */ 42 unsigned long opcode; 43 44 /* The opcode mask. This is used by the disassembler. This is a 45 mask containing ones indicating those bits which must match the 46 opcode field, and zeroes indicating those bits which need not 47 match (and are presumably filled in by operands). */ 48 unsigned long mask; 49 50 /* One bit flags for the opcode. These are used to indicate which 51 specific processors support the instructions. The defined values 52 are listed below. */ 53 ppc_cpu_t flags; 54 55 /* One bit flags for the opcode. These are used to indicate which 56 specific processors no longer support the instructions. The defined 57 values are listed below. */ 58 ppc_cpu_t deprecated; 59 60 /* An array of operand codes. Each code is an index into the 61 operand table. They appear in the order which the operands must 62 appear in assembly code, and are terminated by a zero. */ 63 unsigned char operands[8]; 64 }; 65 66 /* The table itself is sorted by major opcode number, and is otherwise 67 in the order in which the disassembler should consider 68 instructions. */ 69 extern const struct powerpc_opcode powerpc_opcodes[]; 70 extern const int powerpc_num_opcodes; 71 extern const struct powerpc_opcode vle_opcodes[]; 72 extern const int vle_num_opcodes; 73 74 /* Values defined for the flags field of a struct powerpc_opcode. */ 75 76 /* Opcode is defined for the PowerPC architecture. */ 77 #define PPC_OPCODE_PPC 1 78 79 /* Opcode is defined for the POWER (RS/6000) architecture. */ 80 #define PPC_OPCODE_POWER 2 81 82 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ 83 #define PPC_OPCODE_POWER2 4 84 85 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 86 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 87 but it also supports many additional POWER instructions. */ 88 #define PPC_OPCODE_601 8 89 90 /* Opcode is supported in both the Power and PowerPC architectures 91 (ie, compiler's -mcpu=common or assembler's -mcom). More than just 92 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER 93 and PPC_OPCODE_POWER2 because many instructions changed mnemonics 94 between POWER and POWERPC. */ 95 #define PPC_OPCODE_COMMON 0x10 96 97 /* Opcode is supported for any Power or PowerPC platform (this is 98 for the assembler's -many option, and it eliminates duplicates). */ 99 #define PPC_OPCODE_ANY 0x20 100 101 /* Opcode is only defined on 64 bit architectures. */ 102 #define PPC_OPCODE_64 0x40 103 104 /* Opcode is supported as part of the 64-bit bridge. */ 105 #define PPC_OPCODE_64_BRIDGE 0x80 106 107 /* Opcode is supported by Altivec Vector Unit */ 108 #define PPC_OPCODE_ALTIVEC 0x100 109 110 /* Opcode is supported by PowerPC 403 processor. */ 111 #define PPC_OPCODE_403 0x200 112 113 /* Opcode is supported by PowerPC BookE processor. */ 114 #define PPC_OPCODE_BOOKE 0x400 115 116 /* Opcode is supported by PowerPC 440 processor. */ 117 #define PPC_OPCODE_440 0x800 118 119 /* Opcode is only supported by Power4 architecture. */ 120 #define PPC_OPCODE_POWER4 0x1000 121 122 /* Opcode is only supported by Power7 architecture. */ 123 #define PPC_OPCODE_POWER7 0x2000 124 125 /* Opcode is only supported by e500x2 Core. */ 126 #define PPC_OPCODE_SPE 0x4000 127 128 /* Opcode is supported by e500x2 Integer select APU. */ 129 #define PPC_OPCODE_ISEL 0x8000 130 131 /* Opcode is an e500 SPE floating point instruction. */ 132 #define PPC_OPCODE_EFS 0x10000 133 134 /* Opcode is supported by branch locking APU. */ 135 #define PPC_OPCODE_BRLOCK 0x20000 136 137 /* Opcode is supported by performance monitor APU. */ 138 #define PPC_OPCODE_PMR 0x40000 139 140 /* Opcode is supported by cache locking APU. */ 141 #define PPC_OPCODE_CACHELCK 0x80000 142 143 /* Opcode is supported by machine check APU. */ 144 #define PPC_OPCODE_RFMCI 0x100000 145 146 /* Opcode is only supported by Power5 architecture. */ 147 #define PPC_OPCODE_POWER5 0x200000 148 149 /* Opcode is supported by PowerPC e300 family. */ 150 #define PPC_OPCODE_E300 0x400000 151 152 /* Opcode is only supported by Power6 architecture. */ 153 #define PPC_OPCODE_POWER6 0x800000 154 155 /* Opcode is only supported by PowerPC Cell family. */ 156 #define PPC_OPCODE_CELL 0x1000000 157 158 /* Opcode is supported by CPUs with paired singles support. */ 159 #define PPC_OPCODE_PPCPS 0x2000000 160 161 /* Opcode is supported by Power E500MC */ 162 #define PPC_OPCODE_E500MC 0x4000000 163 164 /* Opcode is supported by PowerPC 405 processor. */ 165 #define PPC_OPCODE_405 0x8000000 166 167 /* Opcode is supported by Vector-Scalar (VSX) Unit */ 168 #define PPC_OPCODE_VSX 0x10000000 169 170 /* Opcode is supported by A2. */ 171 #define PPC_OPCODE_A2 0x20000000 172 173 /* Opcode is supported by PowerPC 476 processor. */ 174 #define PPC_OPCODE_476 0x40000000 175 176 /* Opcode is supported by AppliedMicro Titan core */ 177 #define PPC_OPCODE_TITAN 0x80000000 178 179 /* Opcode which is supported by the e500 family */ 180 #define PPC_OPCODE_E500 0x100000000ull 181 182 /* Opcode is supported by Extended Altivec Vector Unit */ 183 #define PPC_OPCODE_ALTIVEC2 0x200000000ull 184 185 /* Opcode is supported by Power E6500 */ 186 #define PPC_OPCODE_E6500 0x400000000ull 187 188 /* Opcode is supported by Thread management APU */ 189 #define PPC_OPCODE_TMR 0x800000000ull 190 191 /* Opcode which is supported by the VLE extension. */ 192 #define PPC_OPCODE_VLE 0x1000000000ull 193 194 /* Opcode is only supported by Power8 architecture. */ 195 #define PPC_OPCODE_POWER8 0x2000000000ull 196 197 /* Opcode which is supported by the Hardware Transactional Memory extension. */ 198 /* Currently, this is the same as the POWER8 mask. If another cpu comes out 199 that isn't a superset of POWER8, we can define this to its own mask. */ 200 #define PPC_OPCODE_HTM PPC_OPCODE_POWER8 201 202 /* Opcode is supported by ppc750cl. */ 203 #define PPC_OPCODE_750 0x4000000000ull 204 205 /* Opcode is supported by ppc7450. */ 206 #define PPC_OPCODE_7450 0x8000000000ull 207 208 /* Opcode is supported by ppc821/850/860. */ 209 #define PPC_OPCODE_860 0x10000000000ull 210 211 /* Opcode is only supported by Power9 architecture. */ 212 #define PPC_OPCODE_POWER9 0x20000000000ull 213 214 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */ 215 #define PPC_OPCODE_VSX3 0x40000000000ull 216 217 /* A macro to extract the major opcode from an instruction. */ 218 #define PPC_OP(i) (((i) >> 26) & 0x3f) 219 220 /* A macro to determine if the instruction is a 2-byte VLE insn. */ 221 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) 222 223 /* A macro to extract the major opcode from a VLE instruction. */ 224 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) 225 226 /* A macro to convert a VLE opcode to a VLE opcode segment. */ 227 #define VLE_OP_TO_SEG(i) ((i) >> 1) 228 229 /* The operands table is an array of struct powerpc_operand. */ 231 232 struct powerpc_operand 233 { 234 /* A bitmask of bits in the operand. */ 235 unsigned int bitm; 236 237 /* The shift operation to be applied to the operand. No shift 238 is made if this is zero. For positive values, the operand 239 is shifted left by SHIFT. For negative values, the operand 240 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate 241 that BITM and SHIFT cannot be used to determine where the 242 operand goes in the insn. */ 243 int shift; 244 245 /* Insertion function. This is used by the assembler. To insert an 246 operand value into an instruction, check this field. 247 248 If it is NULL, execute 249 if (o->shift >= 0) 250 i |= (op & o->bitm) << o->shift; 251 else 252 i |= (op & o->bitm) >> -o->shift; 253 (i is the instruction which we are filling in, o is a pointer to 254 this structure, and op is the operand value). 255 256 If this field is not NULL, then simply call it with the 257 instruction and the operand value. It will return the new value 258 of the instruction. If the ERRMSG argument is not NULL, then if 259 the operand value is illegal, *ERRMSG will be set to a warning 260 string (the operand will be inserted in any case). If the 261 operand value is legal, *ERRMSG will be unchanged (most operands 262 can accept any value). */ 263 unsigned long (*insert) 264 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); 265 266 /* Extraction function. This is used by the disassembler. To 267 extract this operand type from an instruction, check this field. 268 269 If it is NULL, compute 270 if (o->shift >= 0) 271 op = (i >> o->shift) & o->bitm; 272 else 273 op = (i << -o->shift) & o->bitm; 274 if ((o->flags & PPC_OPERAND_SIGNED) != 0) 275 sign_extend (op); 276 (i is the instruction, o is a pointer to this structure, and op 277 is the result). 278 279 If this field is not NULL, then simply call it with the 280 instruction value. It will return the value of the operand. If 281 the INVALID argument is not NULL, *INVALID will be set to 282 non-zero if this operand type can not actually be extracted from 283 this operand (i.e., the instruction does not match). If the 284 operand is valid, *INVALID will not be changed. */ 285 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); 286 287 /* One bit syntax flags. */ 288 unsigned long flags; 289 }; 290 291 /* Elements in the table are retrieved by indexing with values from 292 the operands field of the powerpc_opcodes table. */ 293 294 extern const struct powerpc_operand powerpc_operands[]; 295 extern const unsigned int num_powerpc_operands; 296 297 /* Use with the shift field of a struct powerpc_operand to indicate 298 that BITM and SHIFT cannot be used to determine where the operand 299 goes in the insn. */ 300 #define PPC_OPSHIFT_INV (-1U << 31) 301 302 /* Values defined for the flags field of a struct powerpc_operand. */ 303 304 /* This operand takes signed values. */ 305 #define PPC_OPERAND_SIGNED (0x1) 306 307 /* This operand takes signed values, but also accepts a full positive 308 range of values when running in 32 bit mode. That is, if bits is 309 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 310 this flag is ignored. */ 311 #define PPC_OPERAND_SIGNOPT (0x2) 312 313 /* This operand does not actually exist in the assembler input. This 314 is used to support extended mnemonics such as mr, for which two 315 operands fields are identical. The assembler should call the 316 insert function with any op value. The disassembler should call 317 the extract function, ignore the return value, and check the value 318 placed in the valid argument. */ 319 #define PPC_OPERAND_FAKE (0x4) 320 321 /* The next operand should be wrapped in parentheses rather than 322 separated from this one by a comma. This is used for the load and 323 store instructions which want their operands to look like 324 reg,displacement(reg) 325 */ 326 #define PPC_OPERAND_PARENS (0x8) 327 328 /* This operand may use the symbolic names for the CR fields, which 329 are 330 lt 0 gt 1 eq 2 so 3 un 3 331 cr0 0 cr1 1 cr2 2 cr3 3 332 cr4 4 cr5 5 cr6 6 cr7 7 333 These may be combined arithmetically, as in cr2*4+gt. These are 334 only supported on the PowerPC, not the POWER. */ 335 #define PPC_OPERAND_CR_BIT (0x10) 336 337 /* This operand names a register. The disassembler uses this to print 338 register names with a leading 'r'. */ 339 #define PPC_OPERAND_GPR (0x20) 340 341 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 342 #define PPC_OPERAND_GPR_0 (0x40) 343 344 /* This operand names a floating point register. The disassembler 345 prints these with a leading 'f'. */ 346 #define PPC_OPERAND_FPR (0x80) 347 348 /* This operand is a relative branch displacement. The disassembler 349 prints these symbolically if possible. */ 350 #define PPC_OPERAND_RELATIVE (0x100) 351 352 /* This operand is an absolute branch address. The disassembler 353 prints these symbolically if possible. */ 354 #define PPC_OPERAND_ABSOLUTE (0x200) 355 356 /* This operand is optional, and is zero if omitted. This is used for 357 example, in the optional BF field in the comparison instructions. The 358 assembler must count the number of operands remaining on the line, 359 and the number of operands remaining for the opcode, and decide 360 whether this operand is present or not. The disassembler should 361 print this operand out only if it is not zero. */ 362 #define PPC_OPERAND_OPTIONAL (0x400) 363 364 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 365 is omitted, then for the next operand use this operand value plus 366 1, ignoring the next operand field for the opcode. This wretched 367 hack is needed because the Power rotate instructions can take 368 either 4 or 5 operands. The disassembler should print this operand 369 out regardless of the PPC_OPERAND_OPTIONAL field. */ 370 #define PPC_OPERAND_NEXT (0x800) 371 372 /* This operand should be regarded as a negative number for the 373 purposes of overflow checking (i.e., the normal most negative 374 number is disallowed and one more than the normal most positive 375 number is allowed). This flag will only be set for a signed 376 operand. */ 377 #define PPC_OPERAND_NEGATIVE (0x1000) 378 379 /* This operand names a vector unit register. The disassembler 380 prints these with a leading 'v'. */ 381 #define PPC_OPERAND_VR (0x2000) 382 383 /* This operand is for the DS field in a DS form instruction. */ 384 #define PPC_OPERAND_DS (0x4000) 385 386 /* This operand is for the DQ field in a DQ form instruction. */ 387 #define PPC_OPERAND_DQ (0x8000) 388 389 /* Valid range of operand is 0..n rather than 0..n-1. */ 390 #define PPC_OPERAND_PLUS1 (0x10000) 391 392 /* Xilinx APU and FSL related operands */ 393 #define PPC_OPERAND_FSL (0x20000) 394 #define PPC_OPERAND_FCR (0x40000) 395 #define PPC_OPERAND_UDI (0x80000) 396 397 /* This operand names a vector-scalar unit register. The disassembler 398 prints these with a leading 'vs'. */ 399 #define PPC_OPERAND_VSR (0x100000) 400 401 /* This is a CR FIELD that does not use symbolic names. */ 402 #define PPC_OPERAND_CR_REG (0x200000) 403 404 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 405 is omitted, then the value it should use for the operand is stored 406 in the SHIFT field of the immediatly following operand field. */ 407 #define PPC_OPERAND_OPTIONAL_VALUE (0x400000) 408 409 /* The POWER and PowerPC assemblers use a few macros. We keep them 411 with the operands table for simplicity. The macro table is an 412 array of struct powerpc_macro. */ 413 414 struct powerpc_macro 415 { 416 /* The macro name. */ 417 const char *name; 418 419 /* The number of operands the macro takes. */ 420 unsigned int operands; 421 422 /* One bit flags for the opcode. These are used to indicate which 423 specific processors support the instructions. The values are the 424 same as those for the struct powerpc_opcode flags field. */ 425 ppc_cpu_t flags; 426 427 /* A format string to turn the macro into a normal instruction. 428 Each %N in the string is replaced with operand number N (zero 429 based). */ 430 const char *format; 431 }; 432 433 extern const struct powerpc_macro powerpc_macros[]; 434 extern const int powerpc_num_macros; 435 436 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); 437 438 static inline long 439 ppc_optional_operand_value (const struct powerpc_operand *operand) 440 { 441 if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0) 442 return (operand+1)->shift; 443 return 0; 444 } 445 446 #ifdef __cplusplus 447 } 448 #endif 449 450 #endif /* PPC_H */ 451
