| /external/clang/test/SemaCXX/ |
| access-control-check.cpp | 14 int PR() { return iP + PPR(); } // expected-error 2 {{private member of 'P'}}
|
| /external/clang/test/CodeGenCXX/ |
| nested-base-member-access.cpp | 38 void PR() {
51 n1.PR();
|
| constructor-init.cpp | 36 void PR() {
61 n1.PR();
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXTargetMachine.cpp | 77 PassRegistry &PR = *PassRegistry::getPassRegistry();
78 initializeNVVMReflectPass(PR);
79 initializeNVVMIntrRangePass(PR);
80 initializeGenericToNVVMPass(PR);
81 initializeNVPTXAllocaHoistingPass(PR);
82 initializeNVPTXAssignValidGlobalNamesPass(PR);
83 initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
84 initializeNVPTXInferAddressSpacesPass(PR);
85 initializeNVPTXLowerKernelArgsPass(PR);
86 initializeNVPTXLowerAllocaPass(PR);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetMachine.cpp | 41 PassRegistry &PR = *PassRegistry::getPassRegistry();
42 initializeWinEHStatePassPass(PR);
43 initializeFixupBWInstPassPass(PR);
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| rx-dis.c | 103 #define PR (dis->fprintf_func)
105 #define PC(c) PR (PS, "%c", c)
116 PR (PS, ".byte ");
120 PR (PS, "0x%02x ", buf[i]);
162 PR (PS, "%s", opsize_names[opcode.size]);
172 PR (PS, "%s", size_names[oper->size]);
183 PR (PS, "%#x", oper->addend);
185 PR (PS, "%d", oper->addend);
189 PR (PS, "%s", register_names[oper->reg]);
192 PR (PS, "%d[%s]", oper->addend, register_names[oper->reg])
[all...] |
| rl78-dis.c | 103 #define PR (dis->fprintf_func)
105 #define PC(c) PR (PS, "%c", c)
199 PR (PS, " \033[33mW\033[0m");
206 PR (PS, " \033[35m");
209 { PR (PS, "Z"); comma = ","; }
211 { PR (PS, "%sAC", comma); comma = ","; }
213 { PR (PS, "%sCY", comma); comma = ","; }
214 PR (PS, "\033[0m");
226 PR (PS, "es:");
245 PR (PS, "%s", condition_names[oper->condition])
[all...] |
| ia64-opc.h | 53 #define PR IA64_OPND_PR
|
| /device/google/contexthub/firmware/os/platform/stm32/ |
| exti.c | 32 volatile uint32_t PR;
64 EXTI->PR = (1UL << line);
69 return (EXTI->PR & (1UL << line)) ? true : false;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetMachine.cpp | 116 auto PR = PassRegistry::getPassRegistry();
117 initializeGlobalISel(*PR);
118 initializeAArch64ExpandPseudoPass(*PR);
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUTargetMachine.cpp | 75 PassRegistry *PR = PassRegistry::getPassRegistry();
76 initializeSILowerI1CopiesPass(*PR);
77 initializeSIFixSGPRCopiesPass(*PR);
78 initializeSIFoldOperandsPass(*PR);
79 initializeSIShrinkInstructionsPass(*PR);
80 initializeSIFixControlFlowLiveIntervalsPass(*PR);
81 initializeSILoadStoreOptimizerPass(*PR);
82 initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
83 initializeAMDGPUAnnotateUniformValuesPass(*PR);
84 initializeAMDGPUPromoteAllocaPass(*PR);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 265 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
280 unsigned PSrc = MI.getOperand(PR).getReg();
282 MI.getOperand(PR).setReg(POrig);
|
| HexagonGenMux.cpp | 76 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR,
79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
213 unsigned PR = MI->getOperand(1).getReg();
220 if (F != CM.end() && F->second.PredR != PR) {
227 F->second.PredR = PR;
248 if (!DU.Defs[PR])
272 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) {
289 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2));
|
| HexagonGenPredicate.cpp | 50 friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR);
55 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
57 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
58 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
239 Register PR = DefI->getOperand(1);
240 G2P.insert(std::make_pair(Reg, PR));
241 DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n');
242 return PR;
[all...] |
| HexagonSplitDouble.cpp | 456 unsigned PR = Cond[1].getReg();
457 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
462 const MachineInstr *CmpI = MRI->getVRegDef(PR);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetMachine.cpp | 81 PassRegistry &PR = *PassRegistry::getPassRegistry();
82 initializePPCBoolRetToIntPass(PR);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegisterScavenging.cpp | 74 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
75 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
|
| MachineVerifier.cpp | 533 BitVector PR = MFI->getPristineRegs(MBB);
534 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 58 BitVector PR = MF.getFrameInfo()->getPristineRegs(MF);
59 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
|
| TargetPassConfig.cpp | 566 const PassRegistry *PR = PassRegistry::getPassRegistry();
567 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
568 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
[all...] |
| /external/llvm/tools/llc/ |
| llc.cpp | 403 const PassRegistry *PR = PassRegistry::getPassRegistry();
422 const PassInfo *PI = PR->getPassInfo(RunPassName);
446 const PassInfo *PI = PR->getPassInfo(StartAfter);
454 const PassInfo *PI = PR->getPassInfo(StopAfter);
|
| /dalvik/docs/ |
| prettify.js | 68 var PR;
[all...] |
| /external/opencv/cvaux/src/ |
| cvsegment.cpp | 123 int k, YC, PL, PR, flag/*, curstep*/;
125 POP( YC, L, R, PL, PR, flag );
127 int data[][3] = { {-flag, L, R}, {flag, L, PL-1}, {flag,PR+1,R}};
|
| /external/opencv/cv/src/ |
| cvfloodfill.cpp | 144 int k, YC, PL, PR, dir;
145 ICV_POP( YC, L, R, PL, PR, dir );
151 {dir, PR + 1, R + _8_connectivity}
276 int k, YC, PL, PR, dir;
277 ICV_POP( YC, L, R, PL, PR, dir );
283 {dir, PR + 1, R + _8_connectivity}
453 int k, YC, PL, PR, dir, curstep;
454 ICV_POP( YC, L, R, PL, PR, dir );
460 {dir, PR + 1, R + _8_connectivity}
759 int k, YC, PL, PR, dir, curstep
[all...] |
| /libcore/luni/src/test/java/libcore/java/util/ |
| EnumSetTest.java | 104 IN, SN, SB, TE, I, XE, CS, BA, LA, CE, PR, ND, PM, SM, EU, GD, TB, DY, HO, ER, TM, YB, LU,
|
