1 /** @file 2 This header file provides common definitions just for MCH using to avoid including extra module's file. 3 4 Copyright (c) 2013-2015 Intel Corporation. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef _QNC_COMMON_DEFINITIONS_H_ 17 #define _QNC_COMMON_DEFINITIONS_H_ 18 19 // 20 // PCI CONFIGURATION MAP REGISTER OFFSETS 21 // 22 #ifndef PCI_VID 23 #define PCI_VID 0x0000 // Vendor ID Register 24 #define PCI_DID 0x0002 // Device ID Register 25 #define PCI_CMD 0x0004 // PCI Command Register 26 #define PCI_STS 0x0006 // PCI Status Register 27 #define PCI_RID 0x0008 // Revision ID Register 28 #define PCI_IFT 0x0009 // Interface Type 29 #define PCI_SCC 0x000A // Sub Class Code Register 30 #define PCI_BCC 0x000B // Base Class Code Register 31 #define PCI_CLS 0x000C // Cache Line Size 32 #define PCI_PMLT 0x000D // Primary Master Latency Timer 33 #define PCI_HDR 0x000E // Header Type Register 34 #define PCI_BIST 0x000F // Built in Self Test Register 35 #define PCI_BAR0 0x0010 // Base Address Register 0 36 #define PCI_BAR1 0x0014 // Base Address Register 1 37 #define PCI_BAR2 0x0018 // Base Address Register 2 38 #define PCI_PBUS 0x0018 // Primary Bus Number Register 39 #define PCI_SBUS 0x0019 // Secondary Bus Number Register 40 #define PCI_SUBUS 0x001A // Subordinate Bus Number Register 41 #define PCI_SMLT 0x001B // Secondary Master Latency Timer 42 #define PCI_BAR3 0x001C // Base Address Register 3 43 #define PCI_IOBASE 0x001C // I/O base Register 44 #define PCI_IOLIMIT 0x001D // I/O Limit Register 45 #define PCI_SECSTATUS 0x001E // Secondary Status Register 46 #define PCI_BAR4 0x0020 // Base Address Register 4 47 #define PCI_MEMBASE 0x0020 // Memory Base Register 48 #define PCI_MEMLIMIT 0x0022 // Memory Limit Register 49 #define PCI_BAR5 0x0024 // Base Address Register 5 50 #define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register 51 #define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register 52 #define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits 53 #define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits 54 #define PCI_SVID 0x002C // Subsystem Vendor ID 55 #define PCI_SID 0x002E // Subsystem ID 56 #define PCI_IOBASE_U 0x0030 // I/O base Upper Register 57 #define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register 58 #define PCI_CAPP 0x0034 // Capabilities Pointer 59 #define PCI_EROM 0x0038 // Expansion ROM Base Address 60 #define PCI_INTLINE 0x003C // Interrupt Line Register 61 #define PCI_INTPIN 0x003D // Interrupt Pin Register 62 #define PCI_MAXGNT 0x003E // Max Grant Register 63 #define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register 64 #define PCI_MAXLAT 0x003F // Max Latency Register 65 #endif 66 // 67 // Bit Difinitions 68 // 69 #ifndef BIT0 70 #define BIT0 0x0001 71 #define BIT1 0x0002 72 #define BIT2 0x0004 73 #define BIT3 0x0008 74 #define BIT4 0x0010 75 #define BIT5 0x0020 76 #define BIT6 0x0040 77 #define BIT7 0x0080 78 #define BIT8 0x0100 79 #define BIT9 0x0200 80 #define BIT10 0x0400 81 #define BIT11 0x0800 82 #define BIT12 0x1000 83 #define BIT13 0x2000 84 #define BIT14 0x4000 85 #define BIT15 0x8000 86 #define BIT16 0x00010000 87 #define BIT17 0x00020000 88 #define BIT18 0x00040000 89 #define BIT19 0x00080000 90 #define BIT20 0x00100000 91 #define BIT21 0x00200000 92 #define BIT22 0x00400000 93 #define BIT23 0x00800000 94 #define BIT24 0x01000000 95 #define BIT25 0x02000000 96 #define BIT26 0x04000000 97 #define BIT27 0x08000000 98 #define BIT28 0x10000000 99 #define BIT29 0x20000000 100 #define BIT30 0x40000000 101 #define BIT31 0x80000000 102 #endif 103 104 105 // 106 // Common Memory mapped Io access macros ------------------------------------------ 107 // 108 #define QNCMmioAddress( BaseAddr, Register ) \ 109 ( (UINTN)BaseAddr + \ 110 (UINTN)(Register) \ 111 ) 112 113 // 114 // UINT64 115 // 116 #define QNCMmio64Ptr( BaseAddr, Register ) \ 117 ( (volatile UINT64 *)QNCMmioAddress( BaseAddr, Register ) ) 118 119 #define QNCMmio64( BaseAddr, Register ) \ 120 *QNCMmio64Ptr( BaseAddr, Register ) 121 122 #define QNCMmio64Or( BaseAddr, Register, OrData ) \ 123 QNCMmio64( BaseAddr, Register ) = \ 124 (UINT64) ( \ 125 QNCMmio64( BaseAddr, Register ) | \ 126 (UINT64)(OrData) \ 127 ) 128 129 #define QNCMmio64And( BaseAddr, Register, AndData ) \ 130 QNCMmio64( BaseAddr, Register ) = \ 131 (UINT64) ( \ 132 QNCMmio64( BaseAddr, Register ) & \ 133 (UINT64)(AndData) \ 134 ) 135 136 #define QNCMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \ 137 QNCMmio64( BaseAddr, Register ) = \ 138 (UINT64) ( \ 139 ( QNCMmio64( BaseAddr, Register ) & \ 140 (UINT64)(AndData) \ 141 ) | \ 142 (UINT64)(OrData) \ 143 ) 144 145 // 146 // UINT32 147 // 148 #define QNCMmio32Ptr( BaseAddr, Register ) \ 149 ( (volatile UINT32 *)QNCMmioAddress( BaseAddr, Register ) ) 150 151 #define QNCMmio32( BaseAddr, Register ) \ 152 *QNCMmio32Ptr( BaseAddr, Register ) 153 154 #define QNCMmio32Or( BaseAddr, Register, OrData ) \ 155 QNCMmio32( BaseAddr, Register ) = \ 156 (UINT32) ( \ 157 QNCMmio32( BaseAddr, Register ) | \ 158 (UINT32)(OrData) \ 159 ) 160 161 #define QNCMmio32And( BaseAddr, Register, AndData ) \ 162 QNCMmio32( BaseAddr, Register ) = \ 163 (UINT32) ( \ 164 QNCMmio32( BaseAddr, Register ) & \ 165 (UINT32)(AndData) \ 166 ) 167 168 #define QNCMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \ 169 QNCMmio32( BaseAddr, Register ) = \ 170 (UINT32) ( \ 171 ( QNCMmio32( BaseAddr, Register ) & \ 172 (UINT32)(AndData) \ 173 ) | \ 174 (UINT32)(OrData) \ 175 ) 176 // 177 // UINT16 178 // 179 180 #define QNCMmio16Ptr( BaseAddr, Register ) \ 181 ( (volatile UINT16 *)QNCMmioAddress( BaseAddr, Register ) ) 182 183 #define QNCMmio16( BaseAddr, Register ) \ 184 *QNCMmio16Ptr( BaseAddr, Register ) 185 186 #define QNCMmio16Or( BaseAddr, Register, OrData ) \ 187 QNCMmio16( BaseAddr, Register ) = \ 188 (UINT16) ( \ 189 QNCMmio16( BaseAddr, Register ) | \ 190 (UINT16)(OrData) \ 191 ) 192 193 #define QNCMmio16And( BaseAddr, Register, AndData ) \ 194 QNCMmio16( BaseAddr, Register ) = \ 195 (UINT16) ( \ 196 QNCMmio16( BaseAddr, Register ) & \ 197 (UINT16)(AndData) \ 198 ) 199 200 #define QNCMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \ 201 QNCMmio16( BaseAddr, Register ) = \ 202 (UINT16) ( \ 203 ( QNCMmio16( BaseAddr, Register ) & \ 204 (UINT16)(AndData) \ 205 ) | \ 206 (UINT16)(OrData) \ 207 ) 208 // 209 // UINT8 210 // 211 #define QNCMmio8Ptr( BaseAddr, Register ) \ 212 ( (volatile UINT8 *)QNCMmioAddress( BaseAddr, Register ) ) 213 214 #define QNCMmio8( BaseAddr, Register ) \ 215 *QNCMmio8Ptr( BaseAddr, Register ) 216 217 #define QNCMmio8Or( BaseAddr, Register, OrData ) \ 218 QNCMmio8( BaseAddr, Register ) = \ 219 (UINT8) ( \ 220 QNCMmio8( BaseAddr, Register ) | \ 221 (UINT8)(OrData) \ 222 ) 223 224 #define QNCMmio8And( BaseAddr, Register, AndData ) \ 225 QNCMmio8( BaseAddr, Register ) = \ 226 (UINT8) ( \ 227 QNCMmio8( BaseAddr, Register ) & \ 228 (UINT8)(AndData) \ 229 ) 230 231 #define QNCMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \ 232 QNCMmio8( BaseAddr, Register ) = \ 233 (UINT8) ( \ 234 ( QNCMmio8( BaseAddr, Register ) & \ 235 (UINT8)(AndData) \ 236 ) | \ 237 (UINT8)(OrData) \ 238 ) 239 240 // 241 // Common Memory mapped Pci access macros ------------------------------------------ 242 // 243 244 #define QNCMmPciAddress( Segment, Bus, Device, Function, Register ) \ 245 ( (UINTN) QncGetPciExpressBaseAddress() + \ 246 (UINTN)(Bus << 20) + \ 247 (UINTN)(Device << 15) + \ 248 (UINTN)(Function << 12) + \ 249 (UINTN)(Register) \ 250 ) 251 252 // 253 // Macro to calculate the Pci device's base memory mapped address 254 // 255 #define PciDeviceMmBase( Bus, Device, Function) \ 256 ( (UINTN) QncGetPciExpressBaseAddress () + \ 257 (UINTN)(Bus << 20) + \ 258 (UINTN)(Device << 15) + \ 259 (UINTN)(Function << 12) \ 260 ) 261 262 // 263 // UINT32 264 // 265 #define QNCMmPci32Ptr( Segment, Bus, Device, Function, Register ) \ 266 ( (volatile UINT32 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) ) 267 268 #define QNCMmPci32( Segment, Bus, Device, Function, Register ) \ 269 *QNCMmPci32Ptr( Segment, Bus, Device, Function, Register ) 270 271 #define QNCMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \ 272 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \ 273 (UINT32) ( \ 274 QNCMmPci32( Segment, Bus, Device, Function, Register ) | \ 275 (UINT32)(OrData) \ 276 ) 277 278 #define QNCMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \ 279 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \ 280 (UINT32) ( \ 281 QNCMmPci32( Segment, Bus, Device, Function, Register ) & \ 282 (UINT32)(AndData) \ 283 ) 284 285 #define QNCMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ 286 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \ 287 (UINT32) ( \ 288 ( QNCMmPci32( Segment, Bus, Device, Function, Register ) & \ 289 (UINT32)(AndData) \ 290 ) | \ 291 (UINT32)(OrData) \ 292 ) 293 // 294 // UINT16 295 // 296 #define QNCMmPci16Ptr( Segment, Bus, Device, Function, Register ) \ 297 ( (volatile UINT16 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) ) 298 299 #define QNCMmPci16( Segment, Bus, Device, Function, Register ) \ 300 *QNCMmPci16Ptr( Segment, Bus, Device, Function, Register ) 301 302 #define QNCMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \ 303 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \ 304 (UINT16) ( \ 305 QNCMmPci16( Segment, Bus, Device, Function, Register ) | \ 306 (UINT16)(OrData) \ 307 ) 308 309 #define QNCMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \ 310 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \ 311 (UINT16) ( \ 312 QNCMmPci16( Segment, Bus, Device, Function, Register ) & \ 313 (UINT16)(AndData) \ 314 ) 315 316 #define QNCMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ 317 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \ 318 (UINT16) ( \ 319 ( QNCMmPci16( Segment, Bus, Device, Function, Register ) & \ 320 (UINT16)(AndData) \ 321 ) | \ 322 (UINT16)(OrData) \ 323 ) 324 // 325 // UINT8 326 // 327 #define QNCMmPci8Ptr( Segment, Bus, Device, Function, Register ) \ 328 ( (volatile UINT8 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) ) 329 330 #define QNCMmPci8( Segment, Bus, Device, Function, Register ) \ 331 *QNCMmPci8Ptr( Segment, Bus, Device, Function, Register ) 332 333 #define QNCMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \ 334 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \ 335 (UINT8) ( \ 336 QNCMmPci8( Segment, Bus, Device, Function, Register ) | \ 337 (UINT8)(OrData) \ 338 ) 339 340 #define QNCMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \ 341 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \ 342 (UINT8) ( \ 343 QNCMmPci8( Segment, Bus, Device, Function, Register ) & \ 344 (UINT8)(AndData) \ 345 ) 346 347 #define QNCMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ 348 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \ 349 (UINT8) ( \ 350 ( QNCMmPci8( Segment, Bus, Device, Function, Register ) & \ 351 (UINT8)(AndData) \ 352 ) | \ 353 (UINT8)(OrData) \ 354 ) 355 356 #endif 357
