| /cts/hostsidetests/sustainedperf/dhrystone/ |
| dhry_2.c | 20 #ifndef REG
21 #define REG
22 /* REG becomes defined as empty */
94 REG One_Fifty Int_Index;
95 REG One_Fifty Int_Loc;
144 REG One_Thirty Int_Loc;
|
| dhry_1.c | 34 #ifndef REG
35 Boolean Reg = false;
36 #define REG
37 /* REG becomes defined as empty */
40 Boolean Reg = true;
79 REG One_Fifty Int_2_Loc;
81 REG char Ch_Index;
85 REG int Run_Index;
86 REG int Number_Of_Runs;
215 REG Rec_Pointer Ptr_Val_Par
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| mips-formats.h | 64 #define REG(SIZE, LSB, BANK) \
|
| crx-opc.c | 588 REG(u4, 0x84, CRX_U_REGTYPE)
594 #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE}
599 #define REG_R(N) REG(CONCAT2(r,N), N, CRX_R_REGTYPE)
605 REG(ra, 0xe, CRX_R_REGTYPE),
606 REG(sp, 0xf, CRX_R_REGTYPE),
609 #define REG_U(N) REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE)
615 REG(ura, 0x8e, CRX_U_REGTYPE),
616 REG(usp, 0x8f, CRX_U_REGTYPE),
619 #define REG_CFG(NAME, N) REG(NAME, N, CRX_CFG_REGTYPE
[all...] |
| cr16-opc.c | 115 /* Create an arithmetic instruction - INST[d]-32bit types(reg pairs).*/
280 /* opc16 reg, preg */
284 /* opc16 preg, reg */
345 /* tbit reg reg */
351 /* opc8 reg abs20 */ \
353 /* opc20 reg abs24 */ \
355 /* opc7 reg rindex8_abs20 */ \
357 /* opc4 reg disps4(RPbase) */ \
359 /* opcNN reg disps0(RPbase) */
[all...] |
| /external/ltp/testcases/kernel/syscalls/nftw/ |
| nftw.h | 62 #define REG 1
|
| nftw64.h | 61 #define REG 1
|
| /external/syslinux/gpxe/src/arch/i386/prefix/ |
| unnrv2b.S | 58 * #define REG(x) x
70 #define REG(x) e ## x
92 #define REG(x) e ## x
101 #define xAX REG(ax)
102 #define xCX REG(cx)
103 #define xBP REG(bp)
104 #define xSI REG(si)
105 #define xDI REG(di)
|
| /hardware/google/apf/ |
| apf_interpreter.c | 88 #define REG (registers[reg_num])
141 REG = val;
190 // REG is offset of packet bytes to compare.
192 ASSERT_IN_PACKET_BOUNDS(REG);
193 const uint32_t last_packet_offs = REG + cmp_imm - 1;
194 ASSERT_RETURN(last_packet_offs >= REG);
196 if (memcmp(program + pc, packet + REG, cmp_imm))
232 REG = signed_imm;
244 REG = memory[imm - LDM_EXT_OPCODE];
246 memory[imm - STM_EXT_OPCODE] = REG;
[all...] |
| /toolchain/binutils/binutils-2.27/bfd/ |
| cpu-ia64-opc.c | 467 #define REG IA64_OPND_CLASS_REG
494 { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
496 { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
498 { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
500 { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
502 { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
504 { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
506 { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
508 { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
510 { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 *
[all...] |
| /toolchain/binutils/binutils-2.27/include/opcode/ |
| i960.h | 40 #define REG 3
50 /* Masks for the mode bits in REG format instructions */
55 /* Generate the 12-bit opcode for a REG format instruction by placing the
62 /* Generate a template for a REG format instruction: place the opcode bits
70 * The information is also useful to us because some 1-operand REG instructions
71 * use the src1 field, others the dst field; and some 2-operand REG instructions
131 /* TRUE if reg #n is properly aligned */
139 char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */
284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } },
285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }
[all...] |
| m88k.h | 209 /* Max clocks before reg is available. */
211 /* Writeback priority of reg. */
387 REG = 2,
|
| h8300.h | 47 REG = 0x0100,
95 /* Mask to isolate the addressing mode bits (REG .. PREDEC). */
138 RD8 = DST | L_8 | REG,
139 RD16 = DST | L_16 | REG,
140 RD32 = DST | L_32 | REG,
141 R3_8 = OP3 | L_8 | REG,
142 R3_16 = OP3 | L_16 | REG,
143 R3_32 = OP3 | L_32 | REG,
144 RS8 = SRC | L_8 | REG,
145 RS16 = SRC | L_16 | REG,
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| EDEmitter.cpp | 243 #define REG(str) if (name == str) SET("kOperandTypeRegister");
256 REG("GR8");
257 REG("GR8_NOREX");
258 REG("GR16");
259 REG("GR16_NOAX");
260 REG("GR32");
261 REG("GR32_NOAX");
262 REG("GR32_NOREX");
263 REG("GR32_TC");
264 REG("FR32")
[all...] |
| /external/v8/src/x87/ |
| macro-assembler-x87.cc | 123 #define REG(Name) \
126 static const Register saved_regs[] = {REG(eax), REG(ecx), REG(edx)};
128 #undef REG
139 Register reg = saved_regs[i]; local
140 if (!reg.is(exclusion1) && !reg.is(exclusion2) && !reg.is(exclusion3)) {
141 push(reg);
160 Register reg = saved_regs[i]; local
[all...] |
| /external/v8/src/ia32/ |
| macro-assembler-ia32.cc | 123 #define REG(Name) \
126 static const Register saved_regs[] = {REG(eax), REG(ecx), REG(edx)};
128 #undef REG
139 Register reg = saved_regs[i]; local
140 if (!reg.is(exclusion1) && !reg.is(exclusion2) && !reg.is(exclusion3)) {
141 push(reg);
148 XMMRegister reg = XMMRegister::from_code(i); local
149 movsd(Operand(esp, (i - 1) * kDoubleSize), reg); local
159 XMMRegister reg = XMMRegister::from_code(i); local
166 Register reg = saved_regs[i]; local
1111 XMMRegister reg = XMMRegister::from_code(i); local
1112 movsd(Operand(ebp, offset - ((i + 1) * kDoubleSize)), reg); local
1154 XMMRegister reg = XMMRegister::from_code(i); local
[all...] |
| /external/v8/src/x64/ |
| macro-assembler-x64.cc | 739 #define REG(Name) \
743 REG(rax), REG(rcx), REG(rdx), REG(rbx), REG(rbp), REG(rsi), REG(rdi), REG(r8),
744 REG(r9), REG(r10), REG(r11
760 Register reg = saved_regs[i]; local
769 XMMRegister reg = XMMRegister::from_code(i); local
770 Movsd(Operand(rsp, i * kDoubleSize), reg); local
782 XMMRegister reg = XMMRegister::from_code(i); local
788 Register reg = saved_regs[i]; local
4476 DoubleRegister reg = local
4478 Movsd(Operand(rbp, offset - ((i + 1) * kDoubleSize)), reg); local
4522 DoubleRegister reg = local
[all...] |
