| /prebuilts/go/darwin-x86/test/interface/ |
| convert1.go | 12 type RW interface { R(); W() }
16 var rw RW var
20 r = rw
22 e = rw
23 rw = rw
|
| convert2.go | 12 type RW interface { R(); W() }
16 var rw RW var
20 r = rw
22 e = rw
23 rw = rw
|
| /prebuilts/go/linux-x86/test/interface/ |
| convert1.go | 12 type RW interface { R(); W() }
16 var rw RW var
20 r = rw
22 e = rw
23 rw = rw
|
| convert2.go | 12 type RW interface { R(); W() }
16 var rw RW var
20 r = rw
22 e = rw
23 rw = rw
|
| /external/compiler-rt/lib/tsan/tests/rtl/ |
| tsan_test_util.h | 36 RW,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
89 return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1)
90 : BT::BitMask(RW, 2*RW-1);
204 // Extract RW low bits of the cell.
205 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
207 assert(RW <= RC.width());
208 return eXTR(RC, 0, RW);
210 // Extract RW high bits of the cell.
211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenSchedule.cpp | 194 // Visit each RW in the sequence selected by the current variant.
301 CodeGenSchedRW &RW = getSchedRW(MatchDef);
302 if (RW.IsAlias)
304 RW.Aliases.push_back(*AI);
437 " Ensure only one SchedAlias exists per RW.");
469 // Index zero reserved for invalid RW.
[all...] |
| /external/autotest/client/common_lib/cros/ |
| cr50_utils.py | 13 RW = 'rw'
27 # 'fwver' is used to get the running RO and RW versions from cr50
28 # 'binvers' gets the version strings for each RO and RW region in the given
42 # keyids: RO 0xaa66150f, RW 0xde88588d
43 # offsets: backup RO at 0x40000, backup RW at 0x44000
46 # RW 0.0.21
50 # 'rw': '0.0.21'
68 '--fwver' : '\nRO (?P<ro>\S+).*\nRW (?P<rw>\S+)',
159 """Find the ro and rw versions
[all...] |
| /external/clang/test/Layout/ |
| ms-x86-alias-avoidance-padding.cpp | 304 struct RW { char c; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
485 // CHECK-NEXT: 8 | struct RW (virtual base)
497 // CHECK-X64-NEXT: 16 | struct RW (virtual base)
510 // CHECK-NEXT: 4 | struct RW (virtual base)
521 // CHECK-X64-NEXT: 8 | struct RW (virtual base)
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| rl78-decode.c | 63 #define RW(x) ((x)+RL78_Reg_AX)
111 #define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
122 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
218 int rw AU = (op[0] >> 1) & 0x03;
224 printf (" rw = 0x%x\n", rw);
228 ID(add); W(); DR(AX); SRW(rw); Fzac;
624 int rw AU = (op[0] >> 1) & 0x03;
630 printf (" rw = 0x%x\n", rw);
[all...] |
| /external/python/cpython3/Lib/test/ |
| test_enum.py | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 763 Value *Locality, *RW, *Address = EmitScalarExpr(E->getArg(0));
765 RW = (E->getNumArgs() > 1) ? EmitScalarExpr(E->getArg(1)) :
771 return RValue::get(Builder.CreateCall(F, {Address, RW, Locality, Data}));
[all...] |
| /prebuilts/tools/common/bazel/formc-deps/ |
| jps-builders.jar | |
| /prebuilts/tools/common/m2/repository/com/amazonaws/aws-java-sdk-route53/1.11.18/ |
| aws-java-sdk-route53-1.11.18.jar | |
| /prebuilts/tools/common/intellij-core/171.2455.10/ |
| intellij-core.jar | |
