| /external/fec/ |
| encode_rs_8.c | 12 static enum {UNKNOWN=0,MMX,SSE,SSE2,ALTIVEC,PORT} cpu_mode;
28 if(f & (1<<26)){ /* SSE2 is present */
29 cpu_mode = SSE2;
60 case SSE2:
|
| fec.h | 261 extern enum cpu_mode {UNKNOWN=0,PORT,MMX,SSE,SSE2,ALTIVEC} Cpu_mode;
|
| /external/skia/src/core/ |
| SkCpu.h | 16 SSE2 = 1 << 1,
65 features |= SSE2;
91 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41);
93 features &= (SkCpu::SSE1 | SkCpu::SSE2);
|
| /external/skqp/src/core/ |
| SkCpu.h | 16 SSE2 = 1 << 1,
65 features |= SSE2;
91 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41);
93 features &= (SkCpu::SSE1 | SkCpu::SSE2);
|
| /external/swiftshader/src/Common/ |
| CPUID.cpp | 35 bool CPUID::SSE2 = detectSSE2();
206 return SSE2 = (registers[3] & 0x04000000) != 0;
|
| CPUID.hpp | 57 static bool SSE2;
108 return SSE2 && enableSSE2;
|
| /external/libchrome/base/ |
| cpu.h | 23 SSE2,
|
| /external/tensorflow/tensorflow/core/platform/ |
| cpu_info.h | 42 SSE2 = 2,
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| isa.hpp | 76 bool SSE2(void) { return CPU_Rep.f_1_EDX_[26]; }
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| PlatformCpuInfo.h | 137 UINT8 SSE2; // EDX [26]
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86Subtarget.h | 45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42
56 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
174 bool hasSSE2() const { return X86SSELevel >= SSE2; }
|
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringX8632Traits.h | 270 // SSE2 is the PNaCl baseline instruction set.
271 SSE2 = Begin,
[all...] |
| IceTargetLoweringX8664Traits.h | 295 // SSE2 is the PNaCl baseline instruction set.
296 SSE2 = Begin,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86Subtarget.h | 49 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
68 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
383 bool hasSSE2() const { return X86SSELevel >= SSE2; }
457 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
458 /// no-sse2). There isn't any reason to disable it if the target processor
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ |
| Cpuid.h | 505 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
507 UINT32 SSE2:1;
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
