1 /* Copyright 2016 The TensorFlow Authors. All Rights Reserved. 2 3 Licensed under the Apache License, Version 2.0 (the "License"); 4 you may not use this file except in compliance with the License. 5 You may obtain a copy of the License at 6 7 http://www.apache.org/licenses/LICENSE-2.0 8 9 Unless required by applicable law or agreed to in writing, software 10 distributed under the License is distributed on an "AS IS" BASIS, 11 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 See the License for the specific language governing permissions and 13 limitations under the License. 14 ==============================================================================*/ 15 16 #ifndef TENSORFLOW_PLATFORM_CPU_INFO_H_ 17 #define TENSORFLOW_PLATFORM_CPU_INFO_H_ 18 19 #include <string> 20 21 #if defined(PLATFORM_WINDOWS) 22 #include "tensorflow/core/platform/windows/cpu_info.h" 23 #endif 24 25 namespace tensorflow { 26 namespace port { 27 28 // TODO(jeff,sanjay): Make portable 29 constexpr bool kLittleEndian = __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__; 30 31 // Returns an estimate of the number of schedulable CPUs for this 32 // process. Usually, it's constant throughout the lifetime of a 33 // process, but it might change if the underlying cluster management 34 // software can change it dynamically. 35 int NumSchedulableCPUs(); 36 37 // Mostly ISA related features that we care about 38 enum CPUFeature { 39 // Do not change numeric assignments. 40 MMX = 0, 41 SSE = 1, 42 SSE2 = 2, 43 SSE3 = 3, 44 SSSE3 = 4, 45 SSE4_1 = 5, 46 SSE4_2 = 6, 47 CMOV = 7, 48 CMPXCHG8B = 8, 49 CMPXCHG16B = 9, 50 POPCNT = 10, 51 AES = 11, 52 AVX = 12, 53 RDRAND = 13, 54 AVX2 = 14, 55 FMA = 15, 56 F16C = 16, 57 PCLMULQDQ = 17, 58 RDSEED = 18, 59 ADX = 19, 60 SMAP = 20, 61 62 // Prefetch Vector Data Into Caches with Intent to Write and T1 Hint 63 // http://www.felixcloutier.com/x86/PREFETCHWT1.html. 64 // You probably want PREFETCHW instead. 65 PREFETCHWT1 = 21, 66 67 BMI1 = 22, 68 BMI2 = 23, 69 HYPERVISOR = 25, // 0 when on a real CPU, 1 on (well-behaved) hypervisor. 70 71 // Prefetch Data into Caches in Anticipation of a Write (3D Now!). 72 // http://www.felixcloutier.com/x86/PREFETCHW.html 73 PREFETCHW = 26, 74 75 // AVX-512: 512-bit vectors (plus masking, etc.) in Knights Landing, 76 // Skylake 77 // Xeon, etc.; each of these entries is a different subset of 78 // instructions, 79 // various combinations of which occur on various CPU types. 80 AVX512F = 27, // Foundation 81 AVX512CD = 28, // Conflict detection 82 AVX512ER = 29, // Exponential and reciprocal 83 AVX512PF = 30, // Prefetching 84 AVX512VL = 31, // Shorter vector lengths 85 AVX512BW = 32, // Byte and word 86 AVX512DQ = 33, // Dword and qword 87 AVX512VBMI = 34, // Bit manipulation 88 AVX512IFMA = 35, // Integer multiply-add 89 AVX512_4VNNIW = 36, // Integer neural network 90 AVX512_4FMAPS = 37, // Floating point neural network 91 }; 92 93 // Checks whether the current processor supports one of the features above. 94 // Checks CPU registers to return hardware capabilities. 95 bool TestCPUFeature(CPUFeature feature); 96 97 // Returns CPU Vendor string (i.e. 'GenuineIntel', 'AuthenticAMD', etc.) 98 std::string CPUVendorIDString(); 99 100 // Returns CPU family. 101 int CPUFamily(); 102 103 // Returns CPU model number. 104 int CPUModelNum(); 105 106 // Returns nominal core processor cycles per second of each processor. 107 double NominalCPUFrequency(); 108 109 } // namespace port 110 } // namespace tensorflow 111 112 #endif // TENSORFLOW_PLATFORM_CPU_INFO_H_ 113
