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  /external/skia/src/opts/
opts_check_x86.cpp 37 /* Every optimization in the function requires at least SSE2 */
38 if (!SkCpu::Supports(SkCpu::SSE2)) {
76 if (SkCpu::Supports(SkCpu::SSE2)) {
86 if (SkCpu::Supports(SkCpu::SSE2)) {
  /external/skqp/src/opts/
opts_check_x86.cpp 37 /* Every optimization in the function requires at least SSE2 */
38 if (!SkCpu::Supports(SkCpu::SSE2)) {
76 if (SkCpu::Supports(SkCpu::SSE2)) {
86 if (SkCpu::Supports(SkCpu::SSE2)) {
  /external/fec/
viterbi27.c 26 case SSE2:
50 case SSE2:
72 case SSE2:
98 case SSE2:
123 case SSE2:
155 case SSE2:
viterbi29.c 26 case SSE2:
50 case SSE2:
72 case SSE2:
98 case SSE2:
123 case SSE2:
148 case SSE2:
viterbi39.c 26 case SSE2:
50 case SSE2:
73 case SSE2:
99 case SSE2:
124 case SSE2:
149 case SSE2:
viterbi615.c 27 case SSE2:
52 case SSE2:
74 case SSE2:
100 case SSE2:
125 case SSE2:
150 case SSE2:
cpu_mode_x86.c 10 "x86 Streaming SIMD Extensions 2 (SSE2)",
23 if(f & (1<<26)){ /* SSE2 is present */
24 Cpu_mode = SSE2;
sumsq.c 31 case SSE2:
dotprod.c 40 case SSE2:
61 case SSE2:
83 case SSE2:
dotprod_sse2_assist.s 1 # SIMD SSE2 dot product
30 # SSE2 dot product loop unrolled 4 times, crunching 32 terms per loop
58 # SSE2 dot product loop, not unrolled, crunching 4 terms per loop
peakval.c 31 case SSE2:
encode_rs_8.c 12 static enum {UNKNOWN=0,MMX,SSE,SSE2,ALTIVEC,PORT} cpu_mode;
28 if(f & (1<<26)){ /* SSE2 is present */
29 cpu_mode = SSE2;
60 case SSE2:
dtest.c 19 {"force-sse2",0,NULL,'t'},
50 Cpu_mode = SSE2;
sse2bfly29.s 1 /* Intel SIMD SSE2 implementation of Viterbi ACS butterflies
9 # SSE2 (128-bit integer SIMD) version
sumsq_test.c 20 {"force-sse2",0,NULL,'t'},
58 Cpu_mode = SSE2;
  /external/skia/src/core/
SkCpu.h 16 SSE2 = 1 << 1,
65 features |= SSE2;
91 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41);
93 features &= (SkCpu::SSE1 | SkCpu::SSE2);
  /external/skqp/src/core/
SkCpu.h 16 SSE2 = 1 << 1,
65 features |= SSE2;
91 features &= (SkCpu::SSE1 | SkCpu::SSE2 | SkCpu::SSE3 | SkCpu::SSSE3 | SkCpu::SSE41);
93 features &= (SkCpu::SSE1 | SkCpu::SSE2);
  /external/libyuv/files/util/
Makefile 3 $(CXX) /arch:SSE2 /Ox /openmp psnr.cc ssim.cc psnr_main.cc
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/
sse-check-none.s 10 # SSE2 instruction
sse-check.s 9 # SSE2 instruction
  /external/swiftshader/src/Common/
CPUID.hpp 57 static bool SSE2;
108 return SSE2 && enableSSE2;
  /external/tensorflow/tensorflow/core/platform/
cpu_info.h 42 SSE2 = 2,
cpu_feature_guard.cc 65 CheckFeatureOrDie(CPUFeature::SSE2, "SSE2");
115 CheckIfFeatureUnused(CPUFeature::SSE2, "SSE2", missing_instructions);
  /external/valgrind/exp-bbv/tests/amd64-linux/
rep_prefix.S 14 # Some SSE2 instructions start with 0xf2 or 0xf3
18 # have to check for SSE2 capability somehow?
  /external/libchrome/base/
cpu.h 23 SSE2,

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