1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "llvm/MC/MCInstrDesc.h" 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 15 16 namespace SIInstrFlags { 17 // This needs to be kept in sync with the field bits in InstSI. 18 enum { 19 SALU = 1 << 3, 20 VALU = 1 << 4, 21 22 SOP1 = 1 << 5, 23 SOP2 = 1 << 6, 24 SOPC = 1 << 7, 25 SOPK = 1 << 8, 26 SOPP = 1 << 9, 27 28 VOP1 = 1 << 10, 29 VOP2 = 1 << 11, 30 VOP3 = 1 << 12, 31 VOPC = 1 << 13, 32 SDWA = 1 << 14, 33 DPP = 1 << 15, 34 35 MUBUF = 1 << 16, 36 MTBUF = 1 << 17, 37 SMRD = 1 << 18, 38 DS = 1 << 19, 39 MIMG = 1 << 20, 40 FLAT = 1 << 21, 41 WQM = 1 << 22, 42 VGPRSpill = 1 << 23, 43 VOPAsmPrefer32Bit = 1 << 24, 44 Gather4 = 1 << 25 45 }; 46 } 47 48 namespace llvm { 49 namespace AMDGPU { 50 enum OperandType { 51 /// Operand with register or 32-bit immediate 52 OPERAND_REG_IMM32 = MCOI::OPERAND_FIRST_TARGET, 53 /// Operand with register or inline constant 54 OPERAND_REG_INLINE_C, 55 56 /// Operand with 32-bit immediate that uses the constant bus. The standard 57 /// OPERAND_IMMEDIATE should be used for special immediates such as source 58 /// modifiers. 59 OPERAND_KIMM32 60 }; 61 } 62 } 63 64 namespace SIInstrFlags { 65 enum Flags { 66 // First 4 bits are the instruction encoding 67 VM_CNT = 1 << 0, 68 EXP_CNT = 1 << 1, 69 LGKM_CNT = 1 << 2 70 }; 71 72 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 73 // The result is true if any of these tests are true. 74 enum ClassFlags { 75 S_NAN = 1 << 0, // Signaling NaN 76 Q_NAN = 1 << 1, // Quiet NaN 77 N_INFINITY = 1 << 2, // Negative infinity 78 N_NORMAL = 1 << 3, // Negative normal 79 N_SUBNORMAL = 1 << 4, // Negative subnormal 80 N_ZERO = 1 << 5, // Negative zero 81 P_ZERO = 1 << 6, // Positive zero 82 P_SUBNORMAL = 1 << 7, // Positive subnormal 83 P_NORMAL = 1 << 8, // Positive normal 84 P_INFINITY = 1 << 9 // Positive infinity 85 }; 86 } 87 88 // Input operand modifiers bit-masks 89 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 90 namespace SISrcMods { 91 enum { 92 NEG = 1 << 0, // Floating-point negate modifier 93 ABS = 1 << 1, // Floating-point absolute modifier 94 SEXT = 1 << 0 // Integer sign-extend modifier 95 }; 96 } 97 98 namespace SIOutMods { 99 enum { 100 NONE = 0, 101 MUL2 = 1, 102 MUL4 = 2, 103 DIV2 = 3 104 }; 105 } 106 107 namespace llvm { 108 namespace AMDGPU { 109 namespace EncValues { // Encoding values of enum9/8/7 operands 110 111 enum { 112 SGPR_MIN = 0, 113 SGPR_MAX = 101, 114 TTMP_MIN = 112, 115 TTMP_MAX = 123, 116 INLINE_INTEGER_C_MIN = 128, 117 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 118 INLINE_INTEGER_C_MAX = 208, 119 INLINE_FLOATING_C_MIN = 240, 120 INLINE_FLOATING_C_MAX = 248, 121 LITERAL_CONST = 255, 122 VGPR_MIN = 256, 123 VGPR_MAX = 511 124 }; 125 126 } // namespace EncValues 127 } // namespace AMDGPU 128 } // namespace llvm 129 130 namespace llvm { 131 namespace AMDGPU { 132 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 133 134 enum Id { // Message ID, width(4) [3:0]. 135 ID_UNKNOWN_ = -1, 136 ID_INTERRUPT = 1, 137 ID_GS, 138 ID_GS_DONE, 139 ID_SYSMSG = 15, 140 ID_GAPS_LAST_, // Indicate that sequence has gaps. 141 ID_GAPS_FIRST_ = ID_INTERRUPT, 142 ID_SHIFT_ = 0, 143 ID_WIDTH_ = 4, 144 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 145 }; 146 147 enum Op { // Both GS and SYS operation IDs. 148 OP_UNKNOWN_ = -1, 149 OP_SHIFT_ = 4, 150 // width(2) [5:4] 151 OP_GS_NOP = 0, 152 OP_GS_CUT, 153 OP_GS_EMIT, 154 OP_GS_EMIT_CUT, 155 OP_GS_LAST_, 156 OP_GS_FIRST_ = OP_GS_NOP, 157 OP_GS_WIDTH_ = 2, 158 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_), 159 // width(3) [6:4] 160 OP_SYS_ECC_ERR_INTERRUPT = 1, 161 OP_SYS_REG_RD, 162 OP_SYS_HOST_TRAP_ACK, 163 OP_SYS_TTRACE_PC, 164 OP_SYS_LAST_, 165 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 166 OP_SYS_WIDTH_ = 3, 167 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_) 168 }; 169 170 enum StreamId { // Stream ID, (2) [9:8]. 171 STREAM_ID_DEFAULT_ = 0, 172 STREAM_ID_LAST_ = 4, 173 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 174 STREAM_ID_SHIFT_ = 8, 175 STREAM_ID_WIDTH_= 2, 176 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 177 }; 178 179 } // namespace SendMsg 180 181 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 182 183 enum Id { // HwRegCode, (6) [5:0] 184 ID_UNKNOWN_ = -1, 185 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 186 ID_SYMBOLIC_LAST_ = 8, 187 ID_SHIFT_ = 0, 188 ID_WIDTH_ = 6, 189 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 190 }; 191 192 enum Offset { // Offset, (5) [10:6] 193 OFFSET_DEFAULT_ = 0, 194 OFFSET_SHIFT_ = 6, 195 OFFSET_WIDTH_ = 5, 196 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_) 197 }; 198 199 enum WidthMinusOne { // WidthMinusOne, (5) [15:11] 200 WIDTH_M1_DEFAULT_ = 31, 201 WIDTH_M1_SHIFT_ = 11, 202 WIDTH_M1_WIDTH_ = 5, 203 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_) 204 }; 205 206 } // namespace Hwreg 207 } // namespace AMDGPU 208 } // namespace llvm 209 210 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 211 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 212 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 213 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 214 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 215 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 216 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 217 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 218 219 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 220 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 221 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 222 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 223 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 224 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 225 #define C_00B84C_USER_SGPR 0xFFFFFFC1 226 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 227 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 228 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 229 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 230 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 231 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 232 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 233 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 234 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 235 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 236 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 237 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 238 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 239 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 240 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 241 /* CIK */ 242 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 243 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 244 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 245 /* */ 246 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 247 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 248 #define C_00B84C_LDS_SIZE 0xFF007FFF 249 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 250 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 251 #define C_00B84C_EXCP_EN 252 253 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 254 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 255 256 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 257 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 258 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 259 #define C_00B848_VGPRS 0xFFFFFFC0 260 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 261 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 262 #define C_00B848_SGPRS 0xFFFFFC3F 263 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 264 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 265 #define C_00B848_PRIORITY 0xFFFFF3FF 266 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 267 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 268 #define C_00B848_FLOAT_MODE 0xFFF00FFF 269 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 270 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 271 #define C_00B848_PRIV 0xFFEFFFFF 272 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 273 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 274 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 275 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 276 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 277 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 278 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 279 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 280 #define C_00B848_IEEE_MODE 0xFF7FFFFF 281 282 283 // Helpers for setting FLOAT_MODE 284 #define FP_ROUND_ROUND_TO_NEAREST 0 285 #define FP_ROUND_ROUND_TO_INF 1 286 #define FP_ROUND_ROUND_TO_NEGINF 2 287 #define FP_ROUND_ROUND_TO_ZERO 3 288 289 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 290 // precision. 291 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 292 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 293 294 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 295 #define FP_DENORM_FLUSH_OUT 1 296 #define FP_DENORM_FLUSH_IN 2 297 #define FP_DENORM_FLUSH_NONE 3 298 299 300 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 301 // precision. 302 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 303 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 304 305 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 306 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 307 308 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 309 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 310 311 #define R_SPILLED_SGPRS 0x4 312 #define R_SPILLED_VGPRS 0x8 313 314 #endif 315
