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      1 /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
      2    Copyright (C) 1996-2016 Free Software Foundation, Inc.
      3    Written by Fred Fish (fnf (at) cygnus.com), Cygnus Support
      4 
      5    This file is part of GDB, GAS, and the GNU binutils.
      6 
      7    GDB, GAS, and the GNU binutils are free software; you can redistribute
      8    them and/or modify them under the terms of the GNU General Public
      9    License as published by the Free Software Foundation; either version 3,
     10    or (at your option) any later version.
     11 
     12    GDB, GAS, and the GNU binutils are distributed in the hope that they
     13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
     14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
     15    the GNU General Public License for more details.
     16 
     17    You should have received a copy of the GNU General Public License
     18    along with this file; see the file COPYING3.  If not, write to the Free
     19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
     20    MA 02110-1301, USA.  */
     21 
     22 #ifndef TIC80_H
     23 #define TIC80_H
     24 
     25 /* The opcode table is an array of struct tic80_opcode.  */
     26 
     27 struct tic80_opcode
     28 {
     29   /* The opcode name.  */
     30 
     31   const char *name;
     32 
     33   /* The opcode itself.  Those bits which will be filled in with operands
     34      are zeroes.  */
     35 
     36   unsigned long opcode;
     37 
     38   /* The opcode mask.  This is used by the disassembler.  This is a mask
     39      containing ones indicating those bits which must match the opcode
     40      field, and zeroes indicating those bits which need not match (and are
     41      presumably filled in by operands).  */
     42 
     43   unsigned long mask;
     44 
     45   /* Special purpose flags for this opcode. */
     46 
     47   unsigned char flags;
     48 
     49   /* An array of operand codes.  Each code is an index into the operand
     50      table.  They appear in the order which the operands must appear in
     51      assembly code, and are terminated by a zero.  FIXME: Adjust size to
     52      match actual requirements when TIc80 support is complete */
     53 
     54   unsigned char operands[8];
     55 };
     56 
     57 /* The table itself is sorted by major opcode number, and is otherwise in
     58    the order in which the disassembler should consider instructions.
     59    FIXME: This isn't currently true. */
     60 
     61 extern const struct tic80_opcode tic80_opcodes[];
     62 extern const int tic80_num_opcodes;
     63 
     64 
     65 /* The operands table is an array of struct tic80_operand.  */
     67 
     68 struct tic80_operand
     69 {
     70   /* The number of bits in the operand.  */
     71 
     72   int bits;
     73 
     74   /* How far the operand is left shifted in the instruction.  */
     75 
     76   int shift;
     77 
     78   /* Insertion function.  This is used by the assembler.  To insert an
     79      operand value into an instruction, check this field.
     80 
     81      If it is NULL, execute
     82          i |= (op & ((1 << o->bits) - 1)) << o->shift;
     83      (i is the instruction which we are filling in, o is a pointer to
     84      this structure, and op is the opcode value; this assumes twos
     85      complement arithmetic).
     86 
     87      If this field is not NULL, then simply call it with the
     88      instruction and the operand value.  It will return the new value
     89      of the instruction.  If the ERRMSG argument is not NULL, then if
     90      the operand value is illegal, *ERRMSG will be set to a warning
     91      string (the operand will be inserted in any case).  If the
     92      operand value is legal, *ERRMSG will be unchanged (most operands
     93      can accept any value).  */
     94 
     95   unsigned long (*insert)
     96     (unsigned long instruction, long op, const char **errmsg);
     97 
     98   /* Extraction function.  This is used by the disassembler.  To
     99      extract this operand type from an instruction, check this field.
    100 
    101      If it is NULL, compute
    102          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
    103 	 if ((o->flags & TIC80_OPERAND_SIGNED) != 0
    104 	     && (op & (1 << (o->bits - 1))) != 0)
    105 	   op -= 1 << o->bits;
    106      (i is the instruction, o is a pointer to this structure, and op
    107      is the result; this assumes twos complement arithmetic).
    108 
    109      If this field is not NULL, then simply call it with the
    110      instruction value.  It will return the value of the operand.  If
    111      the INVALID argument is not NULL, *INVALID will be set to
    112      non-zero if this operand type can not actually be extracted from
    113      this operand (i.e., the instruction does not match).  If the
    114      operand is valid, *INVALID will not be changed.  */
    115 
    116   long (*extract) (unsigned long instruction, int *invalid);
    117 
    118   /* One bit syntax flags.  */
    119 
    120   unsigned long flags;
    121 };
    122 
    123 /* Elements in the table are retrieved by indexing with values from
    124    the operands field of the tic80_opcodes table.  */
    125 
    126 extern const struct tic80_operand tic80_operands[];
    127 
    128 
    129 /* Values defined for the flags field of a struct tic80_operand.
    131 
    132    Note that flags for all predefined symbols, such as the general purpose
    133    registers (ex: r10), control registers (ex: FPST), condition codes (ex:
    134    eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be
    135    or'd into an int where the lower bits contain the actual numeric value
    136    that correponds to this predefined symbol.  This way a single int can
    137    contain both the value of the symbol and it's type.
    138  */
    139 
    140 /* This operand must be an even register number.  Floating point numbers
    141    for example are stored in even/odd register pairs. */
    142 
    143 #define TIC80_OPERAND_EVEN	(1 << 0)
    144 
    145 /* This operand must be an odd register number and must be one greater than
    146    the register number of the previous operand.  I.E. the second register in
    147    an even/odd register pair. */
    148 
    149 #define TIC80_OPERAND_ODD	(1 << 1)
    150 
    151 /* This operand takes signed values.  */
    152 
    153 #define TIC80_OPERAND_SIGNED	(1 << 2)
    154 
    155 /* This operand may be either a predefined constant name or a numeric value.
    156    An example would be a condition code like "eq0.b" which has the numeric
    157    value 0x2. */
    158 
    159 #define TIC80_OPERAND_NUM	(1 << 3)
    160 
    161 /* This operand should be wrapped in parentheses rather than separated
    162    from the previous one by a comma.  This is used for various
    163    instructions, like the load and store instructions, which want
    164    their operands to look like "displacement(reg)" */
    165 
    166 #define TIC80_OPERAND_PARENS	(1 << 4)
    167 
    168 /* This operand is a PC relative branch offset.  The disassembler prints
    169    these symbolically if possible.  Note that the offsets are taken as word
    170    offsets. */
    171 
    172 #define TIC80_OPERAND_PCREL	(1 << 5)
    173 
    174 /* This flag is a hint to the disassembler for using hex as the prefered
    175    printing format, even for small positive or negative immediate values.
    176    Normally values in the range -999 to 999 are printed as signed decimal
    177    values and other values are printed in hex. */
    178 
    179 #define TIC80_OPERAND_BITFIELD	(1 << 6)
    180 
    181 /* This operand may have a ":m" modifier specified by bit 17 in a short
    182    immediate form instruction. */
    183 
    184 #define TIC80_OPERAND_M_SI	(1 << 7)
    185 
    186 /* This operand may have a ":m" modifier specified by bit 15 in a long
    187    immediate or register form instruction. */
    188 
    189 #define TIC80_OPERAND_M_LI	(1 << 8)
    190 
    191 /* This operand may have a ":s" modifier specified in bit 11 in a long
    192    immediate or register form instruction. */
    193 
    194 #define TIC80_OPERAND_SCALED	(1 << 9)
    195 
    196 /* This operand is a floating point value */
    197 
    198 #define TIC80_OPERAND_FLOAT	(1 << 10)
    199 
    200 /* This operand is an byte offset from a base relocation. The lower
    201  two bits of the final relocated address are ignored when the value is
    202  written to the program counter. */
    203 
    204 #define TIC80_OPERAND_BASEREL	(1 << 11)
    205 
    206 /* This operand is an "endmask" field for a shift instruction.
    207    It is treated special in that it can have values of 0-32,
    208    where 0 and 32 result in the same instruction.  The assembler
    209    must be able to accept both endmask values.  This disassembler
    210    has no way of knowing from the instruction which value was
    211    given at assembly time, so it just uses '0'. */
    212 
    213 #define TIC80_OPERAND_ENDMASK	(1 << 12)
    214 
    215 /* This operand is one of the 32 general purpose registers.
    216    The disassembler prints these with a leading 'r'. */
    217 
    218 #define TIC80_OPERAND_GPR	(1 << 27)
    219 
    220 /* This operand is a floating point accumulator register.
    221    The disassembler prints these with a leading 'a'. */
    222 
    223 #define TIC80_OPERAND_FPA	( 1 << 28)
    224 
    225 /* This operand is a control register number, either numeric or
    226    symbolic (like "EIF", "EPC", etc).
    227    The disassembler prints these symbolically. */
    228 
    229 #define TIC80_OPERAND_CR	(1 << 29)
    230 
    231 /* This operand is a condition code, either numeric or
    232    symbolic (like "eq0.b", "ne0.w", etc).
    233    The disassembler prints these symbolically. */
    234 
    235 #define TIC80_OPERAND_CC	(1 << 30)
    236 
    237 /* This operand is a bit number, either numeric or
    238    symbolic (like "eq.b", "or.f", etc).
    239    The disassembler prints these symbolically.
    240    Note that they appear in the instruction in 1's complement relative
    241    to the values given in the manual. */
    242 
    243 #define TIC80_OPERAND_BITNUM	(1 << 31)
    244 
    245 /* This mask is used to strip operand bits from an int that contains
    246    both operand bits and a numeric value in the lsbs. */
    247 
    248 #define TIC80_OPERAND_MASK	(TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM)
    249 
    250 
    251 /* Flag bits for the struct tic80_opcode flags field. */
    253 
    254 #define TIC80_VECTOR		01	/* Is a vector instruction */
    255 #define TIC80_NO_R0_DEST	02	/* Register r0 cannot be a destination register */
    256 
    257 
    258 /* The opcodes library contains a table that allows translation from predefined
    260    symbol names to numeric values, and vice versa. */
    261 
    262 /* Structure to hold information about predefined symbols.  */
    263 
    264 struct predefined_symbol
    265 {
    266   char *name;		/* name to recognize */
    267   int value;
    268 };
    269 
    270 #define PDS_NAME(pdsp) ((pdsp) -> name)
    271 #define PDS_VALUE(pdsp) ((pdsp) -> value)
    272 
    273 /* Translation array.  */
    274 extern const struct predefined_symbol tic80_predefined_symbols[];
    275 /* How many members in the array.  */
    276 extern const int tic80_num_predefined_symbols;
    277 
    278 /* Translate value to symbolic name.  */
    279 const char *tic80_value_to_symbol (int val, int class);
    280 
    281 /* Translate symbolic name to value.  */
    282 int tic80_symbol_to_value (char *name, int class);
    283 
    284 const struct predefined_symbol *tic80_next_predefined_symbol
    285   (const struct predefined_symbol *);
    286 
    287 #endif /* TIC80_H */
    288