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      1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "MCTargetDesc/MipsBaseInfo.h"
     11 #include "MipsInstrInfo.h"
     12 #include "MipsMachineFunction.h"
     13 #include "MipsSubtarget.h"
     14 #include "MipsTargetMachine.h"
     15 #include "llvm/CodeGen/MachineInstrBuilder.h"
     16 #include "llvm/CodeGen/MachineRegisterInfo.h"
     17 #include "llvm/IR/Function.h"
     18 #include "llvm/Support/CommandLine.h"
     19 #include "llvm/Support/raw_ostream.h"
     20 
     21 using namespace llvm;
     22 
     23 static cl::opt<bool>
     24 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
     25                  cl::desc("Always use $gp as the global base register."));
     26 
     27 MipsFunctionInfo::~MipsFunctionInfo() {}
     28 
     29 bool MipsFunctionInfo::globalBaseRegSet() const {
     30   return GlobalBaseReg;
     31 }
     32 
     33 unsigned MipsFunctionInfo::getGlobalBaseReg() {
     34   // Return if it has already been initialized.
     35   if (GlobalBaseReg)
     36     return GlobalBaseReg;
     37 
     38   MipsSubtarget const &STI =
     39       static_cast<const MipsSubtarget &>(MF.getSubtarget());
     40 
     41   const TargetRegisterClass *RC =
     42       STI.inMips16Mode()
     43           ? &Mips::CPU16RegsRegClass
     44           : STI.inMicroMipsMode()
     45                 ? STI.hasMips64()
     46                       ? &Mips::GPRMM16_64RegClass
     47                       : &Mips::GPRMM16RegClass
     48                 : static_cast<const MipsTargetMachine &>(MF.getTarget())
     49                           .getABI()
     50                           .IsN64()
     51                       ? &Mips::GPR64RegClass
     52                       : &Mips::GPR32RegClass;
     53   return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
     54 }
     55 
     56 void MipsFunctionInfo::createEhDataRegsFI() {
     57   for (int I = 0; I < 4; ++I) {
     58     const TargetRegisterClass *RC =
     59         static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
     60             ? &Mips::GPR64RegClass
     61             : &Mips::GPR32RegClass;
     62 
     63     EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
     64         RC->getAlignment(), false);
     65   }
     66 }
     67 
     68 void MipsFunctionInfo::createISRRegFI() {
     69   // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
     70   // The current implementation only supports Mips32r2+ not Mips64rX. Status
     71   // is always 32 bits, ErrorPC is 32 or 64 bits dependant on architecture,
     72   // however Mips32r2+ is the supported architecture.
     73   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
     74 
     75   for (int I = 0; I < 2; ++I)
     76     ISRDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(
     77         RC->getSize(), RC->getAlignment(), false);
     78 }
     79 
     80 bool MipsFunctionInfo::isEhDataRegFI(int FI) const {
     81   return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
     82                         || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
     83 }
     84 
     85 bool MipsFunctionInfo::isISRRegFI(int FI) const {
     86   return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
     87 }
     88 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) {
     89   return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES));
     90 }
     91 
     92 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) {
     93   return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV));
     94 }
     95 
     96 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
     97   if (MoveF64ViaSpillFI == -1) {
     98     MoveF64ViaSpillFI = MF.getFrameInfo()->CreateStackObject(
     99         RC->getSize(), RC->getAlignment(), false);
    100   }
    101   return MoveF64ViaSpillFI;
    102 }
    103 
    104 void MipsFunctionInfo::anchor() { }
    105