1 /* 2 * Copyright 2010 Jerome Glisse <glisse (at) freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include "r600_pipe.h" 24 #include "r600_opcodes.h" 25 #include "r600_shader.h" 26 27 #include "util/u_memory.h" 28 #include "eg_sq.h" 29 #include <errno.h> 30 31 int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf) 32 { 33 unsigned id = cf->id; 34 35 if (cf->op == CF_NATIVE) { 36 bc->bytecode[id++] = cf->isa[0]; 37 bc->bytecode[id++] = cf->isa[1]; 38 } else { 39 const struct cf_op_info *cfop = r600_isa_cf(cf->op); 40 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op); 41 if (cfop->flags & CF_ALU) { /* ALU clauses */ 42 43 /* prepend ALU_EXTENDED if we need more than 2 kcache sets */ 44 if (cf->eg_alu_extended) { 45 bc->bytecode[id++] = 46 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE0(cf->kcache[0].index_mode) | 47 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE1(cf->kcache[1].index_mode) | 48 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE2(cf->kcache[2].index_mode) | 49 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK_INDEX_MODE3(cf->kcache[3].index_mode) | 50 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK2(cf->kcache[2].bank) | 51 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK3(cf->kcache[3].bank) | 52 S_SQ_CF_ALU_WORD0_EXT_KCACHE_MODE2(cf->kcache[2].mode); 53 bc->bytecode[id++] = 54 S_SQ_CF_ALU_WORD1_EXT_CF_INST( 55 r600_isa_cf_opcode(bc->isa->hw_class, CF_OP_ALU_EXT)) | 56 S_SQ_CF_ALU_WORD1_EXT_KCACHE_MODE3(cf->kcache[3].mode) | 57 S_SQ_CF_ALU_WORD1_EXT_KCACHE_ADDR2(cf->kcache[2].addr) | 58 S_SQ_CF_ALU_WORD1_EXT_KCACHE_ADDR3(cf->kcache[3].addr) | 59 S_SQ_CF_ALU_WORD1_EXT_BARRIER(1); 60 } 61 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) | 62 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) | 63 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) | 64 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank); 65 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) | 66 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) | 67 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) | 68 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) | 69 S_SQ_CF_ALU_WORD1_BARRIER(1) | 70 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1); 71 } else if (cfop->flags & CF_CLAUSE) { 72 /* CF_TEX/VTX (CF_ALU already handled above) */ 73 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1); 74 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) | 75 S_SQ_CF_WORD1_BARRIER(1) | 76 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1); 77 } else if (cfop->flags & CF_EXP) { 78 /* EXPORT instructions */ 79 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) | 80 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) | 81 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) | 82 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) | 83 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr); 84 bc->bytecode[id] = 85 S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) | 86 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) | 87 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) | 88 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) | 89 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) | 90 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) | 91 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode); 92 93 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ 94 bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); 95 id++; 96 } else if (cfop->flags & CF_MEM) { 97 /* MEM_STREAM, MEM_RING instructions */ 98 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) | 99 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) | 100 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) | 101 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) | 102 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr); 103 bc->bytecode[id] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) | 104 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) | 105 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) | 106 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask) | 107 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size); 108 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ 109 bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program); 110 id++; 111 } else { 112 /* other instructions */ 113 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1); 114 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode)| 115 S_SQ_CF_WORD1_BARRIER(1) | 116 S_SQ_CF_WORD1_COND(cf->cond) | 117 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) | 118 S_SQ_CF_WORD1_COUNT(cf->count) | 119 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program); 120 } 121 } 122 return 0; 123 } 124 125 #if 0 126 void eg_bytecode_export_read(struct r600_bytecode *bc, 127 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1) 128 { 129 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0); 130 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0); 131 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0); 132 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0); 133 134 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1); 135 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1); 136 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1); 137 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1); 138 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1); 139 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1); 140 output->op = r600_isa_cf_by_opcode(bc->isa, 141 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), /* is_cf_alu = */ 0 ); 142 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1); 143 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1); 144 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1); 145 } 146 #endif 147 148 int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_clause) 149 { 150 struct r600_bytecode_alu alu; 151 int r; 152 unsigned type; 153 154 assert(id < 2); 155 assert(bc->chip_class >= EVERGREEN); 156 157 if (bc->index_loaded[id]) 158 return 0; 159 160 memset(&alu, 0, sizeof(alu)); 161 alu.op = ALU_OP1_MOVA_INT; 162 alu.src[0].sel = bc->index_reg[id]; 163 alu.src[0].chan = 0; 164 if (bc->chip_class == CAYMAN) 165 alu.dst.sel = id == 0 ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1; 166 167 alu.last = 1; 168 r = r600_bytecode_add_alu(bc, &alu); 169 if (r) 170 return r; 171 172 bc->ar_loaded = 0; /* clobbered */ 173 174 if (bc->chip_class == EVERGREEN) { 175 memset(&alu, 0, sizeof(alu)); 176 alu.op = id == 0 ? ALU_OP0_SET_CF_IDX0 : ALU_OP0_SET_CF_IDX1; 177 alu.last = 1; 178 r = r600_bytecode_add_alu(bc, &alu); 179 if (r) 180 return r; 181 } 182 183 /* Must split ALU group as index only applies to following group */ 184 if (inside_alu_clause) { 185 type = bc->cf_last->op; 186 if ((r = r600_bytecode_add_cf(bc))) { 187 return r; 188 } 189 bc->cf_last->op = type; 190 } 191 192 bc->index_loaded[id] = 1; 193 194 return 0; 195 } 196 197 int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds *gds, unsigned id) 198 { 199 unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, gds->op) >> 8; 200 bc->bytecode[id++] = S_SQ_MEM_GDS_WORD0_MEM_INST(2) | 201 S_SQ_MEM_GDS_WORD0_MEM_OP(opcode) | 202 S_SQ_MEM_GDS_WORD0_SRC_GPR(gds->src_gpr) | 203 S_SQ_MEM_GDS_WORD0_SRC_REL(gds->src_rel) | 204 S_SQ_MEM_GDS_WORD0_SRC_SEL_X(gds->src_sel_x) | 205 S_SQ_MEM_GDS_WORD0_SRC_SEL_Y(gds->src_sel_y) | 206 S_SQ_MEM_GDS_WORD0_SRC_SEL_Z(gds->src_sel_z); 207 208 bc->bytecode[id++] = S_SQ_MEM_GDS_WORD1_DST_GPR(gds->dst_gpr) | 209 S_SQ_MEM_GDS_WORD1_DST_REL(gds->dst_rel) | 210 S_SQ_MEM_GDS_WORD1_GDS_OP(gds->gds_op) | 211 S_SQ_MEM_GDS_WORD1_SRC_GPR(gds->src_gpr2); 212 213 bc->bytecode[id++] = S_SQ_MEM_GDS_WORD2_DST_SEL_X(gds->dst_sel_x) | 214 S_SQ_MEM_GDS_WORD2_DST_SEL_Y(gds->dst_sel_y) | 215 S_SQ_MEM_GDS_WORD2_DST_SEL_Z(gds->dst_sel_z) | 216 S_SQ_MEM_GDS_WORD2_DST_SEL_W(gds->dst_sel_w); 217 return 0; 218 } 219 220 int eg_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id) 221 { 222 if (alu->is_lds_idx_op) { 223 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs); 224 assert(!alu->src[0].neg && !alu->src[1].neg && !alu->src[2].neg); 225 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | 226 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) | 227 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | 228 S_SQ_ALU_WORD0_LDS_IDX_OP_IDX_OFFSET_4(alu->lds_idx >> 4) | 229 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | 230 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) | 231 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | 232 S_SQ_ALU_WORD0_LDS_IDX_OP_IDX_OFFSET_5(alu->lds_idx >> 5) | 233 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) | 234 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) | 235 S_SQ_ALU_WORD0_LAST(alu->last); 236 } else { 237 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | 238 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) | 239 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | 240 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | 241 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | 242 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) | 243 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | 244 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | 245 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) | 246 S_SQ_ALU_WORD0_LAST(alu->last); 247 } 248 249 /* don't replace gpr by pv or ps for destination register */ 250 if (alu->is_lds_idx_op) { 251 unsigned lds_op = r600_isa_alu_opcode(bc->isa->hw_class, alu->op); 252 bc->bytecode[id++] = 253 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) | 254 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) | 255 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | 256 S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_1(alu->lds_idx >> 1) | 257 258 S_SQ_ALU_WORD1_OP3_ALU_INST(lds_op & 0xff) | 259 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | 260 S_SQ_ALU_WORD1_LDS_IDX_OP_LDS_OP((lds_op >> 8) & 0xff) | 261 S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_0(alu->lds_idx) | 262 S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_2(alu->lds_idx >> 2) | 263 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | 264 S_SQ_ALU_WORD1_LDS_IDX_OP_IDX_OFFSET_3(alu->lds_idx >> 3); 265 266 } else if (alu->is_op3) { 267 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs); 268 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | 269 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | 270 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | 271 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | 272 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) | 273 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) | 274 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) | 275 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) | 276 S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) | 277 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); 278 } else { 279 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) | 280 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) | 281 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) | 282 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) | 283 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) | 284 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) | 285 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) | 286 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) | 287 S_SQ_ALU_WORD1_OP2_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) | 288 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | 289 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) | 290 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred); 291 } 292 return 0; 293 } 294
