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      1 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the Hexagon specific subclass of TargetSubtarget.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "HexagonSubtarget.h"
     15 #include "Hexagon.h"
     16 #include "HexagonRegisterInfo.h"
     17 #include "llvm/Support/CommandLine.h"
     18 #include "llvm/Support/ErrorHandling.h"
     19 #include <map>
     20 
     21 using namespace llvm;
     22 
     23 #define DEBUG_TYPE "hexagon-subtarget"
     24 
     25 #define GET_SUBTARGETINFO_CTOR
     26 #define GET_SUBTARGETINFO_TARGET_DESC
     27 #include "HexagonGenSubtargetInfo.inc"
     28 
     29 static cl::opt<bool> EnableMemOps("enable-hexagon-memops",
     30   cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
     31   cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
     32 
     33 static cl::opt<bool> DisableMemOps("disable-hexagon-memops",
     34   cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
     35   cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
     36 
     37 static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
     38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
     39   cl::desc("Generate non-chopped conversion from fp to int."));
     40 
     41 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
     42   cl::Hidden, cl::ZeroOrMore, cl::init(true));
     43 
     44 static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
     45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
     46   cl::desc("Enable Hexagon Double Vector eXtensions"));
     47 
     48 static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
     49   cl::Hidden, cl::ZeroOrMore, cl::init(false),
     50   cl::desc("Enable Hexagon Vector eXtensions"));
     51 
     52 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
     53   cl::Hidden, cl::ZeroOrMore, cl::init(false),
     54   cl::desc("Disable Hexagon MI Scheduling"));
     55 
     56 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
     57   cl::Hidden, cl::ZeroOrMore, cl::init(false),
     58   cl::desc("Enable subregister liveness tracking for Hexagon"));
     59 
     60 void HexagonSubtarget::initializeEnvironment() {
     61   UseMemOps = false;
     62   ModeIEEERndNear = false;
     63   UseBSBScheduling = false;
     64 }
     65 
     66 HexagonSubtarget &
     67 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
     68   CPUString = HEXAGON_MC::selectHexagonCPU(getTargetTriple(), CPU);
     69 
     70   static std::map<StringRef, HexagonArchEnum> CpuTable {
     71     { "hexagonv4", V4 },
     72     { "hexagonv5", V5 },
     73     { "hexagonv55", V55 },
     74     { "hexagonv60", V60 },
     75   };
     76 
     77   auto foundIt = CpuTable.find(CPUString);
     78   if (foundIt != CpuTable.end())
     79     HexagonArchVersion = foundIt->second;
     80   else
     81     llvm_unreachable("Unrecognized Hexagon processor version");
     82 
     83   UseHVXOps = false;
     84   UseHVXDblOps = false;
     85   ParseSubtargetFeatures(CPUString, FS);
     86 
     87   if (EnableHexagonHVX.getPosition())
     88     UseHVXOps = EnableHexagonHVX;
     89   if (EnableHexagonHVXDouble.getPosition())
     90     UseHVXDblOps = EnableHexagonHVXDouble;
     91 
     92   return *this;
     93 }
     94 
     95 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
     96                                    StringRef FS, const TargetMachine &TM)
     97     : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
     98       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
     99       FrameLowering() {
    100 
    101   initializeEnvironment();
    102 
    103   // Initialize scheduling itinerary for the specified CPU.
    104   InstrItins = getInstrItineraryForCPU(CPUString);
    105 
    106   // UseMemOps on by default unless disabled explicitly
    107   if (DisableMemOps)
    108     UseMemOps = false;
    109   else if (EnableMemOps)
    110     UseMemOps = true;
    111   else
    112     UseMemOps = false;
    113 
    114   if (EnableIEEERndNear)
    115     ModeIEEERndNear = true;
    116   else
    117     ModeIEEERndNear = false;
    118 
    119   UseBSBScheduling = hasV60TOps() && EnableBSBSched;
    120 }
    121 
    122 // Pin the vtable to this file.
    123 void HexagonSubtarget::anchor() {}
    124 
    125 bool HexagonSubtarget::enableMachineScheduler() const {
    126   if (DisableHexagonMISched.getNumOccurrences())
    127     return !DisableHexagonMISched;
    128   return true;
    129 }
    130 
    131 bool HexagonSubtarget::enableSubRegLiveness() const {
    132   return EnableSubregLiveness;
    133 }
    134 
    135