1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 /*****************************************************************************/ 21 /* */ 22 /* File Name : decoder_api_main.c */ 23 /* */ 24 /* Description : Functions which recieve the API call from user */ 25 /* */ 26 /* List of Functions : <List the functions defined in this file> */ 27 /* */ 28 /* Issues / Problems : None */ 29 /* */ 30 /* Revision History : */ 31 /* */ 32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 33 /* 30 05 2007 Rajneesh Creation */ 34 /* */ 35 /*****************************************************************************/ 36 37 /*****************************************************************************/ 38 /* File Includes */ 39 /*****************************************************************************/ 40 41 /* System include files */ 42 #include <stdio.h> 43 #include <stdlib.h> 44 #include <stddef.h> 45 #include <string.h> 46 47 /* User include files */ 48 #include "iv_datatypedef.h" 49 #include "iv.h" 50 #include "ivd.h" 51 #include "ithread.h" 52 53 #include "impeg2_job_queue.h" 54 #include "impeg2_macros.h" 55 #include "impeg2_buf_mgr.h" 56 #include "impeg2_disp_mgr.h" 57 #include "impeg2_defs.h" 58 #include "impeg2_platform_macros.h" 59 #include "impeg2_inter_pred.h" 60 #include "impeg2_idct.h" 61 #include "impeg2_format_conv.h" 62 #include "impeg2_mem_func.h" 63 64 #include "impeg2d.h" 65 #include "impeg2d_api.h" 66 #include "impeg2d_bitstream.h" 67 #include "impeg2d_debug.h" 68 #include "impeg2d_structs.h" 69 #include "impeg2d_mc.h" 70 #include "impeg2d_pic_proc.h" 71 #include "impeg2d_deinterlace.h" 72 73 #define NUM_FRAMES_LIMIT_ENABLED 0 74 75 #ifdef LOGO_EN 76 #include "impeg2_ittiam_logo.h" 77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht); 78 #else 79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) 80 #endif 81 82 #if NUM_FRAMES_LIMIT_ENABLED 83 #define NUM_FRAMES_LIMIT 10000 84 #else 85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF 86 #endif 87 88 #define CODEC_NAME "MPEG2VDEC" 89 #define CODEC_RELEASE_TYPE "eval" 90 #define CODEC_RELEASE_VER "01.00" 91 #define CODEC_VENDOR "ITTIAM" 92 93 #ifdef __ANDROID__ 94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 95 strcpy(version_string,"@(#)Id:"); \ 96 strcat(version_string,codec_name); \ 97 strcat(version_string,"_"); \ 98 strcat(version_string,codec_release_type); \ 99 strcat(version_string," Ver:"); \ 100 strcat(version_string,codec_release_ver); \ 101 strcat(version_string," Released by "); \ 102 strcat(version_string,codec_vendor); 103 #else 104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 105 strcpy(version_string,"@(#)Id:"); \ 106 strcat(version_string,codec_name); \ 107 strcat(version_string,"_"); \ 108 strcat(version_string,codec_release_type); \ 109 strcat(version_string," Ver:"); \ 110 strcat(version_string,codec_release_ver); \ 111 strcat(version_string," Released by "); \ 112 strcat(version_string,codec_vendor); \ 113 strcat(version_string," Build: "); \ 114 strcat(version_string,__DATE__); \ 115 strcat(version_string," @ "); \ 116 strcat(version_string,__TIME__); 117 #endif 118 119 120 #define MIN_OUT_BUFS_420 3 121 #define MIN_OUT_BUFS_422ILE 1 122 #define MIN_OUT_BUFS_RGB565 1 123 #define MIN_OUT_BUFS_420SP 2 124 125 126 void impeg2d_init_arch(void *pv_codec); 127 void impeg2d_init_function_ptr(void *pv_codec); 128 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size); 129 130 /*****************************************************************************/ 131 /* */ 132 /* Function Name : impeg2d_api_rel_display_frame */ 133 /* */ 134 /* Description : Release displ buffers that will be shared between decoder */ 135 /* and application */ 136 /* Inputs : Error message */ 137 /* Globals : None */ 138 /* Processing : Just prints error message to console */ 139 /* Outputs : Error mesage to the console */ 140 /* Returns : None */ 141 /* */ 142 /* Issues : <List any issues or problems with this function> */ 143 /* */ 144 /* Revision History: */ 145 /* */ 146 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 147 /* 27 05 2006 Sankar Creation */ 148 /* */ 149 /*****************************************************************************/ 150 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl, 151 void *pv_api_ip, 152 void *pv_api_op) 153 { 154 155 ivd_rel_display_frame_ip_t *dec_rel_disp_ip; 156 ivd_rel_display_frame_op_t *dec_rel_disp_op; 157 158 dec_state_t *ps_dec_state; 159 dec_state_multi_core_t *ps_dec_state_multi_core; 160 161 162 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 163 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op; 164 165 dec_rel_disp_op->u4_error_code = 0; 166 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 167 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 168 169 170 /* If not in shared disp buf mode, return */ 171 if(0 == ps_dec_state->u4_share_disp_buf) 172 return IV_SUCCESS; 173 174 if(NULL == ps_dec_state->pv_pic_buf_mg) 175 return IV_SUCCESS; 176 177 178 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP); 179 180 return IV_SUCCESS; 181 } 182 183 /*****************************************************************************/ 184 /* */ 185 /* Function Name : impeg2d_api_set_display_frame */ 186 /* */ 187 /* Description : Sets display buffers that will be shared between decoder */ 188 /* and application */ 189 /* Inputs : Error message */ 190 /* Globals : None */ 191 /* Processing : Just prints error message to console */ 192 /* Outputs : Error mesage to the console */ 193 /* Returns : None */ 194 /* */ 195 /* Issues : <List any issues or problems with this function> */ 196 /* */ 197 /* Revision History: */ 198 /* */ 199 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 200 /* 27 05 2006 Sankar Creation */ 201 /* */ 202 /*****************************************************************************/ 203 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl, 204 void *pv_api_ip, 205 void *pv_api_op) 206 { 207 208 ivd_set_display_frame_ip_t *dec_disp_ip; 209 ivd_set_display_frame_op_t *dec_disp_op; 210 211 UWORD32 i; 212 dec_state_t *ps_dec_state; 213 dec_state_multi_core_t *ps_dec_state_multi_core; 214 UWORD32 u4_num_disp_bufs; 215 UWORD32 u4_disp_buf_size[3]; 216 UWORD32 num_bufs; 217 218 219 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 220 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 221 dec_disp_op->u4_error_code = 0; 222 223 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs; 224 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT) 225 u4_num_disp_bufs = BUF_MGR_MAX_CNT; 226 227 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 228 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 229 230 num_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs; 231 232 if(ps_dec_state->u4_share_disp_buf) 233 { 234 pic_buf_t *ps_pic_buf; 235 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base; 236 237 /* Get the sizes of the first buffer structure. Compare this with the 238 * rest to make sure all the buffers are of the same size. 239 */ 240 u4_disp_buf_size[0] = 241 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0]; 242 u4_disp_buf_size[1] = 243 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1]; 244 u4_disp_buf_size[2] = 245 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2]; 246 for(i = 0; i < u4_num_disp_bufs; i++) 247 { 248 /* Verify all buffer structures have the same sized buffers as the 249 * first buffer structure*/ 250 if ((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0] 251 != u4_disp_buf_size[0]) 252 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1] 253 != u4_disp_buf_size[1]) 254 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2] 255 != u4_disp_buf_size[2])) 256 { 257 return IV_FAIL; 258 } 259 /* Verify all buffer structures have the same number of 260 * buffers (e.g. y, u, v) */ 261 if (dec_disp_ip->s_disp_buffer[i].u4_num_bufs != num_bufs) 262 { 263 return IV_FAIL; 264 } 265 266 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 267 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat) 268 { 269 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 270 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 271 } 272 else 273 { 274 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i]; 275 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] + 276 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2); 277 } 278 279 ps_pic_buf->i4_buf_id = i; 280 281 ps_pic_buf->u1_used_as_ref = 0; 282 283 ps_pic_buf->u4_ts = 0; 284 285 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i); 286 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP); 287 ps_pic_buf++; 288 289 } 290 } 291 memcpy(&(ps_dec_state->as_disp_buffers[0]), 292 &(dec_disp_ip->s_disp_buffer), 293 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t)); 294 295 return IV_SUCCESS; 296 297 } 298 299 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl, 300 void *pv_api_ip, 301 void *pv_api_op) 302 { 303 impeg2d_ctl_set_num_cores_ip_t *ps_ip; 304 impeg2d_ctl_set_num_cores_op_t *ps_op; 305 dec_state_t *ps_dec_state; 306 dec_state_multi_core_t *ps_dec_state_multi_core; 307 308 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip; 309 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op; 310 311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 312 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 313 314 if(ps_ip->u4_num_cores > 0) 315 { 316 317 318 WORD32 i; 319 for(i = 0; i < MAX_THREADS; i++) 320 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores; 321 } 322 else 323 { 324 ps_dec_state->i4_num_cores = 1; 325 } 326 ps_op->u4_error_code = IV_SUCCESS; 327 328 return IV_SUCCESS; 329 } 330 331 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl, 332 void *pv_api_ip, 333 void *pv_api_op) 334 { 335 impeg2d_ctl_get_seq_info_ip_t *ps_ip; 336 impeg2d_ctl_get_seq_info_op_t *ps_op; 337 dec_state_t *ps_codec; 338 dec_state_multi_core_t *ps_dec_state_multi_core; 339 340 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip; 341 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op; 342 343 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 344 ps_codec = ps_dec_state_multi_core->ps_dec_state[0]; 345 UNUSED(ps_ip); 346 if(ps_codec->u2_header_done == 1) 347 { 348 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info; 349 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code; 350 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n; 351 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d; 352 if(ps_codec->u1_seq_disp_extn_present == 1) 353 { 354 ps_op->u1_video_format = ps_codec->u1_video_format; 355 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries; 356 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics; 357 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients; 358 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size; 359 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size; 360 } 361 else 362 { 363 ps_op->u1_video_format = 5; 364 ps_op->u1_colour_primaries = 2; 365 ps_op->u1_transfer_characteristics = 2; 366 ps_op->u1_matrix_coefficients = 2; 367 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size; 368 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size; 369 } 370 ps_op->u4_error_code = IV_SUCCESS; 371 return IV_SUCCESS; 372 } 373 else 374 { 375 ps_op->u4_error_code = IV_FAIL; 376 return IV_FAIL; 377 } 378 } 379 380 /** 381 ******************************************************************************* 382 * 383 * @brief 384 * Sets Processor type 385 * 386 * @par Description: 387 * Sets Processor type 388 * 389 * @param[in] ps_codec_obj 390 * Pointer to codec object at API level 391 * 392 * @param[in] pv_api_ip 393 * Pointer to input argument structure 394 * 395 * @param[out] pv_api_op 396 * Pointer to output argument structure 397 * 398 * @returns Status 399 * 400 * @remarks 401 * 402 * 403 ******************************************************************************* 404 */ 405 406 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj, 407 void *pv_api_ip, 408 void *pv_api_op) 409 { 410 impeg2d_ctl_set_processor_ip_t *ps_ip; 411 impeg2d_ctl_set_processor_op_t *ps_op; 412 dec_state_t *ps_codec; 413 dec_state_multi_core_t *ps_dec_state_multi_core; 414 415 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle); 416 ps_codec = ps_dec_state_multi_core->ps_dec_state[0]; 417 418 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip; 419 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op; 420 421 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 422 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 423 424 impeg2d_init_function_ptr(ps_codec); 425 426 427 ps_op->u4_error_code = 0; 428 return IV_SUCCESS; 429 } 430 /*****************************************************************************/ 431 /* */ 432 /* Function Name : impeg2d_fill_mem_rec */ 433 /* */ 434 /* Description : */ 435 /* Inputs : */ 436 /* Globals : */ 437 /* Processing : */ 438 /* Outputs : */ 439 /* Returns : */ 440 /* */ 441 /* Issues : */ 442 /* */ 443 /* Revision History: */ 444 /* */ 445 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 446 /* 17 09 2007 Rajendra C Y Draft */ 447 /* */ 448 /*****************************************************************************/ 449 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip, 450 impeg2d_fill_mem_rec_op_t *ps_op) 451 { 452 UWORD32 u4_i; 453 454 UWORD8 u1_no_rec = 0; 455 UWORD32 max_frm_width,max_frm_height,max_frm_size; 456 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 457 WORD32 i4_num_threads; 458 WORD32 i4_share_disp_buf, i4_chroma_format; 459 WORD32 i4_chroma_size; 460 UWORD32 u4_deinterlace; 461 UNUSED(u4_deinterlace); 462 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd); 463 /* In error clips with field prediction, the mv may incorrectly refer to 464 * the last MB row, causing an out of bounds read access. Allocating 8 extra 465 * rows to handle this. Adding another extra row to handle half_y prediction. 466 */ 467 max_frm_height = ALIGN32(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht) + 9; 468 469 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */ 470 471 i4_chroma_size = max_frm_width * max_frm_height / 4; 472 473 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf)) 474 { 475 #ifndef LOGO_EN 476 i4_share_disp_buf = ps_ip->u4_share_disp_buf; 477 #else 478 i4_share_disp_buf = 0; 479 #endif 480 } 481 else 482 { 483 i4_share_disp_buf = 0; 484 } 485 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format)) 486 { 487 i4_chroma_format = ps_ip->e_output_format; 488 } 489 else 490 { 491 i4_chroma_format = -1; 492 } 493 494 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace)) 495 { 496 u4_deinterlace = ps_ip->u4_deinterlace; 497 } 498 else 499 { 500 u4_deinterlace = 0; 501 } 502 503 504 if( (i4_chroma_format != IV_YUV_420P) && 505 (i4_chroma_format != IV_YUV_420SP_UV) && 506 (i4_chroma_format != IV_YUV_420SP_VU)) 507 { 508 i4_share_disp_buf = 0; 509 } 510 511 /* Disable deinterlacer in shared mode */ 512 if(i4_share_disp_buf) 513 { 514 u4_deinterlace = 0; 515 } 516 517 /*************************************************************************/ 518 /* Fill the memory requirement XDM Handle */ 519 /*************************************************************************/ 520 /* ! */ 521 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 522 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 523 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t); 524 525 ps_mem_rec++; 526 u1_no_rec++; 527 528 { 529 /*************************************************************************/ 530 /* Fill the memory requirement for threads context */ 531 /*************************************************************************/ 532 /* ! */ 533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 535 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t); 536 537 ps_mem_rec++; 538 u1_no_rec++; 539 } 540 541 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 542 { 543 /*************************************************************************/ 544 /* Fill the memory requirement for MPEG2 Decoder Context */ 545 /*************************************************************************/ 546 /* ! */ 547 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 548 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 549 ps_mem_rec->u4_mem_size = sizeof(dec_state_t); 550 551 ps_mem_rec++; 552 u1_no_rec++; 553 554 /* To store thread handle */ 555 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 556 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 557 ps_mem_rec->u4_mem_size = ithread_get_handle_size(); 558 559 ps_mem_rec++; 560 u1_no_rec++; 561 562 /*************************************************************************/ 563 /* Fill the memory requirement for Motion Compensation Buffers */ 564 /*************************************************************************/ 565 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 566 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM; 567 568 /* for mc_fw_buf.pu1_y */ 569 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE; 570 571 /* for mc_fw_buf.pu1_u */ 572 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 573 574 /* for mc_fw_buf.pu1_v */ 575 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 576 577 /* for mc_bk_buf.pu1_y */ 578 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE; 579 580 /* for mc_bk_buf.pu1_u */ 581 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 582 583 /* for mc_bk_buf.pu1_v */ 584 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 585 586 /* for mc_buf.pu1_y */ 587 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE; 588 589 /* for mc_buf.pu1_u */ 590 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 591 592 /* for mc_buf.pu1_v */ 593 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE; 594 595 ps_mem_rec++; 596 u1_no_rec++; 597 598 599 /*************************************************************************/ 600 /* Fill the memory requirement Stack Context */ 601 /*************************************************************************/ 602 /* ! */ 603 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 604 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 605 ps_mem_rec->u4_mem_size = 392; 606 607 ps_mem_rec++; 608 u1_no_rec++; 609 } 610 611 612 613 { 614 /*************************************************************************/ 615 /* Fill the memory requirement for Picture Buffer Manager */ 616 /*************************************************************************/ 617 /* ! */ 618 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 619 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 620 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT; 621 622 ps_mem_rec++; 623 u1_no_rec++; 624 } 625 /*************************************************************************/ 626 /* Internal Frame Buffers */ 627 /*************************************************************************/ 628 /* ! */ 629 630 { 631 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++) 632 { 633 /* ! */ 634 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/; 635 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 636 if(0 == i4_share_disp_buf) 637 ps_mem_rec->u4_mem_size = max_frm_size; 638 else if(IV_YUV_420P != i4_chroma_format) 639 { 640 /* If color format is not 420P and it is shared, then allocate for chroma */ 641 ps_mem_rec->u4_mem_size = i4_chroma_size * 2; 642 } 643 else 644 ps_mem_rec->u4_mem_size = 64; 645 ps_mem_rec++; 646 u1_no_rec++; 647 } 648 } 649 650 ps_mem_rec->u4_mem_alignment = 128; 651 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 652 ps_mem_rec->u4_mem_size = MAX_BITSTREAM_BUFFER_SIZE + MIN_BUFFER_BYTES_AT_EOS; 653 ps_mem_rec++; 654 u1_no_rec++; 655 656 { 657 WORD32 i4_job_queue_size; 658 WORD32 i4_num_jobs; 659 660 /* One job per row of MBs */ 661 i4_num_jobs = max_frm_height >> 4; 662 663 /* One format convert/frame copy job per row of MBs for non-shared mode*/ 664 i4_num_jobs += max_frm_height >> 4; 665 666 667 i4_job_queue_size = impeg2_jobq_ctxt_size(); 668 i4_job_queue_size += i4_num_jobs * sizeof(job_t); 669 ps_mem_rec->u4_mem_size = i4_job_queue_size; 670 ps_mem_rec->u4_mem_alignment = 128; 671 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 672 673 ps_mem_rec++; 674 u1_no_rec++; 675 676 } 677 678 ps_mem_rec->u4_mem_alignment = 128; 679 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 680 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size(); 681 ps_mem_rec++; 682 u1_no_rec++; 683 684 ps_mem_rec->u4_mem_alignment = 128; 685 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 686 687 if(IV_YUV_420P != i4_chroma_format) 688 ps_mem_rec->u4_mem_size = max_frm_size; 689 else 690 ps_mem_rec->u4_mem_size = 64; 691 692 ps_mem_rec++; 693 u1_no_rec++; 694 695 ps_mem_rec->u4_mem_alignment = 128; 696 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 697 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS); 698 ps_mem_rec++; 699 u1_no_rec++; 700 701 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec; 702 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0; 703 } 704 705 706 /*****************************************************************************/ 707 /* */ 708 /* Function Name : impeg2d_api_get_version */ 709 /* */ 710 /* Description : */ 711 /* */ 712 /* Inputs : */ 713 /* Globals : <Does it use any global variables?> */ 714 /* Outputs : */ 715 /* Returns : void */ 716 /* */ 717 /* Issues : none */ 718 /* */ 719 /* Revision History: */ 720 /* */ 721 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 722 /* 22 10 2008 100356 Draft */ 723 /* */ 724 /*****************************************************************************/ 725 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl, 726 void *pv_api_ip, 727 void *pv_api_op) 728 { 729 char au1_version_string[512]; 730 731 impeg2d_ctl_getversioninfo_ip_t *ps_ip; 732 impeg2d_ctl_getversioninfo_op_t *ps_op; 733 734 UNUSED(ps_dechdl); 735 736 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip; 737 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op; 738 739 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS; 740 741 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 742 CODEC_VENDOR); 743 744 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0) 745 { 746 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL; 747 return (IV_FAIL); 748 } 749 750 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size 751 >= (strlen(au1_version_string) + 1)) 752 { 753 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer, 754 au1_version_string, (strlen(au1_version_string) + 1)); 755 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS; 756 } 757 else 758 { 759 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL; 760 } 761 762 return (IV_SUCCESS); 763 } 764 765 /*****************************************************************************/ 766 /* */ 767 /* Function Name : impeg2d_api_get_buf_info */ 768 /* */ 769 /* Description : */ 770 /* */ 771 /* Inputs : */ 772 /* Globals : <Does it use any global variables?> */ 773 /* Outputs : */ 774 /* Returns : void */ 775 /* */ 776 /* Issues : none */ 777 /* */ 778 /* Revision History: */ 779 /* */ 780 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 781 /* 22 10 2008 100356 Draft */ 782 /* */ 783 /*****************************************************************************/ 784 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl, 785 void *pv_api_ip, 786 void *pv_api_op) 787 { 788 dec_state_t *ps_dec_state; 789 dec_state_multi_core_t *ps_dec_state_multi_core; 790 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip = 791 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip; 792 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op = 793 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op; 794 UWORD32 u4_i, u4_stride, u4_height; 795 UNUSED(ps_ctl_bufinfo_ip); 796 797 ps_dec_state_multi_core = 798 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle); 799 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 800 801 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1; 802 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1; 803 804 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++) 805 { 806 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] = 807 0; 808 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] = 809 0; 810 } 811 812 for(u4_i = 0; 813 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs; 814 u4_i++) 815 { 816 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] = 817 MAX_BITSTREAM_BUFFER_SIZE; 818 } 819 820 if (0 == ps_dec_state->u4_frm_buf_stride) 821 { 822 if (1 == ps_dec_state->u2_header_done) 823 { 824 u4_stride = ps_dec_state->u2_horizontal_size; 825 } 826 else 827 { 828 u4_stride = ps_dec_state->u2_create_max_width; 829 } 830 } 831 else 832 { 833 u4_stride = ps_dec_state->u4_frm_buf_stride; 834 } 835 u4_stride = ALIGN16(u4_stride); 836 u4_height = ALIGN32(ps_dec_state->u2_frame_height) + 9; 837 838 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 839 impeg2d_get_outbuf_size( 840 u4_stride, 841 u4_height, 842 ps_dec_state->i4_chromaFormat, 843 &ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0]); 844 845 if (0 == ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs) 846 { 847 //Invalid chroma format; Error code may be updated, verify in testing if needed 848 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 849 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 850 return IV_FAIL; 851 } 852 853 /* Adding initialization for 2 uninitialized values */ 854 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1; 855 if(ps_dec_state->u4_share_disp_buf) 856 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 857 NUM_INT_FRAME_BUFFERS; 858 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE; 859 860 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS; 861 862 return (IV_SUCCESS); 863 } 864 865 /*****************************************************************************/ 866 /* */ 867 /* Function Name : impeg2d_api_set_flush_mode */ 868 /* */ 869 /* Description : */ 870 /* */ 871 /* Inputs : */ 872 /* Globals : <Does it use any global variables?> */ 873 /* Outputs : */ 874 /* Returns : void */ 875 /* */ 876 /* Issues : none */ 877 /* */ 878 /* Revision History: */ 879 /* */ 880 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 881 /* 08 06 2009 100356 RAVI */ 882 /* */ 883 /*****************************************************************************/ 884 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl, 885 void *pv_api_ip, 886 void *pv_api_op) 887 { 888 dec_state_t *ps_dec_state; 889 dec_state_multi_core_t *ps_dec_state_multi_core; 890 impeg2d_ctl_flush_op_t *ps_ctl_dec_op = 891 (impeg2d_ctl_flush_op_t*)pv_api_op; 892 893 UNUSED(pv_api_ip); 894 895 ps_dec_state_multi_core = 896 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle); 897 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 898 899 ps_dec_state->u1_flushfrm = 1; 900 901 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size = 902 sizeof(impeg2d_ctl_flush_op_t); 903 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS; 904 905 return (IV_SUCCESS); 906 } 907 908 /*****************************************************************************/ 909 /* */ 910 /* Function Name : impeg2d_api_set_default */ 911 /* */ 912 /* Description : */ 913 /* */ 914 /* Inputs : */ 915 /* Globals : <Does it use any global variables?> */ 916 /* Outputs : */ 917 /* Returns : void */ 918 /* */ 919 /* Issues : none */ 920 /* */ 921 /* Revision History: */ 922 /* */ 923 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 924 /* 08 06 2009 100356 RAVI */ 925 /* */ 926 /*****************************************************************************/ 927 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl, 928 void *pv_api_ip, 929 void *pv_api_op) 930 { 931 dec_state_t *ps_dec_state; 932 dec_state_multi_core_t *ps_dec_state_multi_core; 933 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = 934 (impeg2d_ctl_set_config_op_t *)pv_api_op; 935 936 UNUSED(pv_api_ip); 937 938 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS; 939 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size = 940 sizeof(impeg2d_ctl_set_config_op_t); 941 942 ps_dec_state_multi_core = 943 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle); 944 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 945 946 ps_dec_state->u1_flushfrm = 0; 947 ps_dec_state->u2_decode_header = 1; 948 949 if (1 == ps_dec_state->u2_header_done) 950 { 951 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width; 952 } 953 954 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS; 955 956 return (IV_SUCCESS); 957 958 } 959 960 /*****************************************************************************/ 961 /* */ 962 /* Function Name : impeg2d_api_reset */ 963 /* */ 964 /* Description : */ 965 /* */ 966 /* Inputs : */ 967 /* Globals : <Does it use any global variables?> */ 968 /* Outputs : */ 969 /* Returns : void */ 970 /* */ 971 /* Issues : none */ 972 /* */ 973 /* Revision History: */ 974 /* */ 975 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 976 /* 08 06 2009 100356 RAVI */ 977 /* */ 978 /*****************************************************************************/ 979 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl, 980 void *pv_api_ip, 981 void *pv_api_op) 982 { 983 dec_state_t *ps_dec_state; 984 dec_state_multi_core_t *ps_dec_state_multi_core; 985 UNUSED(pv_api_ip); 986 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op; 987 988 WORD32 i4_num_threads; 989 990 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 991 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 992 993 if(ps_dec_state_multi_core != NULL) 994 { 995 if(ps_dec_state->aps_ref_pics[1] != NULL) 996 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF); 997 if(ps_dec_state->aps_ref_pics[0] != NULL) 998 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF); 999 while(1) 1000 { 1001 pic_buf_t *ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id); 1002 if(NULL == ps_disp_pic) 1003 break; 1004 if(0 == ps_dec_state->u4_share_disp_buf) 1005 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP); 1006 1007 } 1008 1009 if((ps_dec_state->u4_deinterlace) && (NULL != ps_dec_state->ps_deint_pic)) 1010 { 1011 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, 1012 ps_dec_state->ps_deint_pic->i4_buf_id, 1013 MPEG2_BUF_MGR_DEINT); 1014 } 1015 1016 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 1017 { 1018 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads]; 1019 1020 1021 /* --------------------------------------------------------------------- */ 1022 /* Initializations */ 1023 1024 ps_dec_state->u2_header_done = 0; /* Header decoding not done */ 1025 ps_dec_state->u4_frm_buf_stride = 0; 1026 ps_dec_state->i4_pic_count = 0; 1027 ps_dec_state->u2_is_mpeg2 = 0; 1028 ps_dec_state->aps_ref_pics[0] = NULL; 1029 ps_dec_state->aps_ref_pics[1] = NULL; 1030 ps_dec_state->ps_deint_pic = NULL; 1031 } 1032 } 1033 else 1034 { 1035 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code = 1036 IMPEG2D_INIT_NOT_DONE; 1037 } 1038 1039 return(IV_SUCCESS); 1040 } 1041 1042 /*****************************************************************************/ 1043 /* */ 1044 /* Function Name : impeg2d_api_set_params */ 1045 /* */ 1046 /* Description : */ 1047 /* */ 1048 /* Inputs : */ 1049 /* Globals : <Does it use any global variables?> */ 1050 /* Outputs : */ 1051 /* Returns : void */ 1052 /* */ 1053 /* Issues : none */ 1054 /* */ 1055 /* Revision History: */ 1056 /* */ 1057 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1058 /* 08 06 2009 100356 RAVI */ 1059 /* */ 1060 /*****************************************************************************/ 1061 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op) 1062 { 1063 dec_state_t *ps_dec_state; 1064 dec_state_multi_core_t *ps_dec_state_multi_core; 1065 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip; 1066 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op; 1067 1068 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 1069 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1070 1071 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME)) 1072 { 1073 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1074 return(IV_FAIL); 1075 } 1076 1077 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT)) 1078 { 1079 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1080 return(IV_FAIL); 1081 } 1082 1083 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE) 1084 { 1085 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1086 return(IV_FAIL); 1087 } 1088 1089 if(ps_dec_state->u2_header_done == 1) 1090 { 1091 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) || 1092 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width))) 1093 { 1094 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL; 1095 return(IV_FAIL); 1096 } 1097 1098 } 1099 1100 1101 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode; 1102 1103 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) 1104 { 1105 if(ps_dec_state->u2_header_done == 1) 1106 { 1107 if (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd > ps_dec_state->u2_frame_width) 1108 { 1109 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd; 1110 } 1111 } 1112 else 1113 { 1114 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd; 1115 } 1116 1117 } 1118 else 1119 { 1120 1121 if(ps_dec_state->u2_header_done == 1) 1122 { 1123 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width; 1124 } 1125 else 1126 { 1127 ps_dec_state->u4_frm_buf_stride = 0; 1128 } 1129 } 1130 1131 1132 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME) 1133 { 1134 ps_dec_state->u1_flushfrm = 0; 1135 } 1136 1137 1138 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS; 1139 return(IV_SUCCESS); 1140 1141 } 1142 1143 /*****************************************************************************/ 1144 /* */ 1145 /* Function Name : impeg2d_api_get_status */ 1146 /* */ 1147 /* Description : */ 1148 /* */ 1149 /* Inputs : */ 1150 /* Globals : <Does it use any global variables?> */ 1151 /* Outputs : */ 1152 /* Returns : void */ 1153 /* */ 1154 /* Issues : none */ 1155 /* */ 1156 /* Revision History: */ 1157 /* */ 1158 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1159 /* 08 06 2009 100356 RAVI */ 1160 /* */ 1161 /*****************************************************************************/ 1162 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl, 1163 void *pv_api_ip, 1164 void *pv_api_op) 1165 { 1166 dec_state_t *ps_dec_state; 1167 dec_state_multi_core_t *ps_dec_state_multi_core; 1168 UWORD32 u4_i,u4_stride,u4_height; 1169 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip; 1170 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op; 1171 UNUSED(ps_ctl_dec_ip); 1172 1173 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 1174 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1175 1176 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t); 1177 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1; 1178 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height; 1179 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width; 1180 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod; 1181 1182 1183 if(ps_dec_state->u2_progressive_sequence == 1) 1184 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ; 1185 else 1186 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED; 1187 1188 1189 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat; 1190 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1; 1191 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1; 1192 1193 1194 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P) 1195 { 1196 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420; 1197 } 1198 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 1199 { 1200 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 1201 } 1202 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565) 1203 { 1204 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 1205 } 1206 else 1207 { 1208 //Invalid chroma format; Error code may be updated, verify in testing if needed 1209 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 1210 return IV_FAIL; 1211 } 1212 1213 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS)); 1214 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS)); 1215 1216 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++) 1217 { 1218 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE; 1219 } 1220 1221 u4_stride = ps_dec_state->u4_frm_buf_stride; 1222 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4; 1223 1224 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P) 1225 { 1226 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height); 1227 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ; 1228 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2; 1229 } 1230 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU)) 1231 { 1232 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height); 1233 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ; 1234 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0; 1235 } 1236 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 1237 { 1238 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2; 1239 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0; 1240 } 1241 1242 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS; 1243 1244 return(IV_SUCCESS); 1245 1246 } 1247 1248 /** 1249 ******************************************************************************* 1250 * 1251 * @brief 1252 * Gets frame dimensions/offsets 1253 * 1254 * @par Description: 1255 * Gets frame buffer chararacteristics such a x & y offsets display and 1256 * buffer dimensions 1257 * 1258 * @param[in] ps_codec_obj 1259 * Pointer to codec object at API level 1260 * 1261 * @param[in] pv_api_ip 1262 * Pointer to input argument structure 1263 * 1264 * @param[out] pv_api_op 1265 * Pointer to output argument structure 1266 * 1267 * @returns Status 1268 * 1269 * @remarks 1270 * 1271 * 1272 ******************************************************************************* 1273 */ 1274 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj, 1275 void *pv_api_ip, 1276 void *pv_api_op) 1277 { 1278 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip; 1279 impeg2d_ctl_get_frame_dimensions_op_t *ps_op; 1280 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 1281 dec_state_t *ps_codec; 1282 dec_state_multi_core_t *ps_dec_state_multi_core; 1283 1284 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle); 1285 ps_codec = ps_dec_state_multi_core->ps_dec_state[0]; 1286 1287 1288 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 1289 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op; 1290 UNUSED(ps_ip); 1291 if(ps_codec->u2_header_done) 1292 { 1293 disp_wd = ps_codec->u2_horizontal_size; 1294 disp_ht = ps_codec->u2_vertical_size; 1295 1296 if(0 == ps_codec->u4_share_disp_buf) 1297 { 1298 buffer_wd = disp_wd; 1299 buffer_ht = disp_ht; 1300 } 1301 else 1302 { 1303 buffer_wd = ps_codec->u2_frame_width; 1304 buffer_ht = ps_codec->u2_frame_height; 1305 } 1306 } 1307 else 1308 { 1309 1310 disp_wd = ps_codec->u2_create_max_width; 1311 disp_ht = ps_codec->u2_create_max_height; 1312 1313 if(0 == ps_codec->u4_share_disp_buf) 1314 { 1315 buffer_wd = disp_wd; 1316 buffer_ht = disp_ht; 1317 } 1318 else 1319 { 1320 buffer_wd = ALIGN16(disp_wd); 1321 buffer_ht = ALIGN16(disp_ht); 1322 1323 } 1324 } 1325 if(ps_codec->u2_frame_width > buffer_wd) 1326 buffer_wd = ps_codec->u2_frame_width; 1327 1328 x_offset = 0; 1329 y_offset = 0; 1330 1331 1332 ps_op->u4_disp_wd[0] = disp_wd; 1333 ps_op->u4_disp_ht[0] = disp_ht; 1334 ps_op->u4_buffer_wd[0] = buffer_wd; 1335 ps_op->u4_buffer_ht[0] = buffer_ht; 1336 ps_op->u4_x_offset[0] = x_offset; 1337 ps_op->u4_y_offset[0] = y_offset; 1338 1339 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 1340 >> 1); 1341 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 1342 >> 1); 1343 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 1344 >> 1); 1345 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 1346 >> 1); 1347 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0] 1348 >> 1); 1349 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0] 1350 >> 1); 1351 1352 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV) 1353 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU)) 1354 { 1355 ps_op->u4_disp_wd[2] = 0; 1356 ps_op->u4_disp_ht[2] = 0; 1357 ps_op->u4_buffer_wd[2] = 0; 1358 ps_op->u4_buffer_ht[2] = 0; 1359 ps_op->u4_x_offset[2] = 0; 1360 ps_op->u4_y_offset[2] = 0; 1361 1362 ps_op->u4_disp_wd[1] <<= 1; 1363 ps_op->u4_buffer_wd[1] <<= 1; 1364 ps_op->u4_x_offset[1] <<= 1; 1365 } 1366 1367 return IV_SUCCESS; 1368 1369 } 1370 1371 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op) 1372 { 1373 WORD32 i4_cmd; 1374 IV_API_CALL_STATUS_T u4_error_code; 1375 UWORD32 *pu4_api_ip; 1376 1377 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op); 1378 if(IV_SUCCESS != u4_error_code) 1379 { 1380 return u4_error_code; 1381 } 1382 1383 1384 pu4_api_ip = (UWORD32 *)pv_api_ip; 1385 i4_cmd = *(pu4_api_ip + 1); 1386 1387 switch(i4_cmd) 1388 { 1389 1390 case IV_CMD_GET_NUM_MEM_REC: 1391 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op); 1392 break; 1393 1394 case IV_CMD_FILL_NUM_MEM_REC: 1395 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op); 1396 break; 1397 1398 case IV_CMD_INIT: 1399 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1400 break; 1401 1402 case IVD_CMD_SET_DISPLAY_FRAME: 1403 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1404 break; 1405 1406 case IVD_CMD_REL_DISPLAY_FRAME: 1407 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1408 break; 1409 1410 case IVD_CMD_VIDEO_DECODE: 1411 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op); 1412 break; 1413 1414 case IV_CMD_RETRIEVE_MEMREC: 1415 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1416 break; 1417 1418 case IVD_CMD_VIDEO_CTL: 1419 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op); 1420 break; 1421 1422 default: 1423 break; 1424 } 1425 1426 return(u4_error_code); 1427 1428 } 1429 1430 /*****************************************************************************/ 1431 /* */ 1432 /* Function Name : impeg2d_api_num_mem_rec */ 1433 /* */ 1434 /* Description : The function get the number mem records library needs */ 1435 /* Inputs : Error message */ 1436 /* Globals : None */ 1437 /* Processing : Just prints error message to console */ 1438 /* Outputs : Error mesage to the console */ 1439 /* Returns : None */ 1440 /* */ 1441 /* Issues : <List any issues or problems with this function> */ 1442 /* */ 1443 /* Revision History: */ 1444 /* */ 1445 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1446 /* 23 09 2010 Hamsalekha Creation */ 1447 /* */ 1448 /*****************************************************************************/ 1449 1450 1451 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op) 1452 { 1453 /* To Query No of Memory Records */ 1454 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip; 1455 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op; 1456 1457 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip; 1458 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op; 1459 1460 UNUSED(ps_query_mem_rec_ip); 1461 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t); 1462 1463 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS; 1464 1465 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS; 1466 1467 1468 return(IV_SUCCESS); 1469 1470 } 1471 1472 1473 /*****************************************************************************/ 1474 /* */ 1475 /* Function Name : impeg2d_api_fill_mem_rec */ 1476 /* */ 1477 /* Description : Thsi functions fills details of each mem record lib needs*/ 1478 /* Inputs : Error message */ 1479 /* Globals : None */ 1480 /* Processing : Just prints error message to console */ 1481 /* Outputs : Error mesage to the console */ 1482 /* Returns : None */ 1483 /* */ 1484 /* Issues : <List any issues or problems with this function> */ 1485 /* */ 1486 /* Revision History: */ 1487 /* */ 1488 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1489 /* 23 09 2010 Hamsalekha Creation */ 1490 /* */ 1491 /*****************************************************************************/ 1492 1493 1494 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op) 1495 { 1496 1497 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip; 1498 impeg2d_fill_mem_rec_op_t *ps_mem_q_op; 1499 1500 1501 ps_mem_q_ip = pv_api_ip; 1502 ps_mem_q_op = pv_api_op; 1503 1504 1505 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip, 1506 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op); 1507 1508 1509 return(IV_SUCCESS); 1510 1511 } 1512 1513 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size) 1514 { 1515 UWORD32 u4_min_num_out_bufs = 0; 1516 if(u1_chroma_format == IV_YUV_420P) 1517 u4_min_num_out_bufs = MIN_OUT_BUFS_420; 1518 else if(u1_chroma_format == IV_YUV_422ILE) 1519 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 1520 else if(u1_chroma_format == IV_RGB_565) 1521 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 1522 else if((u1_chroma_format == IV_YUV_420SP_UV) 1523 || (u1_chroma_format == IV_YUV_420SP_VU)) 1524 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 1525 1526 if(u1_chroma_format == IV_YUV_420P) 1527 { 1528 p_buf_size[0] = (pic_wd * pic_ht); 1529 p_buf_size[1] = (pic_wd * pic_ht) 1530 >> 2; 1531 p_buf_size[2] = (pic_wd * pic_ht) 1532 >> 2; 1533 } 1534 else if(u1_chroma_format == IV_YUV_422ILE) 1535 { 1536 p_buf_size[0] = (pic_wd * pic_ht) 1537 * 2; 1538 p_buf_size[1] = 1539 p_buf_size[2] = 0; 1540 } 1541 else if(u1_chroma_format == IV_RGB_565) 1542 { 1543 p_buf_size[0] = (pic_wd * pic_ht) 1544 * 2; 1545 p_buf_size[1] = 1546 p_buf_size[2] = 0; 1547 } 1548 else if((u1_chroma_format == IV_YUV_420SP_UV) 1549 || (u1_chroma_format == IV_YUV_420SP_VU)) 1550 { 1551 p_buf_size[0] = (pic_wd * pic_ht); 1552 p_buf_size[1] = (pic_wd * pic_ht) 1553 >> 1; 1554 p_buf_size[2] = 0; 1555 } 1556 1557 return u4_min_num_out_bufs; 1558 } 1559 1560 WORD32 check_app_out_buf_size(dec_state_t *ps_dec) 1561 { 1562 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS]; 1563 UWORD32 u4_min_num_out_bufs, i; 1564 UWORD32 pic_wd, pic_ht; 1565 1566 pic_wd = ps_dec->u2_horizontal_size; 1567 pic_ht = ps_dec->u2_vertical_size; 1568 1569 if(ps_dec->u4_frm_buf_stride > pic_wd) 1570 pic_wd = ps_dec->u4_frm_buf_stride; 1571 1572 u4_min_num_out_bufs = impeg2d_get_outbuf_size(pic_wd, pic_ht, ps_dec->i4_chromaFormat, &au4_min_out_buf_size[0]); 1573 1574 if (0 == ps_dec->u4_share_disp_buf) 1575 { 1576 if(ps_dec->ps_out_buf->u4_num_bufs < u4_min_num_out_bufs) 1577 { 1578 return IV_FAIL; 1579 } 1580 1581 for (i = 0 ; i < u4_min_num_out_bufs; i++) 1582 { 1583 if(ps_dec->ps_out_buf->u4_min_out_buf_size[i] < au4_min_out_buf_size[i]) 1584 return (IV_FAIL); 1585 } 1586 } 1587 else 1588 { 1589 if(ps_dec->as_disp_buffers[0].u4_num_bufs < u4_min_num_out_bufs) 1590 return IV_FAIL; 1591 1592 for (i = 0 ; i < u4_min_num_out_bufs; i++) 1593 { 1594 /* We need to check only with the disp_buffer[0], because we have 1595 * already ensured that all the buffers are of the same size in 1596 * impeg2d_api_set_display_frame. 1597 */ 1598 if(ps_dec->as_disp_buffers[0].u4_min_out_buf_size[i] < 1599 au4_min_out_buf_size[i]) 1600 return (IV_FAIL); 1601 } 1602 } 1603 1604 return(IV_SUCCESS); 1605 } 1606 1607 1608 1609 /*****************************************************************************/ 1610 /* */ 1611 /* Function Name : impeg2d_api_init */ 1612 /* */ 1613 /* Description : */ 1614 /* Inputs : */ 1615 /* Globals : */ 1616 /* Processing : */ 1617 /* Outputs : */ 1618 /* Returns : */ 1619 /* */ 1620 /* Issues : */ 1621 /* */ 1622 /* Revision History: */ 1623 /* */ 1624 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1625 /* 17 09 2007 Rajendra C Y Draft */ 1626 /* */ 1627 /*****************************************************************************/ 1628 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl, 1629 void *ps_ip, 1630 void *ps_op) 1631 { 1632 UWORD32 i; 1633 1634 void *pv; 1635 UWORD32 u4_size; 1636 1637 dec_state_t *ps_dec_state; 1638 dec_state_multi_core_t *ps_dec_state_multi_core; 1639 UWORD32 u4_num_mem_rec; 1640 iv_mem_rec_t *ps_mem_rec ; 1641 iv_mem_rec_t *ps_frm_buf; 1642 iv_obj_t *ps_dec_handle; 1643 WORD32 i4_max_wd, i4_max_ht; 1644 1645 impeg2d_init_ip_t *ps_dec_init_ip; 1646 impeg2d_init_op_t *ps_dec_init_op; 1647 WORD32 i4_num_threads; 1648 UWORD32 u4_share_disp_buf, u4_chroma_format; 1649 UWORD32 u4_deinterlace; 1650 1651 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip; 1652 ps_dec_init_op = (impeg2d_init_op_t *)ps_op; 1653 1654 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd); 1655 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht); 1656 1657 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf)) 1658 { 1659 #ifndef LOGO_EN 1660 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf; 1661 #else 1662 u4_share_disp_buf = 0; 1663 #endif 1664 } 1665 else 1666 { 1667 u4_share_disp_buf = 0; 1668 } 1669 1670 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format; 1671 1672 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace)) 1673 { 1674 u4_deinterlace = ps_dec_init_ip->u4_deinterlace; 1675 } 1676 else 1677 { 1678 u4_deinterlace = 0; 1679 } 1680 1681 if( (u4_chroma_format != IV_YUV_420P) && 1682 (u4_chroma_format != IV_YUV_420SP_UV) && 1683 (u4_chroma_format != IV_YUV_420SP_VU)) 1684 { 1685 u4_share_disp_buf = 0; 1686 } 1687 1688 /* Disable deinterlacer in shared mode */ 1689 if(u4_share_disp_buf) 1690 { 1691 u4_deinterlace = 0; 1692 } 1693 1694 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location; 1695 ps_mem_rec ++; 1696 1697 1698 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t); 1699 1700 1701 /* Except memTab[0], all other memTabs are initialized to zero */ 1702 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++) 1703 { 1704 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size); 1705 ps_mem_rec++; 1706 } 1707 1708 /* Reinitializing memTab[0] memory base address */ 1709 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location; 1710 1711 1712 /* memTab[0] is for codec Handle,redundant currently not being used */ 1713 ps_dec_handle = ps_mem_rec->pv_base; 1714 u4_num_mem_rec = 1; 1715 ps_mem_rec++; 1716 1717 1718 1719 1720 1721 /* decoder handle */ 1722 ps_dec_state_multi_core = ps_mem_rec->pv_base; 1723 u4_num_mem_rec++; 1724 ps_mem_rec++; 1725 1726 1727 { 1728 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */ 1729 1730 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core; 1731 ps_dechdl->pv_fxns = (void *)impeg2d_api_function; 1732 } 1733 1734 1735 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 1736 { 1737 /*************************************************************************/ 1738 /* For MPEG2 Decoder Context */ 1739 /*************************************************************************/ 1740 ps_dec_state = ps_mem_rec->pv_base; 1741 1742 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state; 1743 1744 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core; 1745 1746 ps_dec_state->i4_num_cores = 1; 1747 /* @ */ /* Used for storing MemRecords */ 1748 u4_num_mem_rec++; 1749 ps_mem_rec++; 1750 1751 /* Thread handle */ 1752 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base; 1753 u4_num_mem_rec++; 1754 ps_mem_rec++; 1755 1756 /*************************************************************************/ 1757 /* For Motion Compensation Buffers */ 1758 /*************************************************************************/ 1759 pv = ps_mem_rec->pv_base; 1760 1761 /* for mc_fw_buf.pu1_y */ 1762 1763 ps_dec_state->s_mc_fw_buf.pu1_y = pv; 1764 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE); 1765 1766 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE; 1767 /* for mc_fw_buf.pu1_u */ 1768 1769 ps_dec_state->s_mc_fw_buf.pu1_u = pv; 1770 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1771 1772 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1773 1774 /* for mc_fw_buf.pu1_v */ 1775 1776 ps_dec_state->s_mc_fw_buf.pu1_v = pv; 1777 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1778 1779 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1780 1781 /* for mc_bk_buf.pu1_y */ 1782 1783 ps_dec_state->s_mc_bk_buf.pu1_y = pv; 1784 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE); 1785 1786 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE; 1787 1788 /* for mc_bk_buf.pu1_u */ 1789 1790 ps_dec_state->s_mc_bk_buf.pu1_u = pv; 1791 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1792 1793 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1794 1795 /* for mc_bk_buf.pu1_v */ 1796 1797 ps_dec_state->s_mc_bk_buf.pu1_v = pv; 1798 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1799 1800 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1801 1802 /* for mc_buf.pu1_y */ 1803 1804 ps_dec_state->s_mc_buf.pu1_y = pv; 1805 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE); 1806 1807 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE; 1808 1809 /* for mc_buf.pu1_u */ 1810 1811 ps_dec_state->s_mc_buf.pu1_u = pv; 1812 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE); 1813 1814 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1815 1816 /* for mc_buf.pu1_v */ 1817 1818 ps_dec_state->s_mc_buf.pu1_v = pv; 1819 1820 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE; 1821 1822 u4_num_mem_rec++; 1823 ps_mem_rec++; 1824 1825 1826 1827 ps_dec_state->pv_pic_buf_mg = 0; 1828 1829 /*************************************************************************/ 1830 /* For saving stack context to support global error handling */ 1831 /*************************************************************************/ 1832 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base; 1833 u4_num_mem_rec++; 1834 ps_mem_rec++; 1835 1836 } 1837 1838 1839 1840 1841 1842 /*************************************************************************/ 1843 /* For Picture Buffer Manager */ 1844 /*************************************************************************/ 1845 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1846 1847 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base; 1848 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t); 1849 1850 u4_num_mem_rec++; 1851 ps_mem_rec++; 1852 1853 1854 1855 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++) 1856 { 1857 1858 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads]; 1859 1860 1861 /* --------------------------------------------------------------------- */ 1862 /* Initializations */ 1863 1864 ps_dec_state->u2_header_done = 0; /* Header decoding not done */ 1865 1866 1867 { 1868 UWORD32 u4_max_frm_width,u4_max_frm_height; 1869 1870 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd); 1871 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht); 1872 1873 ps_dec_state->u2_create_max_width = u4_max_frm_width; 1874 ps_dec_state->u2_create_max_height = u4_max_frm_height; 1875 1876 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format; 1877 ps_dec_state->u4_frm_buf_stride = 0 ; 1878 ps_dec_state->u2_frame_width = u4_max_frm_width; 1879 ps_dec_state->u2_picture_width = u4_max_frm_width; 1880 ps_dec_state->u2_horizontal_size = u4_max_frm_width; 1881 1882 ps_dec_state->u2_frame_height = u4_max_frm_height; 1883 ps_dec_state->u2_vertical_size = u4_max_frm_height; 1884 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf; 1885 ps_dec_state->u4_deinterlace = u4_deinterlace; 1886 ps_dec_state->ps_deint_pic = NULL; 1887 } 1888 } 1889 1890 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1891 1892 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE) 1893 &&((ps_dec_state->u2_vertical_size & 0x1) != 0)) 1894 { 1895 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n"); 1896 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR; 1897 return(IV_FAIL); 1898 1899 1900 } 1901 1902 /* --------------------------------------------------------------------- */ 1903 1904 1905 /* ! */ 1906 // picture buffer manager initialization will be done only for first thread 1907 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr); 1908 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg); 1909 1910 /*************************************************************************/ 1911 /* Internal Frame Buffers */ 1912 /*************************************************************************/ 1913 1914 1915 /* Set first frame to grey */ 1916 { 1917 ps_frm_buf = ps_mem_rec; 1918 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size); 1919 ps_frm_buf++; 1920 } 1921 1922 if(0 == ps_dec_state->u4_share_disp_buf) 1923 { 1924 pic_buf_t *ps_pic_buf; 1925 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base; 1926 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++) 1927 { 1928 UWORD8 *pu1_buf; 1929 pu1_buf = ps_mem_rec->pv_base; 1930 1931 ps_pic_buf->pu1_y = pu1_buf; 1932 pu1_buf += i4_max_ht * i4_max_wd; 1933 1934 ps_pic_buf->pu1_u = pu1_buf; 1935 pu1_buf += i4_max_ht * i4_max_wd >> 2; 1936 1937 ps_pic_buf->pu1_v = pu1_buf; 1938 pu1_buf += i4_max_ht * i4_max_wd >> 2; 1939 1940 ps_pic_buf->i4_buf_id = i; 1941 1942 ps_pic_buf->u1_used_as_ref = 0; 1943 1944 ps_pic_buf->u4_ts = 0; 1945 1946 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i); 1947 ps_mem_rec++; 1948 ps_pic_buf++; 1949 } 1950 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS; 1951 } 1952 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P) 1953 { 1954 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++) 1955 { 1956 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base; 1957 ps_mem_rec++; 1958 } 1959 1960 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS; 1961 } 1962 else 1963 { 1964 ps_mem_rec+=NUM_INT_FRAME_BUFFERS; 1965 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS; 1966 } 1967 1968 1969 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 1970 1971 ps_dec_state->pu1_input_buffer = ps_mem_rec->pv_base; 1972 u4_num_mem_rec++; 1973 ps_mem_rec++; 1974 1975 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base; 1976 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size; 1977 u4_num_mem_rec++; 1978 ps_mem_rec++; 1979 1980 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec) 1981 { 1982 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT; 1983 return(IV_FAIL); 1984 1985 } 1986 1987 ps_dec_state->u1_flushfrm = 0; 1988 ps_dec_state->u1_flushcnt = 0; 1989 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size); 1990 1991 1992 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base; 1993 u4_num_mem_rec++; 1994 ps_mem_rec++; 1995 1996 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base; 1997 u4_num_mem_rec++; 1998 ps_mem_rec++; 1999 2000 2001 /*************************************************************************/ 2002 /* Last MemTab is used for storing TabRecords */ 2003 /*************************************************************************/ 2004 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base; 2005 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size); 2006 /* Updating in Decoder Context with memRecords */ 2007 u4_num_mem_rec++; 2008 ps_mem_rec++; 2009 ps_dec_state->u4_num_mem_records = u4_num_mem_rec; 2010 2011 2012 ps_dec_state->u4_num_frames_decoded = 0; 2013 ps_dec_state->aps_ref_pics[0] = NULL; 2014 ps_dec_state->aps_ref_pics[1] = NULL; 2015 2016 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS; 2017 2018 impeg2d_init_arch(ps_dec_state); 2019 2020 impeg2d_init_function_ptr(ps_dec_state); 2021 2022 return(IV_SUCCESS); 2023 } 2024 2025 /*****************************************************************************/ 2026 /* */ 2027 /* Function Name : impeg2d_api_retrieve_mem_rec */ 2028 /* */ 2029 /* Description : */ 2030 /* */ 2031 /* Inputs : */ 2032 /* Globals : <Does it use any global variables?> */ 2033 /* Outputs : */ 2034 /* Returns : void */ 2035 /* */ 2036 /* Issues : none */ 2037 /* */ 2038 /* Revision History: */ 2039 /* */ 2040 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2041 /* 22 10 2008 100356 Draft */ 2042 /* */ 2043 /*****************************************************************************/ 2044 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl, 2045 void *pv_api_ip, 2046 void *pv_api_op) 2047 { 2048 UWORD32 u4_i; 2049 dec_state_t *ps_dec_state; 2050 dec_state_multi_core_t *ps_dec_state_multi_core; 2051 iv_mem_rec_t *ps_mem_rec; 2052 iv_mem_rec_t *ps_temp_rec; 2053 2054 2055 2056 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip; 2057 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op; 2058 2059 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip; 2060 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op; 2061 2062 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location; 2063 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle); 2064 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 2065 ps_temp_rec = ps_dec_state->pv_memTab; 2066 2067 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++) 2068 { 2069 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size; 2070 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment; 2071 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type; 2072 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base; 2073 } 2074 2075 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS; 2076 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records; 2077 2078 impeg2_jobq_deinit(ps_dec_state->pv_jobq); 2079 IMPEG2D_PRINT_STATISTICS(); 2080 2081 2082 return(IV_SUCCESS); 2083 2084 } 2085 2086 /*****************************************************************************/ 2087 /* */ 2088 /* Function Name : impeg2d_api_ctl */ 2089 /* */ 2090 /* Description : */ 2091 /* */ 2092 /* Inputs : */ 2093 /* Globals : <Does it use any global variables?> */ 2094 /* Outputs : */ 2095 /* Returns : void */ 2096 /* */ 2097 /* Issues : none */ 2098 /* */ 2099 /* Revision History: */ 2100 /* */ 2101 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2102 /* 22 10 2008 100356 Draft */ 2103 /* */ 2104 /*****************************************************************************/ 2105 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl, 2106 void *pv_api_ip, 2107 void *pv_api_op) 2108 { 2109 WORD32 i4_sub_cmd; 2110 UWORD32 *pu4_api_ip; 2111 IV_API_CALL_STATUS_T u4_error_code; 2112 2113 pu4_api_ip = (UWORD32 *)pv_api_ip; 2114 i4_sub_cmd = *(pu4_api_ip + 2); 2115 2116 switch(i4_sub_cmd) 2117 { 2118 case IVD_CMD_CTL_GETPARAMS: 2119 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip, 2120 (void *)pv_api_op); 2121 break; 2122 2123 case IVD_CMD_CTL_SETPARAMS: 2124 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip, 2125 (void *)pv_api_op); 2126 break; 2127 2128 case IVD_CMD_CTL_RESET: 2129 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip, 2130 (void *)pv_api_op); 2131 break; 2132 2133 case IVD_CMD_CTL_SETDEFAULT: 2134 u4_error_code = impeg2d_api_set_default(ps_dechdl, 2135 (void *)pv_api_ip, 2136 (void *)pv_api_op); 2137 break; 2138 2139 case IVD_CMD_CTL_FLUSH: 2140 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl, 2141 (void *)pv_api_ip, 2142 (void *)pv_api_op); 2143 break; 2144 2145 case IVD_CMD_CTL_GETBUFINFO: 2146 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl, 2147 (void *)pv_api_ip, 2148 (void *)pv_api_op); 2149 break; 2150 2151 case IVD_CMD_CTL_GETVERSION: 2152 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip, 2153 (void *)pv_api_op); 2154 break; 2155 2156 case IMPEG2D_CMD_CTL_SET_NUM_CORES: 2157 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl, 2158 (void *)pv_api_ip, 2159 (void *)pv_api_op); 2160 break; 2161 2162 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS: 2163 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl, 2164 (void *)pv_api_ip, 2165 (void *)pv_api_op); 2166 break; 2167 2168 case IMPEG2D_CMD_CTL_GET_SEQ_INFO: 2169 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl, 2170 (void *)pv_api_ip, 2171 (void *)pv_api_op); 2172 break; 2173 2174 case IMPEG2D_CMD_CTL_SET_PROCESSOR: 2175 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip, 2176 (void *)pv_api_op); 2177 break; 2178 2179 default: 2180 u4_error_code = IV_FAIL; 2181 break; 2182 } 2183 2184 return (u4_error_code); 2185 2186 } 2187 2188 /*****************************************************************************/ 2189 /* */ 2190 /* Function Name : impeg2d_api_check_struct_sanity */ 2191 /* */ 2192 /* Description : */ 2193 /* */ 2194 /* Inputs : */ 2195 /* Globals : <Does it use any global variables?> */ 2196 /* Outputs : */ 2197 /* Returns : void */ 2198 /* */ 2199 /* Issues : none */ 2200 /* */ 2201 /* Revision History: */ 2202 /* */ 2203 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2204 /* 22 10 2008 100356 Draft */ 2205 /* */ 2206 /*****************************************************************************/ 2207 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle, 2208 void *pv_api_ip, 2209 void *pv_api_op) 2210 { 2211 WORD32 i4_cmd; 2212 UWORD32 *pu4_api_ip; 2213 UWORD32 *pu4_api_op; 2214 WORD32 i,j; 2215 2216 if(NULL == pv_api_op) 2217 return(IV_FAIL); 2218 2219 if(NULL == pv_api_ip) 2220 return(IV_FAIL); 2221 2222 pu4_api_ip = (UWORD32 *)pv_api_ip; 2223 pu4_api_op = (UWORD32 *)pv_api_op; 2224 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1); 2225 2226 /* error checks on handle */ 2227 switch(i4_cmd) 2228 { 2229 case IV_CMD_GET_NUM_MEM_REC: 2230 case IV_CMD_FILL_NUM_MEM_REC: 2231 break; 2232 case IV_CMD_INIT: 2233 if(ps_handle == NULL) 2234 { 2235 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2236 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 2237 return IV_FAIL; 2238 } 2239 2240 if(ps_handle->u4_size != sizeof(iv_obj_t)) 2241 { 2242 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2243 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 2244 return IV_FAIL; 2245 } 2246 break; 2247 case IVD_CMD_GET_DISPLAY_FRAME: 2248 case IVD_CMD_VIDEO_DECODE: 2249 case IV_CMD_RETRIEVE_MEMREC: 2250 case IVD_CMD_SET_DISPLAY_FRAME: 2251 case IVD_CMD_REL_DISPLAY_FRAME: 2252 case IVD_CMD_VIDEO_CTL: 2253 { 2254 if(ps_handle == NULL) 2255 { 2256 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2257 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 2258 return IV_FAIL; 2259 } 2260 2261 if(ps_handle->u4_size != sizeof(iv_obj_t)) 2262 { 2263 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2264 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 2265 return IV_FAIL; 2266 } 2267 if(ps_handle->pv_fxns != impeg2d_api_function) 2268 { 2269 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2270 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 2271 return IV_FAIL; 2272 } 2273 2274 if(ps_handle->pv_codec_handle == NULL) 2275 { 2276 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2277 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 2278 return IV_FAIL; 2279 } 2280 } 2281 break; 2282 default: 2283 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 2284 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 2285 return IV_FAIL; 2286 } 2287 2288 switch(i4_cmd) 2289 { 2290 case IV_CMD_GET_NUM_MEM_REC: 2291 { 2292 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip; 2293 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op; 2294 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0; 2295 2296 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t)) 2297 { 2298 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2299 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2300 return(IV_FAIL); 2301 } 2302 2303 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t)) 2304 { 2305 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2306 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2307 return(IV_FAIL); 2308 } 2309 } 2310 break; 2311 case IV_CMD_FILL_NUM_MEM_REC: 2312 { 2313 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip; 2314 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op; 2315 iv_mem_rec_t *ps_mem_rec; 2316 2317 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0; 2318 2319 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t)) 2320 { 2321 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2322 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2323 return(IV_FAIL); 2324 } 2325 2326 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t)) 2327 { 2328 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2329 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2330 return(IV_FAIL); 2331 } 2332 2333 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH) 2334 { 2335 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2336 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 2337 return(IV_FAIL); 2338 } 2339 2340 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH) 2341 { 2342 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2343 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED; 2344 return(IV_FAIL); 2345 } 2346 2347 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT) 2348 { 2349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2350 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 2351 return(IV_FAIL); 2352 } 2353 2354 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT) 2355 { 2356 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2357 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED; 2358 return(IV_FAIL); 2359 } 2360 2361 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location) 2362 { 2363 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2364 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT; 2365 return(IV_FAIL); 2366 } 2367 2368 /* check memrecords sizes are correct */ 2369 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location; 2370 for(i=0;i<NUM_MEM_RECORDS;i++) 2371 { 2372 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 2373 { 2374 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2375 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 2376 return IV_FAIL; 2377 } 2378 } 2379 } 2380 break; 2381 2382 case IV_CMD_INIT: 2383 { 2384 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip; 2385 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op; 2386 iv_mem_rec_t *ps_mem_rec; 2387 UWORD32 u4_tot_num_mem_recs; 2388 2389 ps_op->s_ivd_init_op_t.u4_error_code = 0; 2390 2391 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t)) 2392 { 2393 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2394 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2395 return(IV_FAIL); 2396 } 2397 2398 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t)) 2399 { 2400 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2401 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2402 return(IV_FAIL); 2403 } 2404 2405 u4_tot_num_mem_recs = NUM_MEM_RECORDS; 2406 2407 2408 2409 2410 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs) 2411 { 2412 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2413 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT; 2414 return(IV_FAIL); 2415 } 2416 2417 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH) 2418 { 2419 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2420 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 2421 return(IV_FAIL); 2422 } 2423 2424 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH) 2425 { 2426 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2427 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED; 2428 return(IV_FAIL); 2429 } 2430 2431 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT) 2432 { 2433 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2434 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 2435 return(IV_FAIL); 2436 } 2437 2438 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT) 2439 { 2440 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2441 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED; 2442 return(IV_FAIL); 2443 } 2444 2445 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location) 2446 { 2447 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2448 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT; 2449 return(IV_FAIL); 2450 } 2451 2452 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) && 2453 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU)) 2454 { 2455 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2456 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 2457 return(IV_FAIL); 2458 } 2459 2460 /* verify number of mem records */ 2461 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS) 2462 { 2463 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2464 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT; 2465 return IV_FAIL; 2466 } 2467 2468 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location; 2469 /* verify wether first memrecord is handle or not */ 2470 /* 2471 if(ps_mem_rec->pv_base != ps_handle) 2472 { 2473 // indicate the incorrect handle error 2474 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2475 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE; 2476 return IV_FAIL; 2477 } 2478 */ 2479 /* check memrecords sizes are correct */ 2480 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++) 2481 { 2482 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 2483 { 2484 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2485 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 2486 return IV_FAIL; 2487 } 2488 } 2489 2490 /* verify memtabs for overlapping regions */ 2491 { 2492 UWORD8 *pau1_start[NUM_MEM_RECORDS]; 2493 UWORD8 *pau1_end[NUM_MEM_RECORDS]; 2494 2495 2496 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base); 2497 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1; 2498 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++) 2499 { 2500 /* This array is populated to check memtab overlapp */ 2501 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base); 2502 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1; 2503 2504 for(j = 0; j < i; j++) 2505 { 2506 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j])) 2507 { 2508 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2509 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 2510 return IV_FAIL; 2511 } 2512 2513 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j])) 2514 { 2515 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2516 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 2517 return IV_FAIL; 2518 } 2519 2520 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j])) 2521 { 2522 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2523 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR; 2524 return IV_FAIL; 2525 } 2526 } 2527 } 2528 } 2529 2530 2531 2532 2533 { 2534 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS]; 2535 2536 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip; 2537 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op; 2538 IV_API_CALL_STATUS_T e_status; 2539 WORD32 i4_num_memrec; 2540 { 2541 2542 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip; 2543 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op; 2544 2545 2546 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t); 2547 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t); 2548 2549 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC; 2550 impeg2d_api_function(NULL, 2551 (void *)&s_no_of_mem_rec_query_ip, 2552 (void *)&s_no_of_mem_rec_query_op); 2553 2554 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec; 2555 2556 2557 2558 } 2559 2560 2561 /* initialize mem records array with sizes */ 2562 for(i = 0; i < i4_num_memrec; i++) 2563 { 2564 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t); 2565 } 2566 2567 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t); 2568 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC; 2569 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd; 2570 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht; 2571 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api; 2572 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf; 2573 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format; 2574 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t); 2575 2576 2577 e_status = impeg2d_api_function(NULL, 2578 (void *)&s_fill_mem_rec_ip, 2579 (void *)&s_fill_mem_rec_op); 2580 if(IV_FAIL == e_status) 2581 { 2582 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code; 2583 return(IV_FAIL); 2584 } 2585 2586 2587 2588 for(i = 0; i < i4_num_memrec; i ++) 2589 { 2590 if(ps_mem_rec[i].pv_base == NULL) 2591 { 2592 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2593 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL; 2594 return IV_FAIL; 2595 } 2596 #ifdef CHECK_ALIGN 2597 2598 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1)) 2599 { 2600 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2601 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR; 2602 return IV_FAIL; 2603 } 2604 #endif //CHECK_ALIGN 2605 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment) 2606 { 2607 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2608 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR; 2609 return IV_FAIL; 2610 } 2611 2612 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size) 2613 { 2614 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2615 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE; 2616 return IV_FAIL; 2617 } 2618 2619 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type) 2620 { 2621 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type) 2622 { 2623 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type) 2624 { 2625 continue; 2626 } 2627 } 2628 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2629 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE; 2630 return IV_FAIL; 2631 } 2632 } 2633 } 2634 2635 2636 } 2637 break; 2638 2639 case IVD_CMD_GET_DISPLAY_FRAME: 2640 { 2641 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip; 2642 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op; 2643 2644 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 2645 2646 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t)) 2647 { 2648 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2649 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2650 return(IV_FAIL); 2651 } 2652 2653 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t)) 2654 { 2655 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2656 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2657 return(IV_FAIL); 2658 } 2659 2660 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0) 2661 { 2662 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2663 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2664 return IV_FAIL; 2665 } 2666 2667 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++) 2668 { 2669 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL) 2670 { 2671 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2672 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 2673 return IV_FAIL; 2674 } 2675 2676 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0) 2677 { 2678 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2679 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2680 return IV_FAIL; 2681 } 2682 /* 2683 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0) 2684 { 2685 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2686 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2687 return IV_FAIL; 2688 } 2689 */ 2690 } 2691 } 2692 break; 2693 case IVD_CMD_REL_DISPLAY_FRAME: 2694 { 2695 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip; 2696 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op; 2697 2698 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 2699 2700 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t)) 2701 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t))) 2702 { 2703 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2704 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2705 return(IV_FAIL); 2706 } 2707 2708 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) && 2709 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t))) 2710 { 2711 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2712 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2713 return(IV_FAIL); 2714 } 2715 2716 } 2717 break; 2718 2719 2720 case IVD_CMD_SET_DISPLAY_FRAME: 2721 { 2722 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip; 2723 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op; 2724 UWORD32 j, i; 2725 2726 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 2727 2728 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t)) 2729 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t))) 2730 { 2731 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2732 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2733 return(IV_FAIL); 2734 } 2735 2736 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) && 2737 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t))) 2738 { 2739 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2740 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2741 return(IV_FAIL); 2742 } 2743 2744 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 2745 { 2746 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2747 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2748 return IV_FAIL; 2749 } 2750 2751 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++) 2752 { 2753 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0) 2754 { 2755 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2756 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 2757 return IV_FAIL; 2758 } 2759 2760 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++) 2761 { 2762 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL) 2763 { 2764 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2765 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 2766 return IV_FAIL; 2767 } 2768 2769 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0) 2770 { 2771 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2772 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2773 return IV_FAIL; 2774 } 2775 } 2776 } 2777 } 2778 break; 2779 2780 case IVD_CMD_VIDEO_DECODE: 2781 { 2782 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip; 2783 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op; 2784 2785 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 2786 2787 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t)) 2788 { 2789 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2790 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2791 return(IV_FAIL); 2792 } 2793 2794 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t)) 2795 { 2796 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2797 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2798 return(IV_FAIL); 2799 } 2800 2801 } 2802 break; 2803 2804 case IV_CMD_RETRIEVE_MEMREC: 2805 { 2806 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip; 2807 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op; 2808 iv_mem_rec_t *ps_mem_rec; 2809 2810 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0; 2811 2812 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t)) 2813 { 2814 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2815 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2816 return(IV_FAIL); 2817 } 2818 2819 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t)) 2820 { 2821 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2822 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2823 return(IV_FAIL); 2824 } 2825 2826 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location; 2827 /* check memrecords sizes are correct */ 2828 for(i=0;i < NUM_MEM_RECORDS ; i++) 2829 { 2830 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 2831 { 2832 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2833 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT; 2834 return IV_FAIL; 2835 } 2836 } 2837 } 2838 break; 2839 2840 case IVD_CMD_VIDEO_CTL: 2841 { 2842 UWORD32 *pu4_ptr_cmd; 2843 UWORD32 u4_sub_command; 2844 2845 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 2846 pu4_ptr_cmd += 2; 2847 u4_sub_command = *pu4_ptr_cmd; 2848 2849 switch(u4_sub_command) 2850 { 2851 case IVD_CMD_CTL_SETPARAMS: 2852 { 2853 impeg2d_ctl_set_config_ip_t *ps_ip; 2854 impeg2d_ctl_set_config_op_t *ps_op; 2855 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip; 2856 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op; 2857 2858 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0; 2859 2860 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t)) 2861 { 2862 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2863 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2864 return IV_FAIL; 2865 } 2866 } 2867 case IVD_CMD_CTL_SETDEFAULT: 2868 { 2869 impeg2d_ctl_set_config_op_t *ps_op; 2870 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op; 2871 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0; 2872 2873 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t)) 2874 { 2875 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2876 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2877 return IV_FAIL; 2878 } 2879 } 2880 break; 2881 2882 case IVD_CMD_CTL_GETPARAMS: 2883 { 2884 impeg2d_ctl_getstatus_ip_t *ps_ip; 2885 impeg2d_ctl_getstatus_op_t *ps_op; 2886 2887 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip; 2888 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op; 2889 2890 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0; 2891 2892 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t)) 2893 { 2894 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2895 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2896 return IV_FAIL; 2897 } 2898 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t)) 2899 { 2900 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2901 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2902 return IV_FAIL; 2903 } 2904 } 2905 break; 2906 2907 case IVD_CMD_CTL_GETBUFINFO: 2908 { 2909 impeg2d_ctl_getbufinfo_ip_t *ps_ip; 2910 impeg2d_ctl_getbufinfo_op_t *ps_op; 2911 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip; 2912 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op; 2913 2914 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0; 2915 2916 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t)) 2917 { 2918 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2919 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2920 return IV_FAIL; 2921 } 2922 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t)) 2923 { 2924 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2925 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2926 return IV_FAIL; 2927 } 2928 } 2929 break; 2930 2931 case IVD_CMD_CTL_GETVERSION: 2932 { 2933 impeg2d_ctl_getversioninfo_ip_t *ps_ip; 2934 impeg2d_ctl_getversioninfo_op_t *ps_op; 2935 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip; 2936 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op; 2937 2938 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0; 2939 2940 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t)) 2941 { 2942 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2943 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2944 return IV_FAIL; 2945 } 2946 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t)) 2947 { 2948 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2949 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2950 return IV_FAIL; 2951 } 2952 } 2953 break; 2954 2955 case IVD_CMD_CTL_FLUSH: 2956 { 2957 impeg2d_ctl_flush_ip_t *ps_ip; 2958 impeg2d_ctl_flush_op_t *ps_op; 2959 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip; 2960 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op; 2961 2962 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0; 2963 2964 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t)) 2965 { 2966 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2967 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2968 return IV_FAIL; 2969 } 2970 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t)) 2971 { 2972 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2973 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2974 return IV_FAIL; 2975 } 2976 } 2977 break; 2978 2979 case IVD_CMD_CTL_RESET: 2980 { 2981 impeg2d_ctl_reset_ip_t *ps_ip; 2982 impeg2d_ctl_reset_op_t *ps_op; 2983 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip; 2984 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op; 2985 2986 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0; 2987 2988 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t)) 2989 { 2990 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2991 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT; 2992 return IV_FAIL; 2993 } 2994 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t)) 2995 { 2996 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 2997 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT; 2998 return IV_FAIL; 2999 } 3000 } 3001 break; 3002 3003 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS: 3004 { 3005 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip; 3006 impeg2d_ctl_get_frame_dimensions_op_t *ps_op; 3007 3008 ps_ip = 3009 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 3010 ps_op = 3011 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op; 3012 3013 if(ps_ip->u4_size 3014 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t)) 3015 { 3016 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3017 ps_op->u4_error_code |= 3018 IVD_IP_API_STRUCT_SIZE_INCORRECT; 3019 return IV_FAIL; 3020 } 3021 3022 if(ps_op->u4_size 3023 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t)) 3024 { 3025 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3026 ps_op->u4_error_code |= 3027 IVD_OP_API_STRUCT_SIZE_INCORRECT; 3028 return IV_FAIL; 3029 } 3030 3031 break; 3032 } 3033 case IMPEG2D_CMD_CTL_GET_SEQ_INFO: 3034 { 3035 impeg2d_ctl_get_seq_info_ip_t *ps_ip; 3036 impeg2d_ctl_get_seq_info_op_t *ps_op; 3037 3038 ps_ip = 3039 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip; 3040 ps_op = 3041 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op; 3042 3043 if(ps_ip->u4_size 3044 != sizeof(impeg2d_ctl_get_seq_info_ip_t)) 3045 { 3046 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3047 ps_op->u4_error_code |= 3048 IVD_IP_API_STRUCT_SIZE_INCORRECT; 3049 return IV_FAIL; 3050 } 3051 3052 if(ps_op->u4_size 3053 != sizeof(impeg2d_ctl_get_seq_info_op_t)) 3054 { 3055 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3056 ps_op->u4_error_code |= 3057 IVD_OP_API_STRUCT_SIZE_INCORRECT; 3058 return IV_FAIL; 3059 } 3060 3061 break; 3062 } 3063 case IMPEG2D_CMD_CTL_SET_NUM_CORES: 3064 { 3065 impeg2d_ctl_set_num_cores_ip_t *ps_ip; 3066 impeg2d_ctl_set_num_cores_op_t *ps_op; 3067 3068 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip; 3069 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op; 3070 3071 if(ps_ip->u4_size 3072 != sizeof(impeg2d_ctl_set_num_cores_ip_t)) 3073 { 3074 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3075 ps_op->u4_error_code |= 3076 IVD_IP_API_STRUCT_SIZE_INCORRECT; 3077 return IV_FAIL; 3078 } 3079 3080 if(ps_op->u4_size 3081 != sizeof(impeg2d_ctl_set_num_cores_op_t)) 3082 { 3083 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3084 ps_op->u4_error_code |= 3085 IVD_OP_API_STRUCT_SIZE_INCORRECT; 3086 return IV_FAIL; 3087 } 3088 3089 #ifdef MULTICORE 3090 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS)) 3091 #else 3092 if(ps_ip->u4_num_cores != 1) 3093 #endif 3094 { 3095 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3096 return IV_FAIL; 3097 } 3098 break; 3099 } 3100 case IMPEG2D_CMD_CTL_SET_PROCESSOR: 3101 { 3102 impeg2d_ctl_set_processor_ip_t *ps_ip; 3103 impeg2d_ctl_set_processor_op_t *ps_op; 3104 3105 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip; 3106 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op; 3107 3108 if(ps_ip->u4_size 3109 != sizeof(impeg2d_ctl_set_processor_ip_t)) 3110 { 3111 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3112 ps_op->u4_error_code |= 3113 IVD_IP_API_STRUCT_SIZE_INCORRECT; 3114 return IV_FAIL; 3115 } 3116 3117 if(ps_op->u4_size 3118 != sizeof(impeg2d_ctl_set_processor_op_t)) 3119 { 3120 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3121 ps_op->u4_error_code |= 3122 IVD_OP_API_STRUCT_SIZE_INCORRECT; 3123 return IV_FAIL; 3124 } 3125 3126 break; 3127 } 3128 default: 3129 break; 3130 3131 } 3132 } 3133 break; 3134 3135 default: 3136 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 3137 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 3138 return IV_FAIL; 3139 } 3140 3141 3142 } 3143 3144 return IV_SUCCESS; 3145 } 3146 3147 /*****************************************************************************/ 3148 /* */ 3149 /* Function Name : impeg2d_api_entity */ 3150 /* */ 3151 /* Description : */ 3152 /* */ 3153 /* Inputs : */ 3154 /* Globals : <Does it use any global variables?> */ 3155 /* Outputs : */ 3156 /* Returns : void */ 3157 /* */ 3158 /* Issues : none */ 3159 /* */ 3160 /* Revision History: */ 3161 /* */ 3162 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3163 /* 22 10 2008 100356 Draft */ 3164 /* */ 3165 /*****************************************************************************/ 3166 3167 3168 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl, 3169 void *pv_api_ip, 3170 void *pv_api_op) 3171 { 3172 iv_obj_t *ps_dec_handle; 3173 dec_state_t *ps_dec_state; 3174 dec_state_multi_core_t *ps_dec_state_multi_core; 3175 3176 impeg2d_video_decode_ip_t *ps_dec_ip; 3177 3178 impeg2d_video_decode_op_t *ps_dec_op; 3179 WORD32 bytes_remaining; 3180 pic_buf_t *ps_disp_pic; 3181 3182 3183 3184 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip; 3185 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op; 3186 3187 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t)); 3188 3189 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t); 3190 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0; 3191 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes; 3192 3193 ps_dec_handle = (iv_obj_t *)ps_dechdl; 3194 3195 if(ps_dechdl == NULL) 3196 { 3197 return(IV_FAIL); 3198 } 3199 3200 3201 3202 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle; 3203 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0]; 3204 3205 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3206 if(0 == ps_dec_state->u4_share_disp_buf) 3207 { 3208 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0]; 3209 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1]; 3210 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2]; 3211 } 3212 3213 ps_dec_state->ps_disp_pic = NULL; 3214 ps_dec_state->i4_frame_decoded = 0; 3215 /*rest bytes consumed */ 3216 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0; 3217 3218 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS; 3219 3220 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0)) 3221 { 3222 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 3223 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 3224 return IV_FAIL; 3225 } 3226 3227 3228 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT) 3229 { 3230 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR; 3231 return(IV_FAIL); 3232 } 3233 3234 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0)) 3235 { 3236 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op); 3237 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed; 3238 } 3239 3240 if((1 != ps_dec_state->u2_decode_header) && 3241 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm)) 3242 { 3243 if(ps_dec_state->u1_flushfrm) 3244 { 3245 if(ps_dec_state->aps_ref_pics[1] != NULL) 3246 { 3247 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id); 3248 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF); 3249 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF); 3250 3251 ps_dec_state->aps_ref_pics[1] = NULL; 3252 ps_dec_state->aps_ref_pics[0] = NULL; 3253 3254 } 3255 else if(ps_dec_state->aps_ref_pics[0] != NULL) 3256 { 3257 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id); 3258 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF); 3259 3260 ps_dec_state->aps_ref_pics[0] = NULL; 3261 } 3262 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t); 3263 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t); 3264 3265 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id); 3266 3267 ps_dec_state->ps_disp_pic = ps_disp_pic; 3268 if(ps_disp_pic == NULL) 3269 { 3270 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0; 3271 } 3272 else 3273 { 3274 WORD32 fmt_conv; 3275 if(0 == ps_dec_state->u4_share_disp_buf) 3276 { 3277 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0]; 3278 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1]; 3279 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2]; 3280 fmt_conv = 1; 3281 } 3282 else 3283 { 3284 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y; 3285 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat) 3286 { 3287 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u; 3288 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v; 3289 fmt_conv = 0; 3290 } 3291 else 3292 { 3293 UWORD8 *pu1_buf; 3294 3295 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1]; 3296 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf; 3297 3298 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2]; 3299 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf; 3300 fmt_conv = 1; 3301 } 3302 } 3303 3304 if(fmt_conv == 1) 3305 { 3306 iv_yuv_buf_t *ps_dst; 3307 3308 3309 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3310 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame)) 3311 { 3312 impeg2d_deinterlace(ps_dec_state, 3313 ps_disp_pic, 3314 ps_dst, 3315 0, 3316 ps_dec_state->u2_vertical_size); 3317 3318 } 3319 else 3320 { 3321 impeg2d_format_convert(ps_dec_state, 3322 ps_disp_pic, 3323 ps_dst, 3324 0, 3325 ps_dec_state->u2_vertical_size); 3326 } 3327 } 3328 3329 if(ps_dec_state->u4_deinterlace) 3330 { 3331 if(ps_dec_state->ps_deint_pic) 3332 { 3333 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, 3334 ps_dec_state->ps_deint_pic->i4_buf_id, 3335 MPEG2_BUF_MGR_DEINT); 3336 } 3337 ps_dec_state->ps_deint_pic = ps_disp_pic; 3338 } 3339 if(0 == ps_dec_state->u4_share_disp_buf) 3340 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP); 3341 3342 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size; 3343 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size; 3344 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1; 3345 3346 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id; 3347 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts; 3348 3349 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat; 3350 3351 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type); 3352 3353 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE; 3354 3355 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size; 3356 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride; 3357 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size; 3358 3359 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1; 3360 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3361 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1; 3362 3363 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1; 3364 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3365 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1; 3366 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3367 3368 switch(ps_dec_state->i4_chromaFormat) 3369 { 3370 case IV_YUV_420SP_UV: 3371 case IV_YUV_420SP_VU: 3372 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size; 3373 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride; 3374 break; 3375 case IV_YUV_422ILE: 3376 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0; 3377 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0; 3378 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0; 3379 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0; 3380 break; 3381 default: 3382 break; 3383 } 3384 3385 3386 } 3387 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present) 3388 { 3389 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present) 3390 { 3391 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0], 3392 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1], 3393 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2], 3394 ps_dec_state->u4_frm_buf_stride, 3395 ps_dec_state->u2_horizontal_size, 3396 ps_dec_state->u2_vertical_size, 3397 ps_dec_state->i4_chromaFormat, 3398 ps_dec_state->u2_horizontal_size, 3399 ps_dec_state->u2_vertical_size); 3400 } 3401 return(IV_SUCCESS); 3402 } 3403 else 3404 { 3405 ps_dec_state->u1_flushfrm = 0; 3406 3407 return(IV_FAIL); 3408 } 3409 3410 } 3411 else if(ps_dec_state->u1_flushfrm==0) 3412 { 3413 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t); 3414 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t); 3415 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4) 3416 { 3417 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes; 3418 return(IV_FAIL); 3419 } 3420 3421 if(1 == ps_dec_state->u4_share_disp_buf) 3422 { 3423 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg)) 3424 { 3425 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = 3426 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL; 3427 return IV_FAIL; 3428 } 3429 } 3430 3431 3432 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat; 3433 3434 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type); 3435 3436 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE; 3437 3438 if (0 == ps_dec_state->u4_frm_buf_stride) 3439 { 3440 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size); 3441 } 3442 3443 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size; 3444 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride; 3445 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size; 3446 3447 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1; 3448 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3449 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1; 3450 3451 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1; 3452 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1; 3453 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1; 3454 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf); 3455 3456 switch(ps_dec_state->i4_chromaFormat) 3457 { 3458 case IV_YUV_420SP_UV: 3459 case IV_YUV_420SP_VU: 3460 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size; 3461 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride; 3462 break; 3463 case IV_YUV_422ILE: 3464 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0; 3465 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0; 3466 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0; 3467 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0; 3468 break; 3469 default: 3470 break; 3471 } 3472 3473 if( ps_dec_state->u1_flushfrm == 0) 3474 { 3475 ps_dec_state->u1_flushcnt = 0; 3476 3477 ps_dec_state->ps_out_buf = &ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer; 3478 if (IV_SUCCESS != check_app_out_buf_size(ps_dec_state)) 3479 { 3480 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 3481 return IV_FAIL; 3482 } 3483 3484 /*************************************************************************/ 3485 /* Frame Decode */ 3486 /*************************************************************************/ 3487 3488 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op); 3489 3490 if (IVD_ERROR_NONE == 3491 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code) 3492 { 3493 if(ps_dec_state->u1_first_frame_done == 0) 3494 { 3495 ps_dec_state->u1_first_frame_done = 1; 3496 } 3497 3498 if(ps_dec_state->ps_disp_pic) 3499 { 3500 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1; 3501 switch(ps_dec_state->ps_disp_pic->e_pic_type) 3502 { 3503 case I_PIC : 3504 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME; 3505 break; 3506 3507 case P_PIC: 3508 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME; 3509 break; 3510 3511 case B_PIC: 3512 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME; 3513 break; 3514 3515 case D_PIC: 3516 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME; 3517 break; 3518 3519 default : 3520 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT; 3521 break; 3522 } 3523 } 3524 else 3525 { 3526 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0; 3527 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME; 3528 } 3529 3530 ps_dec_state->u4_num_frames_decoded++; 3531 } 3532 } 3533 else 3534 { 3535 ps_dec_state->u1_flushcnt++; 3536 } 3537 } 3538 if(ps_dec_state->ps_disp_pic) 3539 { 3540 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id; 3541 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts; 3542 3543 if(0 == ps_dec_state->u4_share_disp_buf) 3544 { 3545 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP); 3546 } 3547 } 3548 3549 if(ps_dec_state->u4_deinterlace) 3550 { 3551 if(ps_dec_state->ps_deint_pic) 3552 { 3553 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, 3554 ps_dec_state->ps_deint_pic->i4_buf_id, 3555 MPEG2_BUF_MGR_DEINT); 3556 } 3557 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic; 3558 } 3559 3560 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present) 3561 { 3562 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0], 3563 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1], 3564 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2], 3565 ps_dec_state->u4_frm_buf_stride, 3566 ps_dec_state->u2_horizontal_size, 3567 ps_dec_state->u2_vertical_size, 3568 ps_dec_state->i4_chromaFormat, 3569 ps_dec_state->u2_horizontal_size, 3570 ps_dec_state->u2_vertical_size); 3571 } 3572 3573 } 3574 3575 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1; 3576 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type; 3577 3578 3579 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code) 3580 return IV_FAIL; 3581 else 3582 return IV_SUCCESS; 3583 } 3584
