| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| reloc-bad.s | 3 ldr r0, 0 label
5 ldr r0, 0 label
|
| ld-sp-warn.s | 3 ldr sp, [r0, #16]! label
4 ldr sp, [r1], #8 label
5 ldr sp, [r0, #16] label
6 ldr r1, [r0, #16] label
7 ldr r1, [r0, r1]! label
|
| sp-pc-usage-t.s | 30 ldr r0, [sp] label
31 ldr r0, [pc] label
32 ldr pc, [r0] label
33 ldr sp, [r0] label
34 ldr pc, [pc] label
35 ldr sp, [sp] label
36 ldr pc, [sp] label
37 ldr sp, [pc] label
|
| thumb1_unified.s | 14 ldr r2, bar label
15 ldr r3, [r4, #4] label
16 ldr r5, [sp, #4] label
|
| sp-pc-validations-bad.s | 6 @ LDR (immediate, ARM)
7 @ LDR (literal)
10 @ LDR (register)
11 ldr r0,[r1,pc, LSL #2] @ Unpredictable label
12 ldr r0,[r1,pc, LSL #2]! @ ditto label
13 ldr r0,[r1],pc, LSL #2 @ ditto label
14 ldr r0,[pc,r1, LSL #2]! @ ditto label
15 ldr r0,[pc],r1, LSL #2 @ ditto label
266 ldr r0, [r1] label
|
| sp-pc-validations-bad-t.s | 17 it_test ldr, \operands
21 it_testw ldr, \operands
26 @ LDR (register)
37 @ LDR (literal)
42 @ LDR (register)
225 @ldrt r0,[pc,#4] => LDR (literal)
373 ldr r0, [r1] label
|
| /external/clang/test/CXX/expr/ |
| p9.cpp | 7 long double &ldr = ld0; variable
|
| /external/llvm/test/MC/AArch64/ |
| arm64-diags.s | 8 ldr x3, (foo + 4)
9 ldr x3, [foo + 4]
10 ; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]
20 ldr x0, [x0, #804]
21 ldr w0, [x0, #802]
22 ldr x0, [x0, #804]!
23 ldr w0, [w0, #301]!
24 ldr x0, [x0], #804
25 ldr w0, [w0], #301
37 ; CHECK-ERRORS: ldr x0, [x0, #804
79 ldr w1, [x3, w3, sxtw #4] label
80 ldr x1, [x3, w3, sxtw #4] label
81 ldr b1, [x3, w3, sxtw #4] label
82 ldr h1, [x3, w3, sxtw #4] label
83 ldr s1, [x3, w3, sxtw #4] label
84 ldr d1, [x3, w3, sxtw #4] label
85 ldr q1, [x3, w3, sxtw #1] label
[all...] |
| /libcore/luni/src/test/java/tests/java/security/ |
| SecureClassLoaderTest.java | 184 MyClassLoader ldr = new MyClassLoader(); local
185 ldr.getPerms(null);
186 ldr.getPerms(cs);
193 // MyClassLoader ldr = new MyClassLoader();
194 // Class klass = ldr.define(null, klassData, 0, klassData.length, null);
202 // MyClassLoader ldr = new MyClassLoader();
204 // Class klass = ldr.define(null, bbuf, null);
|
| /bionic/tests/ |
| math_test.cpp | 1425 long double ldr = frexpl(1024.0L, &exp); local
[all...] |
| /external/boringssl/src/crypto/curve25519/asm/ |
| x25519-asm-arm.S | 44 ldr r4,=0 label
45 ldr r5,=254 label
63 ldr r7,=960 label
1559 ldr r2,[sp,#488] label
1560 ldr r4,[sp,#492] label
1571 ldr r1,=0 label
1574 ldr r4,=0 label
1575 ldr r5,=2 label
2023 ldr r2,[r1],#4 label
2024 ldr r3,[r1],#4 label
2025 ldr r4,[r1],#4 label
2026 ldr r5,[r1],#4 label
2027 ldr r6,[r1],#4 label
2028 ldr r7,[r1],#4 label
2029 ldr r8,[r1],#4 label
2030 ldr r9,[r1],#4 label
2031 ldr r10,[r1],#4 label
2032 ldr r1,[r1] label
2115 ldr r12,[sp,#480] label
2116 ldr r14,[sp,#484] label
2117 ldr r0,=0 label
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.h | 216 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond,
219 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond, function in namespace:Ice::ARM32
222 ldr(OpRt, OpAddress, Cond, TInfo);
753 // Emit ldr/ldrb/str/strb instruction with given address.
[all...] |
| /art/compiler/linker/arm/ |
| relative_patcher_thumb2_test.cc | 56 // LDR immediate, 16-bit, encoding T1. Bits 6-10 are imm5, 0-2 are Rt, 3-5 are Rn.
59 // LDR immediate, 32-bit, encoding T3. Bits 0-11 are offset, 12-15 are Rt, 16-20 are Rn.
62 // LDR immediate, negative offset, encoding T4. Bits 0-7 are the offset to subtract.
65 // LDR register, lsl #2. Bits 4-5 are the imm2, i.e. the lsl shift.
593 uint32_t ldr = kLdrWInsn | offset | (base_reg << 16) | (ref_reg << 12); local
594 const std::vector<uint8_t> raw_code = RawCode({kBneWPlus0, ldr});
615 uint32_t ldr = kLdrWInsn | offset | (base_reg << 16) | (ref_reg << 12); local
616 const std::vector<uint8_t> expected_code = RawCode({bne, ldr});
695 uint32_t ldr = kLdrInsn | (offset << (6 - 2)) | (base_reg << 3) | ref_reg; local
696 const std::vector<uint8_t> raw_code = RawCode({kBneWPlus0, ldr});
720 uint32_t ldr = kLdrInsn | (offset << (6 - 2)) | (base_reg << 3) | ref_reg; local
981 auto ldr = [](uint32_t base_reg) { local
1071 uint32_t ldr = kLdrWInsn | (\/* offset *\/ 8) | (\/* base_reg *\/ 0 << 16) | (root_reg << 12); local
1090 uint32_t ldr = kLdrWInsn | (\/* offset *\/ 8) | (\/* base_reg *\/ 0 << 16) | (root_reg << 12); local
1131 uint32_t ldr = kLdrInsn | (\/* offset *\/ 8 << (6 - 2)) | (\/* base_reg *\/ 0 << 3) | root_reg; local
1150 uint32_t ldr = kLdrInsn | (\/* offset *\/ 8 << (6 - 2)) | (\/* base_reg *\/ 0 << 3) | root_reg; local
1183 const uint32_t ldr = local
[all...] |
| /toolchain/binutils/binutils-2.27/binutils/ |
| od-xcoff.c | 1732 char *ldr; local
[all...] |
| /art/compiler/linker/arm64/ |
| relative_patcher_arm64_test.cc | 51 // LDR immediate, 32-bit, unsigned offset.
54 // LDR register, 32-bit, LSL #2.
69 // LDR w12, <label> and LDR x12, <label>. Bits 5-23 contain label displacement in 4-byte units.
73 // LDR w13, [SP, #<pimm>] and LDR x13, [SP, #<pimm>]. Bits 10-21 contain displacement from SP
230 use_insn |= 1 | // LDR x1, [x0, #(imm12 << 2)]
918 uint32_t ldr = kLdrWInsn | (offset << (10 - 2)) | (base_reg << 5) | ref_reg; local
941 uint32_t ldr = kLdrWInsn | (offset << (10 - 2)) | (base_reg << 5) | ref_reg; local
1158 auto ldr = [](uint32_t base_reg) { local
1244 uint32_t ldr = kLdrWInsn | (\/* offset *\/ 8 << (10 - 2)) | (\/* base_reg *\/ 0 << 5) | root_reg; local
1263 uint32_t ldr = kLdrWInsn | (\/* offset *\/ 8 << (10 - 2)) | (\/* base_reg *\/ 0 << 5) | root_reg; local
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | 119 Instruction* ldr = GetBuffer()->GetOffsetAddress<Instruction*>(offset); local
120 VIXL_ASSERT(ldr->IsLoadLiteral());
122 ptrdiff_t imm19 = ldr->GetImmLLiteral();
127 ldr->SetImmLLiteral(target);
1083 void Assembler::ldr(const CPURegister& rt, function in class:vixl::aarch64::Assembler
1200 void Assembler::ldr(const CPURegister& rt, RawLiteral* literal) { function in class:vixl::aarch64::Assembler
1211 void Assembler::ldr(const CPURegister& rt, int64_t imm19) { function in class:vixl::aarch64::Assembler
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.cc | 498 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
502 // ldr rd, [pc, #offset]
505 // ldr rd, [pp, #offset]
508 // ldr rd, [pp, rn]
541 // A mask for the Rd register for push, pop, ldr, str instructions.
792 // ldr<cond> <Rd>, [pc +/- offset_12].
799 // ldr<cond> <Rd>, [pp +/- offset_12].
806 // ldr<cond> <Rd>, [pp, +/- <Rm>].
2073 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) { function in class:v8::internal::Assembler
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 362 // ldr xzr, #pool_size
375 // ldr xzr, #pool_size
405 // ldr xzr, #<size of the constant pool in 32-bit words>
529 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
545 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
917 // 0: ldr xzr, #<size of pool>
1662 void Assembler::ldr(const CPURegister& rt, const MemOperand& src) { function in class:v8::internal::Assembler
1686 void Assembler::ldr(const CPURegister& rt, const Immediate& imm) { function in class:v8::internal::Assembler
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.cc | 2158 void Assembler::ldr(Register rd, const MemOperand& rs) { function in class:v8::internal::Assembler
[all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.cc | 4980 void Assembler::ldr(Condition cond, function in class:vixl::aarch32::Assembler
5175 void Assembler::ldr(Condition cond, function in class:vixl::aarch32::Assembler
[all...] |
| assembler-aarch32.h | 2364 void ldr(Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
2367 void ldr(Condition cond, Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
2370 void ldr(EncodingSize size, Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
2380 void ldr(Register rt, Location* location) { ldr(al, Best, rt, location); } function in class:vixl::aarch32::Assembler
2381 void ldr(Condition cond, Register rt, Location* location) { function in class:vixl::aarch32::Assembler
2384 void ldr(EncodingSize size, Register rt, Location* location) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.cc | 1693 void Disassembler::ldr(Condition cond, function in class:vixl::aarch32::Disassembler
1702 void Disassembler::ldr(Condition cond, function in class:vixl::aarch32::Disassembler
[all...] |
