1 /* tc-mips.c -- assemble code for a MIPS chip. 2 Copyright (C) 1993-2016 Free Software Foundation, Inc. 3 Contributed by the OSF and Ralph Campbell. 4 Written by Keith Knowles and Ralph Campbell, working independently. 5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus 6 Support. 7 8 This file is part of GAS. 9 10 GAS is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 GAS is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GAS; see the file COPYING. If not, write to the Free 22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 23 02110-1301, USA. */ 24 25 #include "as.h" 26 #include "config.h" 27 #include "subsegs.h" 28 #include "safe-ctype.h" 29 30 #include "opcode/mips.h" 31 #include "itbl-ops.h" 32 #include "dwarf2dbg.h" 33 #include "dw2gencfi.h" 34 35 /* Check assumptions made in this file. */ 36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; 37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; 38 39 #ifdef DEBUG 40 #define DBG(x) printf x 41 #else 42 #define DBG(x) 43 #endif 44 45 #define streq(a, b) (strcmp (a, b) == 0) 46 47 #define SKIP_SPACE_TABS(S) \ 48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) 49 50 /* Clean up namespace so we can include obj-elf.h too. */ 51 static int mips_output_flavor (void); 52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } 53 #undef OBJ_PROCESS_STAB 54 #undef OUTPUT_FLAVOR 55 #undef S_GET_ALIGN 56 #undef S_GET_SIZE 57 #undef S_SET_ALIGN 58 #undef S_SET_SIZE 59 #undef obj_frob_file 60 #undef obj_frob_file_after_relocs 61 #undef obj_frob_symbol 62 #undef obj_pop_insert 63 #undef obj_sec_sym_ok_for_reloc 64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES 65 66 #include "obj-elf.h" 67 /* Fix any of them that we actually care about. */ 68 #undef OUTPUT_FLAVOR 69 #define OUTPUT_FLAVOR mips_output_flavor() 70 71 #include "elf/mips.h" 72 73 #ifndef ECOFF_DEBUGGING 74 #define NO_ECOFF_DEBUGGING 75 #define ECOFF_DEBUGGING 0 76 #endif 77 78 int mips_flag_mdebug = -1; 79 80 /* Control generation of .pdr sections. Off by default on IRIX: the native 81 linker doesn't know about and discards them, but relocations against them 82 remain, leading to rld crashes. */ 83 #ifdef TE_IRIX 84 int mips_flag_pdr = FALSE; 85 #else 86 int mips_flag_pdr = TRUE; 87 #endif 88 89 #include "ecoff.h" 90 91 static char *mips_regmask_frag; 92 static char *mips_flags_frag; 93 94 #define ZERO 0 95 #define ATREG 1 96 #define S0 16 97 #define S7 23 98 #define TREG 24 99 #define PIC_CALL_REG 25 100 #define KT0 26 101 #define KT1 27 102 #define GP 28 103 #define SP 29 104 #define FP 30 105 #define RA 31 106 107 #define ILLEGAL_REG (32) 108 109 #define AT mips_opts.at 110 111 extern int target_big_endian; 112 113 /* The name of the readonly data section. */ 114 #define RDATA_SECTION_NAME ".rodata" 115 116 /* Ways in which an instruction can be "appended" to the output. */ 117 enum append_method { 118 /* Just add it normally. */ 119 APPEND_ADD, 120 121 /* Add it normally and then add a nop. */ 122 APPEND_ADD_WITH_NOP, 123 124 /* Turn an instruction with a delay slot into a "compact" version. */ 125 APPEND_ADD_COMPACT, 126 127 /* Insert the instruction before the last one. */ 128 APPEND_SWAP 129 }; 130 131 /* Information about an instruction, including its format, operands 132 and fixups. */ 133 struct mips_cl_insn 134 { 135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */ 136 const struct mips_opcode *insn_mo; 137 138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is 139 a copy of INSN_MO->match with the operands filled in. If we have 140 decided to use an extended MIPS16 instruction, this includes the 141 extension. */ 142 unsigned long insn_opcode; 143 144 /* The frag that contains the instruction. */ 145 struct frag *frag; 146 147 /* The offset into FRAG of the first instruction byte. */ 148 long where; 149 150 /* The relocs associated with the instruction, if any. */ 151 fixS *fixp[3]; 152 153 /* True if this entry cannot be moved from its current position. */ 154 unsigned int fixed_p : 1; 155 156 /* True if this instruction occurred in a .set noreorder block. */ 157 unsigned int noreorder_p : 1; 158 159 /* True for mips16 instructions that jump to an absolute address. */ 160 unsigned int mips16_absolute_jump_p : 1; 161 162 /* True if this instruction is complete. */ 163 unsigned int complete_p : 1; 164 165 /* True if this instruction is cleared from history by unconditional 166 branch. */ 167 unsigned int cleared_p : 1; 168 }; 169 170 /* The ABI to use. */ 171 enum mips_abi_level 172 { 173 NO_ABI = 0, 174 O32_ABI, 175 O64_ABI, 176 N32_ABI, 177 N64_ABI, 178 EABI_ABI 179 }; 180 181 /* MIPS ABI we are using for this output file. */ 182 static enum mips_abi_level mips_abi = NO_ABI; 183 184 /* Whether or not we have code that can call pic code. */ 185 int mips_abicalls = FALSE; 186 187 /* Whether or not we have code which can be put into a shared 188 library. */ 189 static bfd_boolean mips_in_shared = TRUE; 190 191 /* This is the set of options which may be modified by the .set 192 pseudo-op. We use a struct so that .set push and .set pop are more 193 reliable. */ 194 195 struct mips_set_options 196 { 197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 198 if it has not been initialized. Changed by `.set mipsN', and the 199 -mipsN command line option, and the default CPU. */ 200 int isa; 201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set 202 <asename>', by command line options, and based on the default 203 architecture. */ 204 int ase; 205 /* Whether we are assembling for the mips16 processor. 0 if we are 206 not, 1 if we are, and -1 if the value has not been initialized. 207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and 208 -nomips16 command line options, and the default CPU. */ 209 int mips16; 210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, 211 1 if we are, and -1 if the value has not been initialized. Changed 212 by `.set micromips' and `.set nomicromips', and the -mmicromips 213 and -mno-micromips command line options, and the default CPU. */ 214 int micromips; 215 /* Non-zero if we should not reorder instructions. Changed by `.set 216 reorder' and `.set noreorder'. */ 217 int noreorder; 218 /* Non-zero if we should not permit the register designated "assembler 219 temporary" to be used in instructions. The value is the register 220 number, normally $at ($1). Changed by `.set at=REG', `.set noat' 221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ 222 unsigned int at; 223 /* Non-zero if we should warn when a macro instruction expands into 224 more than one machine instruction. Changed by `.set nomacro' and 225 `.set macro'. */ 226 int warn_about_macros; 227 /* Non-zero if we should not move instructions. Changed by `.set 228 move', `.set volatile', `.set nomove', and `.set novolatile'. */ 229 int nomove; 230 /* Non-zero if we should not optimize branches by moving the target 231 of the branch into the delay slot. Actually, we don't perform 232 this optimization anyhow. Changed by `.set bopt' and `.set 233 nobopt'. */ 234 int nobopt; 235 /* Non-zero if we should not autoextend mips16 instructions. 236 Changed by `.set autoextend' and `.set noautoextend'. */ 237 int noautoextend; 238 /* True if we should only emit 32-bit microMIPS instructions. 239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32 240 and -mno-insn32 command line options. */ 241 bfd_boolean insn32; 242 /* Restrict general purpose registers and floating point registers 243 to 32 bit. This is initially determined when -mgp32 or -mfp32 244 is passed but can changed if the assembler code uses .set mipsN. */ 245 int gp; 246 int fp; 247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march 248 command line option, and the default CPU. */ 249 int arch; 250 /* True if ".set sym32" is in effect. */ 251 bfd_boolean sym32; 252 /* True if floating-point operations are not allowed. Changed by .set 253 softfloat or .set hardfloat, by command line options -msoft-float or 254 -mhard-float. The default is false. */ 255 bfd_boolean soft_float; 256 257 /* True if only single-precision floating-point operations are allowed. 258 Changed by .set singlefloat or .set doublefloat, command-line options 259 -msingle-float or -mdouble-float. The default is false. */ 260 bfd_boolean single_float; 261 262 /* 1 if single-precision operations on odd-numbered registers are 263 allowed. */ 264 int oddspreg; 265 }; 266 267 /* Specifies whether module level options have been checked yet. */ 268 static bfd_boolean file_mips_opts_checked = FALSE; 269 270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the 271 value has not been initialized. Changed by `.nan legacy' and 272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line 273 options, and the default CPU. */ 274 static int mips_nan2008 = -1; 275 276 /* This is the struct we use to hold the module level set of options. 277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and 278 fp fields to -1 to indicate that they have not been initialized. */ 279 280 static struct mips_set_options file_mips_opts = 281 { 282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 287 }; 288 289 /* This is similar to file_mips_opts, but for the current set of options. */ 290 291 static struct mips_set_options mips_opts = 292 { 293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 298 }; 299 300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */ 301 static unsigned int file_ase_explicit; 302 303 /* These variables are filled in with the masks of registers used. 304 The object format code reads them and puts them in the appropriate 305 place. */ 306 unsigned long mips_gprmask; 307 unsigned long mips_cprmask[4]; 308 309 /* True if any MIPS16 code was produced. */ 310 static int file_ase_mips16; 311 312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ 313 || mips_opts.isa == ISA_MIPS32R2 \ 314 || mips_opts.isa == ISA_MIPS32R3 \ 315 || mips_opts.isa == ISA_MIPS32R5 \ 316 || mips_opts.isa == ISA_MIPS64 \ 317 || mips_opts.isa == ISA_MIPS64R2 \ 318 || mips_opts.isa == ISA_MIPS64R3 \ 319 || mips_opts.isa == ISA_MIPS64R5) 320 321 /* True if any microMIPS code was produced. */ 322 static int file_ase_micromips; 323 324 /* True if we want to create R_MIPS_JALR for jalr $25. */ 325 #ifdef TE_IRIX 326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI 327 #else 328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, 329 because there's no place for any addend, the only acceptable 330 expression is a bare symbol. */ 331 #define MIPS_JALR_HINT_P(EXPR) \ 332 (!HAVE_IN_PLACE_ADDENDS \ 333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) 334 #endif 335 336 /* The argument of the -march= flag. The architecture we are assembling. */ 337 static const char *mips_arch_string; 338 339 /* The argument of the -mtune= flag. The architecture for which we 340 are optimizing. */ 341 static int mips_tune = CPU_UNKNOWN; 342 static const char *mips_tune_string; 343 344 /* True when generating 32-bit code for a 64-bit processor. */ 345 static int mips_32bitmode = 0; 346 347 /* True if the given ABI requires 32-bit registers. */ 348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) 349 350 /* Likewise 64-bit registers. */ 351 #define ABI_NEEDS_64BIT_REGS(ABI) \ 352 ((ABI) == N32_ABI \ 353 || (ABI) == N64_ABI \ 354 || (ABI) == O64_ABI) 355 356 #define ISA_IS_R6(ISA) \ 357 ((ISA) == ISA_MIPS32R6 \ 358 || (ISA) == ISA_MIPS64R6) 359 360 /* Return true if ISA supports 64 bit wide gp registers. */ 361 #define ISA_HAS_64BIT_REGS(ISA) \ 362 ((ISA) == ISA_MIPS3 \ 363 || (ISA) == ISA_MIPS4 \ 364 || (ISA) == ISA_MIPS5 \ 365 || (ISA) == ISA_MIPS64 \ 366 || (ISA) == ISA_MIPS64R2 \ 367 || (ISA) == ISA_MIPS64R3 \ 368 || (ISA) == ISA_MIPS64R5 \ 369 || (ISA) == ISA_MIPS64R6) 370 371 /* Return true if ISA supports 64 bit wide float registers. */ 372 #define ISA_HAS_64BIT_FPRS(ISA) \ 373 ((ISA) == ISA_MIPS3 \ 374 || (ISA) == ISA_MIPS4 \ 375 || (ISA) == ISA_MIPS5 \ 376 || (ISA) == ISA_MIPS32R2 \ 377 || (ISA) == ISA_MIPS32R3 \ 378 || (ISA) == ISA_MIPS32R5 \ 379 || (ISA) == ISA_MIPS32R6 \ 380 || (ISA) == ISA_MIPS64 \ 381 || (ISA) == ISA_MIPS64R2 \ 382 || (ISA) == ISA_MIPS64R3 \ 383 || (ISA) == ISA_MIPS64R5 \ 384 || (ISA) == ISA_MIPS64R6) 385 386 /* Return true if ISA supports 64-bit right rotate (dror et al.) 387 instructions. */ 388 #define ISA_HAS_DROR(ISA) \ 389 ((ISA) == ISA_MIPS64R2 \ 390 || (ISA) == ISA_MIPS64R3 \ 391 || (ISA) == ISA_MIPS64R5 \ 392 || (ISA) == ISA_MIPS64R6 \ 393 || (mips_opts.micromips \ 394 && ISA_HAS_64BIT_REGS (ISA)) \ 395 ) 396 397 /* Return true if ISA supports 32-bit right rotate (ror et al.) 398 instructions. */ 399 #define ISA_HAS_ROR(ISA) \ 400 ((ISA) == ISA_MIPS32R2 \ 401 || (ISA) == ISA_MIPS32R3 \ 402 || (ISA) == ISA_MIPS32R5 \ 403 || (ISA) == ISA_MIPS32R6 \ 404 || (ISA) == ISA_MIPS64R2 \ 405 || (ISA) == ISA_MIPS64R3 \ 406 || (ISA) == ISA_MIPS64R5 \ 407 || (ISA) == ISA_MIPS64R6 \ 408 || (mips_opts.ase & ASE_SMARTMIPS) \ 409 || mips_opts.micromips \ 410 ) 411 412 /* Return true if ISA supports single-precision floats in odd registers. */ 413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ 414 (((ISA) == ISA_MIPS32 \ 415 || (ISA) == ISA_MIPS32R2 \ 416 || (ISA) == ISA_MIPS32R3 \ 417 || (ISA) == ISA_MIPS32R5 \ 418 || (ISA) == ISA_MIPS32R6 \ 419 || (ISA) == ISA_MIPS64 \ 420 || (ISA) == ISA_MIPS64R2 \ 421 || (ISA) == ISA_MIPS64R3 \ 422 || (ISA) == ISA_MIPS64R5 \ 423 || (ISA) == ISA_MIPS64R6 \ 424 || (CPU) == CPU_R5900) \ 425 && (CPU) != CPU_LOONGSON_3A) 426 427 /* Return true if ISA supports move to/from high part of a 64-bit 428 floating-point register. */ 429 #define ISA_HAS_MXHC1(ISA) \ 430 ((ISA) == ISA_MIPS32R2 \ 431 || (ISA) == ISA_MIPS32R3 \ 432 || (ISA) == ISA_MIPS32R5 \ 433 || (ISA) == ISA_MIPS32R6 \ 434 || (ISA) == ISA_MIPS64R2 \ 435 || (ISA) == ISA_MIPS64R3 \ 436 || (ISA) == ISA_MIPS64R5 \ 437 || (ISA) == ISA_MIPS64R6) 438 439 /* Return true if ISA supports legacy NAN. */ 440 #define ISA_HAS_LEGACY_NAN(ISA) \ 441 ((ISA) == ISA_MIPS1 \ 442 || (ISA) == ISA_MIPS2 \ 443 || (ISA) == ISA_MIPS3 \ 444 || (ISA) == ISA_MIPS4 \ 445 || (ISA) == ISA_MIPS5 \ 446 || (ISA) == ISA_MIPS32 \ 447 || (ISA) == ISA_MIPS32R2 \ 448 || (ISA) == ISA_MIPS32R3 \ 449 || (ISA) == ISA_MIPS32R5 \ 450 || (ISA) == ISA_MIPS64 \ 451 || (ISA) == ISA_MIPS64R2 \ 452 || (ISA) == ISA_MIPS64R3 \ 453 || (ISA) == ISA_MIPS64R5) 454 455 #define GPR_SIZE \ 456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ 457 ? 32 \ 458 : mips_opts.gp) 459 460 #define FPR_SIZE \ 461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ 462 ? 32 \ 463 : mips_opts.fp) 464 465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) 466 467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) 468 469 /* True if relocations are stored in-place. */ 470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) 471 472 /* The ABI-derived address size. */ 473 #define HAVE_64BIT_ADDRESSES \ 474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) 475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) 476 477 /* The size of symbolic constants (i.e., expressions of the form 478 "SYMBOL" or "SYMBOL + OFFSET"). */ 479 #define HAVE_32BIT_SYMBOLS \ 480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) 481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) 482 483 /* Addresses are loaded in different ways, depending on the address size 484 in use. The n32 ABI Documentation also mandates the use of additions 485 with overflow checking, but existing implementations don't follow it. */ 486 #define ADDRESS_ADD_INSN \ 487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") 488 489 #define ADDRESS_ADDI_INSN \ 490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") 491 492 #define ADDRESS_LOAD_INSN \ 493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld") 494 495 #define ADDRESS_STORE_INSN \ 496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd") 497 498 /* Return true if the given CPU supports the MIPS16 ASE. */ 499 #define CPU_HAS_MIPS16(cpu) \ 500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ 501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) 502 503 /* Return true if the given CPU supports the microMIPS ASE. */ 504 #define CPU_HAS_MICROMIPS(cpu) 0 505 506 /* True if CPU has a dror instruction. */ 507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) 508 509 /* True if CPU has a ror instruction. */ 510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) 511 512 /* True if CPU is in the Octeon family */ 513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ 514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) 515 516 /* True if CPU has seq/sne and seqi/snei instructions. */ 517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) 518 519 /* True, if CPU has support for ldc1 and sdc1. */ 520 #define CPU_HAS_LDC1_SDC1(CPU) \ 521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) 522 523 /* True if mflo and mfhi can be immediately followed by instructions 524 which write to the HI and LO registers. 525 526 According to MIPS specifications, MIPS ISAs I, II, and III need 527 (at least) two instructions between the reads of HI/LO and 528 instructions which write them, and later ISAs do not. Contradicting 529 the MIPS specifications, some MIPS IV processor user manuals (e.g. 530 the UM for the NEC Vr5000) document needing the instructions between 531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 532 MIPS64 and later ISAs to have the interlocks, plus any specific 533 earlier-ISA CPUs for which CPU documentation declares that the 534 instructions are really interlocked. */ 535 #define hilo_interlocks \ 536 (mips_opts.isa == ISA_MIPS32 \ 537 || mips_opts.isa == ISA_MIPS32R2 \ 538 || mips_opts.isa == ISA_MIPS32R3 \ 539 || mips_opts.isa == ISA_MIPS32R5 \ 540 || mips_opts.isa == ISA_MIPS32R6 \ 541 || mips_opts.isa == ISA_MIPS64 \ 542 || mips_opts.isa == ISA_MIPS64R2 \ 543 || mips_opts.isa == ISA_MIPS64R3 \ 544 || mips_opts.isa == ISA_MIPS64R5 \ 545 || mips_opts.isa == ISA_MIPS64R6 \ 546 || mips_opts.arch == CPU_R4010 \ 547 || mips_opts.arch == CPU_R5900 \ 548 || mips_opts.arch == CPU_R10000 \ 549 || mips_opts.arch == CPU_R12000 \ 550 || mips_opts.arch == CPU_R14000 \ 551 || mips_opts.arch == CPU_R16000 \ 552 || mips_opts.arch == CPU_RM7000 \ 553 || mips_opts.arch == CPU_VR5500 \ 554 || mips_opts.micromips \ 555 ) 556 557 /* Whether the processor uses hardware interlocks to protect reads 558 from the GPRs after they are loaded from memory, and thus does not 559 require nops to be inserted. This applies to instructions marked 560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA 561 level I and microMIPS mode instructions are always interlocked. */ 562 #define gpr_interlocks \ 563 (mips_opts.isa != ISA_MIPS1 \ 564 || mips_opts.arch == CPU_R3900 \ 565 || mips_opts.arch == CPU_R5900 \ 566 || mips_opts.micromips \ 567 ) 568 569 /* Whether the processor uses hardware interlocks to avoid delays 570 required by coprocessor instructions, and thus does not require 571 nops to be inserted. This applies to instructions marked 572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between 573 instructions marked INSN_WRITE_COND_CODE and ones marked 574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA 575 levels I, II, and III and microMIPS mode instructions are always 576 interlocked. */ 577 /* Itbl support may require additional care here. */ 578 #define cop_interlocks \ 579 ((mips_opts.isa != ISA_MIPS1 \ 580 && mips_opts.isa != ISA_MIPS2 \ 581 && mips_opts.isa != ISA_MIPS3) \ 582 || mips_opts.arch == CPU_R4300 \ 583 || mips_opts.micromips \ 584 ) 585 586 /* Whether the processor uses hardware interlocks to protect reads 587 from coprocessor registers after they are loaded from memory, and 588 thus does not require nops to be inserted. This applies to 589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only 590 requires at MIPS ISA level I and microMIPS mode instructions are 591 always interlocked. */ 592 #define cop_mem_interlocks \ 593 (mips_opts.isa != ISA_MIPS1 \ 594 || mips_opts.micromips \ 595 ) 596 597 /* Is this a mfhi or mflo instruction? */ 598 #define MF_HILO_INSN(PINFO) \ 599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) 600 601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) 602 has been selected. This implies, in particular, that addresses of text 603 labels have their LSB set. */ 604 #define HAVE_CODE_COMPRESSION \ 605 ((mips_opts.mips16 | mips_opts.micromips) != 0) 606 607 /* The minimum and maximum signed values that can be stored in a GPR. */ 608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) 609 #define GPR_SMIN (-GPR_SMAX - 1) 610 611 /* MIPS PIC level. */ 612 613 enum mips_pic_level mips_pic; 614 615 /* 1 if we should generate 32 bit offsets from the $gp register in 616 SVR4_PIC mode. Currently has no meaning in other modes. */ 617 static int mips_big_got = 0; 618 619 /* 1 if trap instructions should used for overflow rather than break 620 instructions. */ 621 static int mips_trap = 0; 622 623 /* 1 if double width floating point constants should not be constructed 624 by assembling two single width halves into two single width floating 625 point registers which just happen to alias the double width destination 626 register. On some architectures this aliasing can be disabled by a bit 627 in the status register, and the setting of this bit cannot be determined 628 automatically at assemble time. */ 629 static int mips_disable_float_construction; 630 631 /* Non-zero if any .set noreorder directives were used. */ 632 633 static int mips_any_noreorder; 634 635 /* Non-zero if nops should be inserted when the register referenced in 636 an mfhi/mflo instruction is read in the next two instructions. */ 637 static int mips_7000_hilo_fix; 638 639 /* The size of objects in the small data section. */ 640 static unsigned int g_switch_value = 8; 641 /* Whether the -G option was used. */ 642 static int g_switch_seen = 0; 643 644 #define N_RMASK 0xc4 645 #define N_VFP 0xd4 646 647 /* If we can determine in advance that GP optimization won't be 648 possible, we can skip the relaxation stuff that tries to produce 649 GP-relative references. This makes delay slot optimization work 650 better. 651 652 This function can only provide a guess, but it seems to work for 653 gcc output. It needs to guess right for gcc, otherwise gcc 654 will put what it thinks is a GP-relative instruction in a branch 655 delay slot. 656 657 I don't know if a fix is needed for the SVR4_PIC mode. I've only 658 fixed it for the non-PIC mode. KR 95/04/07 */ 659 static int nopic_need_relax (symbolS *, int); 660 661 /* handle of the OPCODE hash table */ 662 static struct hash_control *op_hash = NULL; 663 664 /* The opcode hash table we use for the mips16. */ 665 static struct hash_control *mips16_op_hash = NULL; 666 667 /* The opcode hash table we use for the microMIPS ASE. */ 668 static struct hash_control *micromips_op_hash = NULL; 669 670 /* This array holds the chars that always start a comment. If the 671 pre-processor is disabled, these aren't very useful */ 672 const char comment_chars[] = "#"; 673 674 /* This array holds the chars that only start a comment at the beginning of 675 a line. If the line seems to have the form '# 123 filename' 676 .line and .file directives will appear in the pre-processed output */ 677 /* Note that input_file.c hand checks for '#' at the beginning of the 678 first line of the input file. This is because the compiler outputs 679 #NO_APP at the beginning of its output. */ 680 /* Also note that C style comments are always supported. */ 681 const char line_comment_chars[] = "#"; 682 683 /* This array holds machine specific line separator characters. */ 684 const char line_separator_chars[] = ";"; 685 686 /* Chars that can be used to separate mant from exp in floating point nums */ 687 const char EXP_CHARS[] = "eE"; 688 689 /* Chars that mean this number is a floating point constant */ 690 /* As in 0f12.456 */ 691 /* or 0d1.2345e12 */ 692 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 693 694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 695 changed in read.c . Ideally it shouldn't have to know about it at all, 696 but nothing is ideal around here. 697 */ 698 699 /* Types of printf format used for instruction-related error messages. 700 "I" means int ("%d") and "S" means string ("%s"). */ 701 enum mips_insn_error_format { 702 ERR_FMT_PLAIN, 703 ERR_FMT_I, 704 ERR_FMT_SS, 705 }; 706 707 /* Information about an error that was found while assembling the current 708 instruction. */ 709 struct mips_insn_error { 710 /* We sometimes need to match an instruction against more than one 711 opcode table entry. Errors found during this matching are reported 712 against a particular syntactic argument rather than against the 713 instruction as a whole. We grade these messages so that errors 714 against argument N have a greater priority than an error against 715 any argument < N, since the former implies that arguments up to N 716 were acceptable and that the opcode entry was therefore a closer match. 717 If several matches report an error against the same argument, 718 we only use that error if it is the same in all cases. 719 720 min_argnum is the minimum argument number for which an error message 721 should be accepted. It is 0 if MSG is against the instruction as 722 a whole. */ 723 int min_argnum; 724 725 /* The printf()-style message, including its format and arguments. */ 726 enum mips_insn_error_format format; 727 const char *msg; 728 union { 729 int i; 730 const char *ss[2]; 731 } u; 732 }; 733 734 /* The error that should be reported for the current instruction. */ 735 static struct mips_insn_error insn_error; 736 737 static int auto_align = 1; 738 739 /* When outputting SVR4 PIC code, the assembler needs to know the 740 offset in the stack frame from which to restore the $gp register. 741 This is set by the .cprestore pseudo-op, and saved in this 742 variable. */ 743 static offsetT mips_cprestore_offset = -1; 744 745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some 746 more optimizations, it can use a register value instead of a memory-saved 747 offset and even an other register than $gp as global pointer. */ 748 static offsetT mips_cpreturn_offset = -1; 749 static int mips_cpreturn_register = -1; 750 static int mips_gp_register = GP; 751 static int mips_gprel_offset = 0; 752 753 /* Whether mips_cprestore_offset has been set in the current function 754 (or whether it has already been warned about, if not). */ 755 static int mips_cprestore_valid = 0; 756 757 /* This is the register which holds the stack frame, as set by the 758 .frame pseudo-op. This is needed to implement .cprestore. */ 759 static int mips_frame_reg = SP; 760 761 /* Whether mips_frame_reg has been set in the current function 762 (or whether it has already been warned about, if not). */ 763 static int mips_frame_reg_valid = 0; 764 765 /* To output NOP instructions correctly, we need to keep information 766 about the previous two instructions. */ 767 768 /* Whether we are optimizing. The default value of 2 means to remove 769 unneeded NOPs and swap branch instructions when possible. A value 770 of 1 means to not swap branches. A value of 0 means to always 771 insert NOPs. */ 772 static int mips_optimize = 2; 773 774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is 775 equivalent to seeing no -g option at all. */ 776 static int mips_debug = 0; 777 778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ 779 #define MAX_VR4130_NOPS 4 780 781 /* The maximum number of NOPs needed to fill delay slots. */ 782 #define MAX_DELAY_NOPS 2 783 784 /* The maximum number of NOPs needed for any purpose. */ 785 #define MAX_NOPS 4 786 787 /* A list of previous instructions, with index 0 being the most recent. 788 We need to look back MAX_NOPS instructions when filling delay slots 789 or working around processor errata. We need to look back one 790 instruction further if we're thinking about using history[0] to 791 fill a branch delay slot. */ 792 static struct mips_cl_insn history[1 + MAX_NOPS]; 793 794 /* Arrays of operands for each instruction. */ 795 #define MAX_OPERANDS 6 796 struct mips_operand_array { 797 const struct mips_operand *operand[MAX_OPERANDS]; 798 }; 799 static struct mips_operand_array *mips_operands; 800 static struct mips_operand_array *mips16_operands; 801 static struct mips_operand_array *micromips_operands; 802 803 /* Nop instructions used by emit_nop. */ 804 static struct mips_cl_insn nop_insn; 805 static struct mips_cl_insn mips16_nop_insn; 806 static struct mips_cl_insn micromips_nop16_insn; 807 static struct mips_cl_insn micromips_nop32_insn; 808 809 /* The appropriate nop for the current mode. */ 810 #define NOP_INSN (mips_opts.mips16 \ 811 ? &mips16_nop_insn \ 812 : (mips_opts.micromips \ 813 ? (mips_opts.insn32 \ 814 ? µmips_nop32_insn \ 815 : µmips_nop16_insn) \ 816 : &nop_insn)) 817 818 /* The size of NOP_INSN in bytes. */ 819 #define NOP_INSN_SIZE ((mips_opts.mips16 \ 820 || (mips_opts.micromips && !mips_opts.insn32)) \ 821 ? 2 : 4) 822 823 /* If this is set, it points to a frag holding nop instructions which 824 were inserted before the start of a noreorder section. If those 825 nops turn out to be unnecessary, the size of the frag can be 826 decreased. */ 827 static fragS *prev_nop_frag; 828 829 /* The number of nop instructions we created in prev_nop_frag. */ 830 static int prev_nop_frag_holds; 831 832 /* The number of nop instructions that we know we need in 833 prev_nop_frag. */ 834 static int prev_nop_frag_required; 835 836 /* The number of instructions we've seen since prev_nop_frag. */ 837 static int prev_nop_frag_since; 838 839 /* Relocations against symbols are sometimes done in two parts, with a HI 840 relocation and a LO relocation. Each relocation has only 16 bits of 841 space to store an addend. This means that in order for the linker to 842 handle carries correctly, it must be able to locate both the HI and 843 the LO relocation. This means that the relocations must appear in 844 order in the relocation table. 845 846 In order to implement this, we keep track of each unmatched HI 847 relocation. We then sort them so that they immediately precede the 848 corresponding LO relocation. */ 849 850 struct mips_hi_fixup 851 { 852 /* Next HI fixup. */ 853 struct mips_hi_fixup *next; 854 /* This fixup. */ 855 fixS *fixp; 856 /* The section this fixup is in. */ 857 segT seg; 858 }; 859 860 /* The list of unmatched HI relocs. */ 861 862 static struct mips_hi_fixup *mips_hi_fixup_list; 863 864 /* The frag containing the last explicit relocation operator. 865 Null if explicit relocations have not been used. */ 866 867 static fragS *prev_reloc_op_frag; 868 869 /* Map mips16 register numbers to normal MIPS register numbers. */ 870 871 static const unsigned int mips16_to_32_reg_map[] = 872 { 873 16, 17, 2, 3, 4, 5, 6, 7 874 }; 875 876 /* Map microMIPS register numbers to normal MIPS register numbers. */ 877 878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map 879 880 /* The microMIPS registers with type h. */ 881 static const unsigned int micromips_to_32_reg_h_map1[] = 882 { 883 5, 5, 6, 4, 4, 4, 4, 4 884 }; 885 static const unsigned int micromips_to_32_reg_h_map2[] = 886 { 887 6, 7, 7, 21, 22, 5, 6, 7 888 }; 889 890 /* The microMIPS registers with type m. */ 891 static const unsigned int micromips_to_32_reg_m_map[] = 892 { 893 0, 17, 2, 3, 16, 18, 19, 20 894 }; 895 896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map 897 898 /* Classifies the kind of instructions we're interested in when 899 implementing -mfix-vr4120. */ 900 enum fix_vr4120_class 901 { 902 FIX_VR4120_MACC, 903 FIX_VR4120_DMACC, 904 FIX_VR4120_MULT, 905 FIX_VR4120_DMULT, 906 FIX_VR4120_DIV, 907 FIX_VR4120_MTHILO, 908 NUM_FIX_VR4120_CLASSES 909 }; 910 911 /* ...likewise -mfix-loongson2f-jump. */ 912 static bfd_boolean mips_fix_loongson2f_jump; 913 914 /* ...likewise -mfix-loongson2f-nop. */ 915 static bfd_boolean mips_fix_loongson2f_nop; 916 917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ 918 static bfd_boolean mips_fix_loongson2f; 919 920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if 921 there must be at least one other instruction between an instruction 922 of type X and an instruction of type Y. */ 923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; 924 925 /* True if -mfix-vr4120 is in force. */ 926 static int mips_fix_vr4120; 927 928 /* ...likewise -mfix-vr4130. */ 929 static int mips_fix_vr4130; 930 931 /* ...likewise -mfix-24k. */ 932 static int mips_fix_24k; 933 934 /* ...likewise -mfix-rm7000 */ 935 static int mips_fix_rm7000; 936 937 /* ...likewise -mfix-cn63xxp1 */ 938 static bfd_boolean mips_fix_cn63xxp1; 939 940 /* We don't relax branches by default, since this causes us to expand 941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we 942 fail to compute the offset before expanding the macro to the most 943 efficient expansion. */ 944 945 static int mips_relax_branch; 946 947 /* The expansion of many macros depends on the type of symbol that 949 they refer to. For example, when generating position-dependent code, 950 a macro that refers to a symbol may have two different expansions, 951 one which uses GP-relative addresses and one which uses absolute 952 addresses. When generating SVR4-style PIC, a macro may have 953 different expansions for local and global symbols. 954 955 We handle these situations by generating both sequences and putting 956 them in variant frags. In position-dependent code, the first sequence 957 will be the GP-relative one and the second sequence will be the 958 absolute one. In SVR4 PIC, the first sequence will be for global 959 symbols and the second will be for local symbols. 960 961 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and 962 SECOND are the lengths of the two sequences in bytes. These fields 963 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, 964 the subtype has the following flags: 965 966 RELAX_USE_SECOND 967 Set if it has been decided that we should use the second 968 sequence instead of the first. 969 970 RELAX_SECOND_LONGER 971 Set in the first variant frag if the macro's second implementation 972 is longer than its first. This refers to the macro as a whole, 973 not an individual relaxation. 974 975 RELAX_NOMACRO 976 Set in the first variant frag if the macro appeared in a .set nomacro 977 block and if one alternative requires a warning but the other does not. 978 979 RELAX_DELAY_SLOT 980 Like RELAX_NOMACRO, but indicates that the macro appears in a branch 981 delay slot. 982 983 RELAX_DELAY_SLOT_16BIT 984 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a 985 16-bit instruction. 986 987 RELAX_DELAY_SLOT_SIZE_FIRST 988 Like RELAX_DELAY_SLOT, but indicates that the first implementation of 989 the macro is of the wrong size for the branch delay slot. 990 991 RELAX_DELAY_SLOT_SIZE_SECOND 992 Like RELAX_DELAY_SLOT, but indicates that the second implementation of 993 the macro is of the wrong size for the branch delay slot. 994 995 The frag's "opcode" points to the first fixup for relaxable code. 996 997 Relaxable macros are generated using a sequence such as: 998 999 relax_start (SYMBOL); 1000 ... generate first expansion ... 1001 relax_switch (); 1002 ... generate second expansion ... 1003 relax_end (); 1004 1005 The code and fixups for the unwanted alternative are discarded 1006 by md_convert_frag. */ 1007 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) 1008 1009 #define RELAX_FIRST(X) (((X) >> 8) & 0xff) 1010 #define RELAX_SECOND(X) ((X) & 0xff) 1011 #define RELAX_USE_SECOND 0x10000 1012 #define RELAX_SECOND_LONGER 0x20000 1013 #define RELAX_NOMACRO 0x40000 1014 #define RELAX_DELAY_SLOT 0x80000 1015 #define RELAX_DELAY_SLOT_16BIT 0x100000 1016 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 1017 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 1018 1019 /* Branch without likely bit. If label is out of range, we turn: 1020 1021 beq reg1, reg2, label 1022 delay slot 1023 1024 into 1025 1026 bne reg1, reg2, 0f 1027 nop 1028 j label 1029 0: delay slot 1030 1031 with the following opcode replacements: 1032 1033 beq <-> bne 1034 blez <-> bgtz 1035 bltz <-> bgez 1036 bc1f <-> bc1t 1037 1038 bltzal <-> bgezal (with jal label instead of j label) 1039 1040 Even though keeping the delay slot instruction in the delay slot of 1041 the branch would be more efficient, it would be very tricky to do 1042 correctly, because we'd have to introduce a variable frag *after* 1043 the delay slot instruction, and expand that instead. Let's do it 1044 the easy way for now, even if the branch-not-taken case now costs 1045 one additional instruction. Out-of-range branches are not supposed 1046 to be common, anyway. 1047 1048 Branch likely. If label is out of range, we turn: 1049 1050 beql reg1, reg2, label 1051 delay slot (annulled if branch not taken) 1052 1053 into 1054 1055 beql reg1, reg2, 1f 1056 nop 1057 beql $0, $0, 2f 1058 nop 1059 1: j[al] label 1060 delay slot (executed only if branch taken) 1061 2: 1062 1063 It would be possible to generate a shorter sequence by losing the 1064 likely bit, generating something like: 1065 1066 bne reg1, reg2, 0f 1067 nop 1068 j[al] label 1069 delay slot (executed only if branch taken) 1070 0: 1071 1072 beql -> bne 1073 bnel -> beq 1074 blezl -> bgtz 1075 bgtzl -> blez 1076 bltzl -> bgez 1077 bgezl -> bltz 1078 bc1fl -> bc1t 1079 bc1tl -> bc1f 1080 1081 bltzall -> bgezal (with jal label instead of j label) 1082 bgezall -> bltzal (ditto) 1083 1084 1085 but it's not clear that it would actually improve performance. */ 1086 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ 1087 ((relax_substateT) \ 1088 (0xc0000000 \ 1089 | ((at) & 0x1f) \ 1090 | ((toofar) ? 0x20 : 0) \ 1091 | ((link) ? 0x40 : 0) \ 1092 | ((likely) ? 0x80 : 0) \ 1093 | ((uncond) ? 0x100 : 0))) 1094 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 1095 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) 1096 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) 1097 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) 1098 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) 1099 #define RELAX_BRANCH_AT(i) ((i) & 0x1f) 1100 1101 /* For mips16 code, we use an entirely different form of relaxation. 1102 mips16 supports two versions of most instructions which take 1103 immediate values: a small one which takes some small value, and a 1104 larger one which takes a 16 bit value. Since branches also follow 1105 this pattern, relaxing these values is required. 1106 1107 We can assemble both mips16 and normal MIPS code in a single 1108 object. Therefore, we need to support this type of relaxation at 1109 the same time that we support the relaxation described above. We 1110 use the high bit of the subtype field to distinguish these cases. 1111 1112 The information we store for this type of relaxation is the 1113 argument code found in the opcode file for this relocation, whether 1114 the user explicitly requested a small or extended form, and whether 1115 the relocation is in a jump or jal delay slot. That tells us the 1116 size of the value, and how it should be stored. We also store 1117 whether the fragment is considered to be extended or not. We also 1118 store whether this is known to be a branch to a different section, 1119 whether we have tried to relax this frag yet, and whether we have 1120 ever extended a PC relative fragment because of a shift count. */ 1121 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ 1122 (0x80000000 \ 1123 | ((type) & 0xff) \ 1124 | ((small) ? 0x100 : 0) \ 1125 | ((ext) ? 0x200 : 0) \ 1126 | ((dslot) ? 0x400 : 0) \ 1127 | ((jal_dslot) ? 0x800 : 0)) 1128 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) 1129 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) 1130 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) 1131 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) 1132 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) 1133 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) 1134 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) 1135 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) 1136 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) 1137 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) 1138 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) 1139 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) 1140 1141 /* For microMIPS code, we use relaxation similar to one we use for 1142 MIPS16 code. Some instructions that take immediate values support 1143 two encodings: a small one which takes some small value, and a 1144 larger one which takes a 16 bit value. As some branches also follow 1145 this pattern, relaxing these values is required. 1146 1147 We can assemble both microMIPS and normal MIPS code in a single 1148 object. Therefore, we need to support this type of relaxation at 1149 the same time that we support the relaxation described above. We 1150 use one of the high bits of the subtype field to distinguish these 1151 cases. 1152 1153 The information we store for this type of relaxation is the argument 1154 code found in the opcode file for this relocation, the register 1155 selected as the assembler temporary, whether the branch is 1156 unconditional, whether it is compact, whether it stores the link 1157 address implicitly in $ra, whether relaxation of out-of-range 32-bit 1158 branches to a sequence of instructions is enabled, and whether the 1159 displacement of a branch is too large to fit as an immediate argument 1160 of a 16-bit and a 32-bit branch, respectively. */ 1161 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ 1162 relax32, toofar16, toofar32) \ 1163 (0x40000000 \ 1164 | ((type) & 0xff) \ 1165 | (((at) & 0x1f) << 8) \ 1166 | ((uncond) ? 0x2000 : 0) \ 1167 | ((compact) ? 0x4000 : 0) \ 1168 | ((link) ? 0x8000 : 0) \ 1169 | ((relax32) ? 0x10000 : 0) \ 1170 | ((toofar16) ? 0x20000 : 0) \ 1171 | ((toofar32) ? 0x40000 : 0)) 1172 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) 1173 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) 1174 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) 1175 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) 1176 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) 1177 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) 1178 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) 1179 1180 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) 1181 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) 1182 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) 1183 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) 1184 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) 1185 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) 1186 1187 /* Sign-extend 16-bit value X. */ 1188 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) 1189 1190 /* Is the given value a sign-extended 32-bit value? */ 1191 #define IS_SEXT_32BIT_NUM(x) \ 1192 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 1193 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 1194 1195 /* Is the given value a sign-extended 16-bit value? */ 1196 #define IS_SEXT_16BIT_NUM(x) \ 1197 (((x) &~ (offsetT) 0x7fff) == 0 \ 1198 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) 1199 1200 /* Is the given value a sign-extended 12-bit value? */ 1201 #define IS_SEXT_12BIT_NUM(x) \ 1202 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) 1203 1204 /* Is the given value a sign-extended 9-bit value? */ 1205 #define IS_SEXT_9BIT_NUM(x) \ 1206 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) 1207 1208 /* Is the given value a zero-extended 32-bit value? Or a negated one? */ 1209 #define IS_ZEXT_32BIT_NUM(x) \ 1210 (((x) &~ (offsetT) 0xffffffff) == 0 \ 1211 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 1212 1213 /* Extract bits MASK << SHIFT from STRUCT and shift them right 1214 SHIFT places. */ 1215 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ 1216 (((STRUCT) >> (SHIFT)) & (MASK)) 1217 1218 /* Extract the operand given by FIELD from mips_cl_insn INSN. */ 1219 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ 1220 (!(MICROMIPS) \ 1221 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ 1222 : EXTRACT_BITS ((INSN).insn_opcode, \ 1223 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) 1224 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ 1225 EXTRACT_BITS ((INSN).insn_opcode, \ 1226 MIPS16OP_MASK_##FIELD, \ 1227 MIPS16OP_SH_##FIELD) 1228 1229 /* The MIPS16 EXTEND opcode, shifted left 16 places. */ 1230 #define MIPS16_EXTEND (0xf000U << 16) 1231 1232 /* Whether or not we are emitting a branch-likely macro. */ 1234 static bfd_boolean emit_branch_likely_macro = FALSE; 1235 1236 /* Global variables used when generating relaxable macros. See the 1237 comment above RELAX_ENCODE for more details about how relaxation 1238 is used. */ 1239 static struct { 1240 /* 0 if we're not emitting a relaxable macro. 1241 1 if we're emitting the first of the two relaxation alternatives. 1242 2 if we're emitting the second alternative. */ 1243 int sequence; 1244 1245 /* The first relaxable fixup in the current frag. (In other words, 1246 the first fixup that refers to relaxable code.) */ 1247 fixS *first_fixup; 1248 1249 /* sizes[0] says how many bytes of the first alternative are stored in 1250 the current frag. Likewise sizes[1] for the second alternative. */ 1251 unsigned int sizes[2]; 1252 1253 /* The symbol on which the choice of sequence depends. */ 1254 symbolS *symbol; 1255 } mips_relax; 1256 1257 /* Global variables used to decide whether a macro needs a warning. */ 1259 static struct { 1260 /* True if the macro is in a branch delay slot. */ 1261 bfd_boolean delay_slot_p; 1262 1263 /* Set to the length in bytes required if the macro is in a delay slot 1264 that requires a specific length of instruction, otherwise zero. */ 1265 unsigned int delay_slot_length; 1266 1267 /* For relaxable macros, sizes[0] is the length of the first alternative 1268 in bytes and sizes[1] is the length of the second alternative. 1269 For non-relaxable macros, both elements give the length of the 1270 macro in bytes. */ 1271 unsigned int sizes[2]; 1272 1273 /* For relaxable macros, first_insn_sizes[0] is the length of the first 1274 instruction of the first alternative in bytes and first_insn_sizes[1] 1275 is the length of the first instruction of the second alternative. 1276 For non-relaxable macros, both elements give the length of the first 1277 instruction in bytes. 1278 1279 Set to zero if we haven't yet seen the first instruction. */ 1280 unsigned int first_insn_sizes[2]; 1281 1282 /* For relaxable macros, insns[0] is the number of instructions for the 1283 first alternative and insns[1] is the number of instructions for the 1284 second alternative. 1285 1286 For non-relaxable macros, both elements give the number of 1287 instructions for the macro. */ 1288 unsigned int insns[2]; 1289 1290 /* The first variant frag for this macro. */ 1291 fragS *first_frag; 1292 } mips_macro_warning; 1293 1294 /* Prototypes for static functions. */ 1296 1297 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; 1298 1299 static void append_insn 1300 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, 1301 bfd_boolean expansionp); 1302 static void mips_no_prev_insn (void); 1303 static void macro_build (expressionS *, const char *, const char *, ...); 1304 static void mips16_macro_build 1305 (expressionS *, const char *, const char *, va_list *); 1306 static void load_register (int, expressionS *, int); 1307 static void macro_start (void); 1308 static void macro_end (void); 1309 static void macro (struct mips_cl_insn *ip, char *str); 1310 static void mips16_macro (struct mips_cl_insn * ip); 1311 static void mips_ip (char *str, struct mips_cl_insn * ip); 1312 static void mips16_ip (char *str, struct mips_cl_insn * ip); 1313 static void mips16_immed 1314 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, 1315 unsigned int, unsigned long *); 1316 static size_t my_getSmallExpression 1317 (expressionS *, bfd_reloc_code_real_type *, char *); 1318 static void my_getExpression (expressionS *, char *); 1319 static void s_align (int); 1320 static void s_change_sec (int); 1321 static void s_change_section (int); 1322 static void s_cons (int); 1323 static void s_float_cons (int); 1324 static void s_mips_globl (int); 1325 static void s_option (int); 1326 static void s_mipsset (int); 1327 static void s_abicalls (int); 1328 static void s_cpload (int); 1329 static void s_cpsetup (int); 1330 static void s_cplocal (int); 1331 static void s_cprestore (int); 1332 static void s_cpreturn (int); 1333 static void s_dtprelword (int); 1334 static void s_dtpreldword (int); 1335 static void s_tprelword (int); 1336 static void s_tpreldword (int); 1337 static void s_gpvalue (int); 1338 static void s_gpword (int); 1339 static void s_gpdword (int); 1340 static void s_ehword (int); 1341 static void s_cpadd (int); 1342 static void s_insn (int); 1343 static void s_nan (int); 1344 static void s_module (int); 1345 static void s_mips_ent (int); 1346 static void s_mips_end (int); 1347 static void s_mips_frame (int); 1348 static void s_mips_mask (int reg_type); 1349 static void s_mips_stab (int); 1350 static void s_mips_weakext (int); 1351 static void s_mips_file (int); 1352 static void s_mips_loc (int); 1353 static bfd_boolean pic_need_relax (symbolS *, asection *); 1354 static int relaxed_branch_length (fragS *, asection *, int); 1355 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); 1356 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); 1357 static void file_mips_check_options (void); 1358 1359 /* Table and functions used to map between CPU/ISA names, and 1360 ISA levels, and CPU numbers. */ 1361 1362 struct mips_cpu_info 1363 { 1364 const char *name; /* CPU or ISA name. */ 1365 int flags; /* MIPS_CPU_* flags. */ 1366 int ase; /* Set of ASEs implemented by the CPU. */ 1367 int isa; /* ISA level. */ 1368 int cpu; /* CPU number (default CPU if ISA). */ 1369 }; 1370 1371 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ 1372 1373 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); 1374 static const struct mips_cpu_info *mips_cpu_info_from_isa (int); 1375 static const struct mips_cpu_info *mips_cpu_info_from_arch (int); 1376 1377 /* Command-line options. */ 1379 const char *md_shortopts = "O::g::G:"; 1380 1381 enum options 1382 { 1383 OPTION_MARCH = OPTION_MD_BASE, 1384 OPTION_MTUNE, 1385 OPTION_MIPS1, 1386 OPTION_MIPS2, 1387 OPTION_MIPS3, 1388 OPTION_MIPS4, 1389 OPTION_MIPS5, 1390 OPTION_MIPS32, 1391 OPTION_MIPS64, 1392 OPTION_MIPS32R2, 1393 OPTION_MIPS32R3, 1394 OPTION_MIPS32R5, 1395 OPTION_MIPS32R6, 1396 OPTION_MIPS64R2, 1397 OPTION_MIPS64R3, 1398 OPTION_MIPS64R5, 1399 OPTION_MIPS64R6, 1400 OPTION_MIPS16, 1401 OPTION_NO_MIPS16, 1402 OPTION_MIPS3D, 1403 OPTION_NO_MIPS3D, 1404 OPTION_MDMX, 1405 OPTION_NO_MDMX, 1406 OPTION_DSP, 1407 OPTION_NO_DSP, 1408 OPTION_MT, 1409 OPTION_NO_MT, 1410 OPTION_VIRT, 1411 OPTION_NO_VIRT, 1412 OPTION_MSA, 1413 OPTION_NO_MSA, 1414 OPTION_SMARTMIPS, 1415 OPTION_NO_SMARTMIPS, 1416 OPTION_DSPR2, 1417 OPTION_NO_DSPR2, 1418 OPTION_DSPR3, 1419 OPTION_NO_DSPR3, 1420 OPTION_EVA, 1421 OPTION_NO_EVA, 1422 OPTION_XPA, 1423 OPTION_NO_XPA, 1424 OPTION_MICROMIPS, 1425 OPTION_NO_MICROMIPS, 1426 OPTION_MCU, 1427 OPTION_NO_MCU, 1428 OPTION_COMPAT_ARCH_BASE, 1429 OPTION_M4650, 1430 OPTION_NO_M4650, 1431 OPTION_M4010, 1432 OPTION_NO_M4010, 1433 OPTION_M4100, 1434 OPTION_NO_M4100, 1435 OPTION_M3900, 1436 OPTION_NO_M3900, 1437 OPTION_M7000_HILO_FIX, 1438 OPTION_MNO_7000_HILO_FIX, 1439 OPTION_FIX_24K, 1440 OPTION_NO_FIX_24K, 1441 OPTION_FIX_RM7000, 1442 OPTION_NO_FIX_RM7000, 1443 OPTION_FIX_LOONGSON2F_JUMP, 1444 OPTION_NO_FIX_LOONGSON2F_JUMP, 1445 OPTION_FIX_LOONGSON2F_NOP, 1446 OPTION_NO_FIX_LOONGSON2F_NOP, 1447 OPTION_FIX_VR4120, 1448 OPTION_NO_FIX_VR4120, 1449 OPTION_FIX_VR4130, 1450 OPTION_NO_FIX_VR4130, 1451 OPTION_FIX_CN63XXP1, 1452 OPTION_NO_FIX_CN63XXP1, 1453 OPTION_TRAP, 1454 OPTION_BREAK, 1455 OPTION_EB, 1456 OPTION_EL, 1457 OPTION_FP32, 1458 OPTION_GP32, 1459 OPTION_CONSTRUCT_FLOATS, 1460 OPTION_NO_CONSTRUCT_FLOATS, 1461 OPTION_FP64, 1462 OPTION_FPXX, 1463 OPTION_GP64, 1464 OPTION_RELAX_BRANCH, 1465 OPTION_NO_RELAX_BRANCH, 1466 OPTION_INSN32, 1467 OPTION_NO_INSN32, 1468 OPTION_MSHARED, 1469 OPTION_MNO_SHARED, 1470 OPTION_MSYM32, 1471 OPTION_MNO_SYM32, 1472 OPTION_SOFT_FLOAT, 1473 OPTION_HARD_FLOAT, 1474 OPTION_SINGLE_FLOAT, 1475 OPTION_DOUBLE_FLOAT, 1476 OPTION_32, 1477 OPTION_CALL_SHARED, 1478 OPTION_CALL_NONPIC, 1479 OPTION_NON_SHARED, 1480 OPTION_XGOT, 1481 OPTION_MABI, 1482 OPTION_N32, 1483 OPTION_64, 1484 OPTION_MDEBUG, 1485 OPTION_NO_MDEBUG, 1486 OPTION_PDR, 1487 OPTION_NO_PDR, 1488 OPTION_MVXWORKS_PIC, 1489 OPTION_NAN, 1490 OPTION_ODD_SPREG, 1491 OPTION_NO_ODD_SPREG, 1492 OPTION_END_OF_ENUM 1493 }; 1494 1495 struct option md_longopts[] = 1496 { 1497 /* Options which specify architecture. */ 1498 {"march", required_argument, NULL, OPTION_MARCH}, 1499 {"mtune", required_argument, NULL, OPTION_MTUNE}, 1500 {"mips0", no_argument, NULL, OPTION_MIPS1}, 1501 {"mips1", no_argument, NULL, OPTION_MIPS1}, 1502 {"mips2", no_argument, NULL, OPTION_MIPS2}, 1503 {"mips3", no_argument, NULL, OPTION_MIPS3}, 1504 {"mips4", no_argument, NULL, OPTION_MIPS4}, 1505 {"mips5", no_argument, NULL, OPTION_MIPS5}, 1506 {"mips32", no_argument, NULL, OPTION_MIPS32}, 1507 {"mips64", no_argument, NULL, OPTION_MIPS64}, 1508 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, 1509 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, 1510 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, 1511 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, 1512 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, 1513 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, 1514 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, 1515 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, 1516 1517 /* Options which specify Application Specific Extensions (ASEs). */ 1518 {"mips16", no_argument, NULL, OPTION_MIPS16}, 1519 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, 1520 {"mips3d", no_argument, NULL, OPTION_MIPS3D}, 1521 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, 1522 {"mdmx", no_argument, NULL, OPTION_MDMX}, 1523 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, 1524 {"mdsp", no_argument, NULL, OPTION_DSP}, 1525 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, 1526 {"mmt", no_argument, NULL, OPTION_MT}, 1527 {"mno-mt", no_argument, NULL, OPTION_NO_MT}, 1528 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, 1529 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, 1530 {"mdspr2", no_argument, NULL, OPTION_DSPR2}, 1531 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, 1532 {"mdspr3", no_argument, NULL, OPTION_DSPR3}, 1533 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, 1534 {"meva", no_argument, NULL, OPTION_EVA}, 1535 {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, 1536 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, 1537 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, 1538 {"mmcu", no_argument, NULL, OPTION_MCU}, 1539 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, 1540 {"mvirt", no_argument, NULL, OPTION_VIRT}, 1541 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, 1542 {"mmsa", no_argument, NULL, OPTION_MSA}, 1543 {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, 1544 {"mxpa", no_argument, NULL, OPTION_XPA}, 1545 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, 1546 1547 /* Old-style architecture options. Don't add more of these. */ 1548 {"m4650", no_argument, NULL, OPTION_M4650}, 1549 {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, 1550 {"m4010", no_argument, NULL, OPTION_M4010}, 1551 {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, 1552 {"m4100", no_argument, NULL, OPTION_M4100}, 1553 {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, 1554 {"m3900", no_argument, NULL, OPTION_M3900}, 1555 {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, 1556 1557 /* Options which enable bug fixes. */ 1558 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, 1559 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1560 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1561 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, 1562 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, 1563 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, 1564 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, 1565 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 1566 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 1567 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, 1568 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, 1569 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, 1570 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, 1571 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, 1572 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, 1573 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, 1574 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, 1575 1576 /* Miscellaneous options. */ 1577 {"trap", no_argument, NULL, OPTION_TRAP}, 1578 {"no-break", no_argument, NULL, OPTION_TRAP}, 1579 {"break", no_argument, NULL, OPTION_BREAK}, 1580 {"no-trap", no_argument, NULL, OPTION_BREAK}, 1581 {"EB", no_argument, NULL, OPTION_EB}, 1582 {"EL", no_argument, NULL, OPTION_EL}, 1583 {"mfp32", no_argument, NULL, OPTION_FP32}, 1584 {"mgp32", no_argument, NULL, OPTION_GP32}, 1585 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, 1586 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, 1587 {"mfp64", no_argument, NULL, OPTION_FP64}, 1588 {"mfpxx", no_argument, NULL, OPTION_FPXX}, 1589 {"mgp64", no_argument, NULL, OPTION_GP64}, 1590 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, 1591 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, 1592 {"minsn32", no_argument, NULL, OPTION_INSN32}, 1593 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, 1594 {"mshared", no_argument, NULL, OPTION_MSHARED}, 1595 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, 1596 {"msym32", no_argument, NULL, OPTION_MSYM32}, 1597 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, 1598 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, 1599 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, 1600 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, 1601 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, 1602 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, 1603 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, 1604 1605 /* Strictly speaking this next option is ELF specific, 1606 but we allow it for other ports as well in order to 1607 make testing easier. */ 1608 {"32", no_argument, NULL, OPTION_32}, 1609 1610 /* ELF-specific options. */ 1611 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 1612 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, 1613 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, 1614 {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, 1615 {"xgot", no_argument, NULL, OPTION_XGOT}, 1616 {"mabi", required_argument, NULL, OPTION_MABI}, 1617 {"n32", no_argument, NULL, OPTION_N32}, 1618 {"64", no_argument, NULL, OPTION_64}, 1619 {"mdebug", no_argument, NULL, OPTION_MDEBUG}, 1620 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, 1621 {"mpdr", no_argument, NULL, OPTION_PDR}, 1622 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, 1623 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, 1624 {"mnan", required_argument, NULL, OPTION_NAN}, 1625 1626 {NULL, no_argument, NULL, 0} 1627 }; 1628 size_t md_longopts_size = sizeof (md_longopts); 1629 1630 /* Information about either an Application Specific Extension or an 1632 optional architecture feature that, for simplicity, we treat in the 1633 same way as an ASE. */ 1634 struct mips_ase 1635 { 1636 /* The name of the ASE, used in both the command-line and .set options. */ 1637 const char *name; 1638 1639 /* The associated ASE_* flags. If the ASE is available on both 32-bit 1640 and 64-bit architectures, the flags here refer to the subset that 1641 is available on both. */ 1642 unsigned int flags; 1643 1644 /* The ASE_* flag used for instructions that are available on 64-bit 1645 architectures but that are not included in FLAGS. */ 1646 unsigned int flags64; 1647 1648 /* The command-line options that turn the ASE on and off. */ 1649 int option_on; 1650 int option_off; 1651 1652 /* The minimum required architecture revisions for MIPS32, MIPS64, 1653 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ 1654 int mips32_rev; 1655 int mips64_rev; 1656 int micromips32_rev; 1657 int micromips64_rev; 1658 1659 /* The architecture where the ASE was removed or -1 if the extension has not 1660 been removed. */ 1661 int rem_rev; 1662 }; 1663 1664 /* A table of all supported ASEs. */ 1665 static const struct mips_ase mips_ases[] = { 1666 { "dsp", ASE_DSP, ASE_DSP64, 1667 OPTION_DSP, OPTION_NO_DSP, 1668 2, 2, 2, 2, 1669 -1 }, 1670 1671 { "dspr2", ASE_DSP | ASE_DSPR2, 0, 1672 OPTION_DSPR2, OPTION_NO_DSPR2, 1673 2, 2, 2, 2, 1674 -1 }, 1675 1676 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, 1677 OPTION_DSPR3, OPTION_NO_DSPR3, 1678 6, 6, -1, -1, 1679 -1 }, 1680 1681 { "eva", ASE_EVA, 0, 1682 OPTION_EVA, OPTION_NO_EVA, 1683 2, 2, 2, 2, 1684 -1 }, 1685 1686 { "mcu", ASE_MCU, 0, 1687 OPTION_MCU, OPTION_NO_MCU, 1688 2, 2, 2, 2, 1689 -1 }, 1690 1691 /* Deprecated in MIPS64r5, but we don't implement that yet. */ 1692 { "mdmx", ASE_MDMX, 0, 1693 OPTION_MDMX, OPTION_NO_MDMX, 1694 -1, 1, -1, -1, 1695 6 }, 1696 1697 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ 1698 { "mips3d", ASE_MIPS3D, 0, 1699 OPTION_MIPS3D, OPTION_NO_MIPS3D, 1700 2, 1, -1, -1, 1701 6 }, 1702 1703 { "mt", ASE_MT, 0, 1704 OPTION_MT, OPTION_NO_MT, 1705 2, 2, -1, -1, 1706 -1 }, 1707 1708 { "smartmips", ASE_SMARTMIPS, 0, 1709 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, 1710 1, -1, -1, -1, 1711 6 }, 1712 1713 { "virt", ASE_VIRT, ASE_VIRT64, 1714 OPTION_VIRT, OPTION_NO_VIRT, 1715 2, 2, 2, 2, 1716 -1 }, 1717 1718 { "msa", ASE_MSA, ASE_MSA64, 1719 OPTION_MSA, OPTION_NO_MSA, 1720 2, 2, 2, 2, 1721 -1 }, 1722 1723 { "xpa", ASE_XPA, 0, 1724 OPTION_XPA, OPTION_NO_XPA, 1725 2, 2, -1, -1, 1726 -1 }, 1727 }; 1728 1729 /* The set of ASEs that require -mfp64. */ 1730 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) 1731 1732 /* Groups of ASE_* flags that represent different revisions of an ASE. */ 1733 static const unsigned int mips_ase_groups[] = { 1734 ASE_DSP | ASE_DSPR2 | ASE_DSPR3 1735 }; 1736 1737 /* Pseudo-op table. 1739 1740 The following pseudo-ops from the Kane and Heinrich MIPS book 1741 should be defined here, but are currently unsupported: .alias, 1742 .galive, .gjaldef, .gjrlive, .livereg, .noalias. 1743 1744 The following pseudo-ops from the Kane and Heinrich MIPS book are 1745 specific to the type of debugging information being generated, and 1746 should be defined by the object format: .aent, .begin, .bend, 1747 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, 1748 .vreg. 1749 1750 The following pseudo-ops from the Kane and Heinrich MIPS book are 1751 not MIPS CPU specific, but are also not specific to the object file 1752 format. This file is probably the best place to define them, but 1753 they are not currently supported: .asm0, .endr, .lab, .struct. */ 1754 1755 static const pseudo_typeS mips_pseudo_table[] = 1756 { 1757 /* MIPS specific pseudo-ops. */ 1758 {"option", s_option, 0}, 1759 {"set", s_mipsset, 0}, 1760 {"rdata", s_change_sec, 'r'}, 1761 {"sdata", s_change_sec, 's'}, 1762 {"livereg", s_ignore, 0}, 1763 {"abicalls", s_abicalls, 0}, 1764 {"cpload", s_cpload, 0}, 1765 {"cpsetup", s_cpsetup, 0}, 1766 {"cplocal", s_cplocal, 0}, 1767 {"cprestore", s_cprestore, 0}, 1768 {"cpreturn", s_cpreturn, 0}, 1769 {"dtprelword", s_dtprelword, 0}, 1770 {"dtpreldword", s_dtpreldword, 0}, 1771 {"tprelword", s_tprelword, 0}, 1772 {"tpreldword", s_tpreldword, 0}, 1773 {"gpvalue", s_gpvalue, 0}, 1774 {"gpword", s_gpword, 0}, 1775 {"gpdword", s_gpdword, 0}, 1776 {"ehword", s_ehword, 0}, 1777 {"cpadd", s_cpadd, 0}, 1778 {"insn", s_insn, 0}, 1779 {"nan", s_nan, 0}, 1780 {"module", s_module, 0}, 1781 1782 /* Relatively generic pseudo-ops that happen to be used on MIPS 1783 chips. */ 1784 {"asciiz", stringer, 8 + 1}, 1785 {"bss", s_change_sec, 'b'}, 1786 {"err", s_err, 0}, 1787 {"half", s_cons, 1}, 1788 {"dword", s_cons, 3}, 1789 {"weakext", s_mips_weakext, 0}, 1790 {"origin", s_org, 0}, 1791 {"repeat", s_rept, 0}, 1792 1793 /* For MIPS this is non-standard, but we define it for consistency. */ 1794 {"sbss", s_change_sec, 'B'}, 1795 1796 /* These pseudo-ops are defined in read.c, but must be overridden 1797 here for one reason or another. */ 1798 {"align", s_align, 0}, 1799 {"byte", s_cons, 0}, 1800 {"data", s_change_sec, 'd'}, 1801 {"double", s_float_cons, 'd'}, 1802 {"float", s_float_cons, 'f'}, 1803 {"globl", s_mips_globl, 0}, 1804 {"global", s_mips_globl, 0}, 1805 {"hword", s_cons, 1}, 1806 {"int", s_cons, 2}, 1807 {"long", s_cons, 2}, 1808 {"octa", s_cons, 4}, 1809 {"quad", s_cons, 3}, 1810 {"section", s_change_section, 0}, 1811 {"short", s_cons, 1}, 1812 {"single", s_float_cons, 'f'}, 1813 {"stabd", s_mips_stab, 'd'}, 1814 {"stabn", s_mips_stab, 'n'}, 1815 {"stabs", s_mips_stab, 's'}, 1816 {"text", s_change_sec, 't'}, 1817 {"word", s_cons, 2}, 1818 1819 { "extern", ecoff_directive_extern, 0}, 1820 1821 { NULL, NULL, 0 }, 1822 }; 1823 1824 static const pseudo_typeS mips_nonecoff_pseudo_table[] = 1825 { 1826 /* These pseudo-ops should be defined by the object file format. 1827 However, a.out doesn't support them, so we have versions here. */ 1828 {"aent", s_mips_ent, 1}, 1829 {"bgnb", s_ignore, 0}, 1830 {"end", s_mips_end, 0}, 1831 {"endb", s_ignore, 0}, 1832 {"ent", s_mips_ent, 0}, 1833 {"file", s_mips_file, 0}, 1834 {"fmask", s_mips_mask, 'F'}, 1835 {"frame", s_mips_frame, 0}, 1836 {"loc", s_mips_loc, 0}, 1837 {"mask", s_mips_mask, 'R'}, 1838 {"verstamp", s_ignore, 0}, 1839 { NULL, NULL, 0 }, 1840 }; 1841 1842 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the 1843 purpose of the `.dc.a' internal pseudo-op. */ 1844 1845 int 1846 mips_address_bytes (void) 1847 { 1848 file_mips_check_options (); 1849 return HAVE_64BIT_ADDRESSES ? 8 : 4; 1850 } 1851 1852 extern void pop_insert (const pseudo_typeS *); 1853 1854 void 1855 mips_pop_insert (void) 1856 { 1857 pop_insert (mips_pseudo_table); 1858 if (! ECOFF_DEBUGGING) 1859 pop_insert (mips_nonecoff_pseudo_table); 1860 } 1861 1862 /* Symbols labelling the current insn. */ 1864 1865 struct insn_label_list 1866 { 1867 struct insn_label_list *next; 1868 symbolS *label; 1869 }; 1870 1871 static struct insn_label_list *free_insn_labels; 1872 #define label_list tc_segment_info_data.labels 1873 1874 static void mips_clear_insn_labels (void); 1875 static void mips_mark_labels (void); 1876 static void mips_compressed_mark_labels (void); 1877 1878 static inline void 1879 mips_clear_insn_labels (void) 1880 { 1881 struct insn_label_list **pl; 1882 segment_info_type *si; 1883 1884 if (now_seg) 1885 { 1886 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 1887 ; 1888 1889 si = seg_info (now_seg); 1890 *pl = si->label_list; 1891 si->label_list = NULL; 1892 } 1893 } 1894 1895 /* Mark instruction labels in MIPS16/microMIPS mode. */ 1896 1897 static inline void 1898 mips_mark_labels (void) 1899 { 1900 if (HAVE_CODE_COMPRESSION) 1901 mips_compressed_mark_labels (); 1902 } 1903 1904 static char *expr_end; 1906 1907 /* An expression in a macro instruction. This is set by mips_ip and 1908 mips16_ip and when populated is always an O_constant. */ 1909 1910 static expressionS imm_expr; 1911 1912 /* The relocatable field in an instruction and the relocs associated 1913 with it. These variables are used for instructions like LUI and 1914 JAL as well as true offsets. They are also used for address 1915 operands in macros. */ 1916 1917 static expressionS offset_expr; 1918 static bfd_reloc_code_real_type offset_reloc[3] 1919 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1920 1921 /* This is set to the resulting size of the instruction to be produced 1922 by mips16_ip if an explicit extension is used or by mips_ip if an 1923 explicit size is supplied. */ 1924 1925 static unsigned int forced_insn_length; 1926 1927 /* True if we are assembling an instruction. All dot symbols defined during 1928 this time should be treated as code labels. */ 1929 1930 static bfd_boolean mips_assembling_insn; 1931 1932 /* The pdr segment for per procedure frame/regmask info. Not used for 1933 ECOFF debugging. */ 1934 1935 static segT pdr_seg; 1936 1937 /* The default target format to use. */ 1938 1939 #if defined (TE_FreeBSD) 1940 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" 1941 #elif defined (TE_TMIPS) 1942 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" 1943 #else 1944 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" 1945 #endif 1946 1947 const char * 1948 mips_target_format (void) 1949 { 1950 switch (OUTPUT_FLAVOR) 1951 { 1952 case bfd_target_elf_flavour: 1953 #ifdef TE_VXWORKS 1954 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) 1955 return (target_big_endian 1956 ? "elf32-bigmips-vxworks" 1957 : "elf32-littlemips-vxworks"); 1958 #endif 1959 return (target_big_endian 1960 ? (HAVE_64BIT_OBJECTS 1961 ? ELF_TARGET ("elf64-", "big") 1962 : (HAVE_NEWABI 1963 ? ELF_TARGET ("elf32-n", "big") 1964 : ELF_TARGET ("elf32-", "big"))) 1965 : (HAVE_64BIT_OBJECTS 1966 ? ELF_TARGET ("elf64-", "little") 1967 : (HAVE_NEWABI 1968 ? ELF_TARGET ("elf32-n", "little") 1969 : ELF_TARGET ("elf32-", "little")))); 1970 default: 1971 abort (); 1972 return NULL; 1973 } 1974 } 1975 1976 /* Return the ISA revision that is currently in use, or 0 if we are 1977 generating code for MIPS V or below. */ 1978 1979 static int 1980 mips_isa_rev (void) 1981 { 1982 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) 1983 return 2; 1984 1985 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) 1986 return 3; 1987 1988 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) 1989 return 5; 1990 1991 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) 1992 return 6; 1993 1994 /* microMIPS implies revision 2 or above. */ 1995 if (mips_opts.micromips) 1996 return 2; 1997 1998 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) 1999 return 1; 2000 2001 return 0; 2002 } 2003 2004 /* Return the mask of all ASEs that are revisions of those in FLAGS. */ 2005 2006 static unsigned int 2007 mips_ase_mask (unsigned int flags) 2008 { 2009 unsigned int i; 2010 2011 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) 2012 if (flags & mips_ase_groups[i]) 2013 flags |= mips_ase_groups[i]; 2014 return flags; 2015 } 2016 2017 /* Check whether the current ISA supports ASE. Issue a warning if 2018 appropriate. */ 2019 2020 static void 2021 mips_check_isa_supports_ase (const struct mips_ase *ase) 2022 { 2023 const char *base; 2024 int min_rev, size; 2025 static unsigned int warned_isa; 2026 static unsigned int warned_fp32; 2027 2028 if (ISA_HAS_64BIT_REGS (mips_opts.isa)) 2029 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; 2030 else 2031 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; 2032 if ((min_rev < 0 || mips_isa_rev () < min_rev) 2033 && (warned_isa & ase->flags) != ase->flags) 2034 { 2035 warned_isa |= ase->flags; 2036 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2037 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2038 if (min_rev < 0) 2039 as_warn (_("the %d-bit %s architecture does not support the" 2040 " `%s' extension"), size, base, ase->name); 2041 else 2042 as_warn (_("the `%s' extension requires %s%d revision %d or greater"), 2043 ase->name, base, size, min_rev); 2044 } 2045 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) 2046 && (warned_isa & ase->flags) != ase->flags) 2047 { 2048 warned_isa |= ase->flags; 2049 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2050 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2051 as_warn (_("the `%s' extension was removed in %s%d revision %d"), 2052 ase->name, base, size, ase->rem_rev); 2053 } 2054 2055 if ((ase->flags & FP64_ASES) 2056 && mips_opts.fp != 64 2057 && (warned_fp32 & ase->flags) != ase->flags) 2058 { 2059 warned_fp32 |= ase->flags; 2060 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); 2061 } 2062 } 2063 2064 /* Check all enabled ASEs to see whether they are supported by the 2065 chosen architecture. */ 2066 2067 static void 2068 mips_check_isa_supports_ases (void) 2069 { 2070 unsigned int i, mask; 2071 2072 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2073 { 2074 mask = mips_ase_mask (mips_ases[i].flags); 2075 if ((mips_opts.ase & mask) == mips_ases[i].flags) 2076 mips_check_isa_supports_ase (&mips_ases[i]); 2077 } 2078 } 2079 2080 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags 2081 that were affected. */ 2082 2083 static unsigned int 2084 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, 2085 bfd_boolean enabled_p) 2086 { 2087 unsigned int mask; 2088 2089 mask = mips_ase_mask (ase->flags); 2090 opts->ase &= ~mask; 2091 if (enabled_p) 2092 opts->ase |= ase->flags; 2093 return mask; 2094 } 2095 2096 /* Return the ASE called NAME, or null if none. */ 2097 2098 static const struct mips_ase * 2099 mips_lookup_ase (const char *name) 2100 { 2101 unsigned int i; 2102 2103 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2104 if (strcmp (name, mips_ases[i].name) == 0) 2105 return &mips_ases[i]; 2106 return NULL; 2107 } 2108 2109 /* Return the length of a microMIPS instruction in bytes. If bits of 2110 the mask beyond the low 16 are 0, then it is a 16-bit instruction, 2111 otherwise it is a 32-bit instruction. */ 2112 2113 static inline unsigned int 2114 micromips_insn_length (const struct mips_opcode *mo) 2115 { 2116 return (mo->mask >> 16) == 0 ? 2 : 4; 2117 } 2118 2119 /* Return the length of MIPS16 instruction OPCODE. */ 2120 2121 static inline unsigned int 2122 mips16_opcode_length (unsigned long opcode) 2123 { 2124 return (opcode >> 16) == 0 ? 2 : 4; 2125 } 2126 2127 /* Return the length of instruction INSN. */ 2128 2129 static inline unsigned int 2130 insn_length (const struct mips_cl_insn *insn) 2131 { 2132 if (mips_opts.micromips) 2133 return micromips_insn_length (insn->insn_mo); 2134 else if (mips_opts.mips16) 2135 return mips16_opcode_length (insn->insn_opcode); 2136 else 2137 return 4; 2138 } 2139 2140 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 2141 2142 static void 2143 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) 2144 { 2145 size_t i; 2146 2147 insn->insn_mo = mo; 2148 insn->insn_opcode = mo->match; 2149 insn->frag = NULL; 2150 insn->where = 0; 2151 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2152 insn->fixp[i] = NULL; 2153 insn->fixed_p = (mips_opts.noreorder > 0); 2154 insn->noreorder_p = (mips_opts.noreorder > 0); 2155 insn->mips16_absolute_jump_p = 0; 2156 insn->complete_p = 0; 2157 insn->cleared_p = 0; 2158 } 2159 2160 /* Get a list of all the operands in INSN. */ 2161 2162 static const struct mips_operand_array * 2163 insn_operands (const struct mips_cl_insn *insn) 2164 { 2165 if (insn->insn_mo >= &mips_opcodes[0] 2166 && insn->insn_mo < &mips_opcodes[NUMOPCODES]) 2167 return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; 2168 2169 if (insn->insn_mo >= &mips16_opcodes[0] 2170 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) 2171 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; 2172 2173 if (insn->insn_mo >= µmips_opcodes[0] 2174 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) 2175 return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; 2176 2177 abort (); 2178 } 2179 2180 /* Get a description of operand OPNO of INSN. */ 2181 2182 static const struct mips_operand * 2183 insn_opno (const struct mips_cl_insn *insn, unsigned opno) 2184 { 2185 const struct mips_operand_array *operands; 2186 2187 operands = insn_operands (insn); 2188 if (opno >= MAX_OPERANDS || !operands->operand[opno]) 2189 abort (); 2190 return operands->operand[opno]; 2191 } 2192 2193 /* Install UVAL as the value of OPERAND in INSN. */ 2194 2195 static inline void 2196 insn_insert_operand (struct mips_cl_insn *insn, 2197 const struct mips_operand *operand, unsigned int uval) 2198 { 2199 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); 2200 } 2201 2202 /* Extract the value of OPERAND from INSN. */ 2203 2204 static inline unsigned 2205 insn_extract_operand (const struct mips_cl_insn *insn, 2206 const struct mips_operand *operand) 2207 { 2208 return mips_extract_operand (operand, insn->insn_opcode); 2209 } 2210 2211 /* Record the current MIPS16/microMIPS mode in now_seg. */ 2212 2213 static void 2214 mips_record_compressed_mode (void) 2215 { 2216 segment_info_type *si; 2217 2218 si = seg_info (now_seg); 2219 if (si->tc_segment_info_data.mips16 != mips_opts.mips16) 2220 si->tc_segment_info_data.mips16 = mips_opts.mips16; 2221 if (si->tc_segment_info_data.micromips != mips_opts.micromips) 2222 si->tc_segment_info_data.micromips = mips_opts.micromips; 2223 } 2224 2225 /* Read a standard MIPS instruction from BUF. */ 2226 2227 static unsigned long 2228 read_insn (char *buf) 2229 { 2230 if (target_big_endian) 2231 return bfd_getb32 ((bfd_byte *) buf); 2232 else 2233 return bfd_getl32 ((bfd_byte *) buf); 2234 } 2235 2236 /* Write standard MIPS instruction INSN to BUF. Return a pointer to 2237 the next byte. */ 2238 2239 static char * 2240 write_insn (char *buf, unsigned int insn) 2241 { 2242 md_number_to_chars (buf, insn, 4); 2243 return buf + 4; 2244 } 2245 2246 /* Read a microMIPS or MIPS16 opcode from BUF, given that it 2247 has length LENGTH. */ 2248 2249 static unsigned long 2250 read_compressed_insn (char *buf, unsigned int length) 2251 { 2252 unsigned long insn; 2253 unsigned int i; 2254 2255 insn = 0; 2256 for (i = 0; i < length; i += 2) 2257 { 2258 insn <<= 16; 2259 if (target_big_endian) 2260 insn |= bfd_getb16 ((char *) buf); 2261 else 2262 insn |= bfd_getl16 ((char *) buf); 2263 buf += 2; 2264 } 2265 return insn; 2266 } 2267 2268 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the 2269 instruction is LENGTH bytes long. Return a pointer to the next byte. */ 2270 2271 static char * 2272 write_compressed_insn (char *buf, unsigned int insn, unsigned int length) 2273 { 2274 unsigned int i; 2275 2276 for (i = 0; i < length; i += 2) 2277 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); 2278 return buf + length; 2279 } 2280 2281 /* Install INSN at the location specified by its "frag" and "where" fields. */ 2282 2283 static void 2284 install_insn (const struct mips_cl_insn *insn) 2285 { 2286 char *f = insn->frag->fr_literal + insn->where; 2287 if (HAVE_CODE_COMPRESSION) 2288 write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); 2289 else 2290 write_insn (f, insn->insn_opcode); 2291 mips_record_compressed_mode (); 2292 } 2293 2294 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 2295 and install the opcode in the new location. */ 2296 2297 static void 2298 move_insn (struct mips_cl_insn *insn, fragS *frag, long where) 2299 { 2300 size_t i; 2301 2302 insn->frag = frag; 2303 insn->where = where; 2304 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2305 if (insn->fixp[i] != NULL) 2306 { 2307 insn->fixp[i]->fx_frag = frag; 2308 insn->fixp[i]->fx_where = where; 2309 } 2310 install_insn (insn); 2311 } 2312 2313 /* Add INSN to the end of the output. */ 2314 2315 static void 2316 add_fixed_insn (struct mips_cl_insn *insn) 2317 { 2318 char *f = frag_more (insn_length (insn)); 2319 move_insn (insn, frag_now, f - frag_now->fr_literal); 2320 } 2321 2322 /* Start a variant frag and move INSN to the start of the variant part, 2323 marking it as fixed. The other arguments are as for frag_var. */ 2324 2325 static void 2326 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, 2327 relax_substateT subtype, symbolS *symbol, offsetT offset) 2328 { 2329 frag_grow (max_chars); 2330 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 2331 insn->fixed_p = 1; 2332 frag_var (rs_machine_dependent, max_chars, var, 2333 subtype, symbol, offset, NULL); 2334 } 2335 2336 /* Insert N copies of INSN into the history buffer, starting at 2337 position FIRST. Neither FIRST nor N need to be clipped. */ 2338 2339 static void 2340 insert_into_history (unsigned int first, unsigned int n, 2341 const struct mips_cl_insn *insn) 2342 { 2343 if (mips_relax.sequence != 2) 2344 { 2345 unsigned int i; 2346 2347 for (i = ARRAY_SIZE (history); i-- > first;) 2348 if (i >= first + n) 2349 history[i] = history[i - n]; 2350 else 2351 history[i] = *insn; 2352 } 2353 } 2354 2355 /* Clear the error in insn_error. */ 2356 2357 static void 2358 clear_insn_error (void) 2359 { 2360 memset (&insn_error, 0, sizeof (insn_error)); 2361 } 2362 2363 /* Possibly record error message MSG for the current instruction. 2364 If the error is about a particular argument, ARGNUM is the 1-based 2365 number of that argument, otherwise it is 0. FORMAT is the format 2366 of MSG. Return true if MSG was used, false if the current message 2367 was kept. */ 2368 2369 static bfd_boolean 2370 set_insn_error_format (int argnum, enum mips_insn_error_format format, 2371 const char *msg) 2372 { 2373 if (argnum == 0) 2374 { 2375 /* Give priority to errors against specific arguments, and to 2376 the first whole-instruction message. */ 2377 if (insn_error.msg) 2378 return FALSE; 2379 } 2380 else 2381 { 2382 /* Keep insn_error if it is against a later argument. */ 2383 if (argnum < insn_error.min_argnum) 2384 return FALSE; 2385 2386 /* If both errors are against the same argument but are different, 2387 give up on reporting a specific error for this argument. 2388 See the comment about mips_insn_error for details. */ 2389 if (argnum == insn_error.min_argnum 2390 && insn_error.msg 2391 && strcmp (insn_error.msg, msg) != 0) 2392 { 2393 insn_error.msg = 0; 2394 insn_error.min_argnum += 1; 2395 return FALSE; 2396 } 2397 } 2398 insn_error.min_argnum = argnum; 2399 insn_error.format = format; 2400 insn_error.msg = msg; 2401 return TRUE; 2402 } 2403 2404 /* Record an instruction error with no % format fields. ARGNUM and MSG are 2405 as for set_insn_error_format. */ 2406 2407 static void 2408 set_insn_error (int argnum, const char *msg) 2409 { 2410 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); 2411 } 2412 2413 /* Record an instruction error with one %d field I. ARGNUM and MSG are 2414 as for set_insn_error_format. */ 2415 2416 static void 2417 set_insn_error_i (int argnum, const char *msg, int i) 2418 { 2419 if (set_insn_error_format (argnum, ERR_FMT_I, msg)) 2420 insn_error.u.i = i; 2421 } 2422 2423 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG 2424 are as for set_insn_error_format. */ 2425 2426 static void 2427 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) 2428 { 2429 if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) 2430 { 2431 insn_error.u.ss[0] = s1; 2432 insn_error.u.ss[1] = s2; 2433 } 2434 } 2435 2436 /* Report the error in insn_error, which is against assembly code STR. */ 2437 2438 static void 2439 report_insn_error (const char *str) 2440 { 2441 const char *msg = concat (insn_error.msg, " `%s'", NULL); 2442 2443 switch (insn_error.format) 2444 { 2445 case ERR_FMT_PLAIN: 2446 as_bad (msg, str); 2447 break; 2448 2449 case ERR_FMT_I: 2450 as_bad (msg, insn_error.u.i, str); 2451 break; 2452 2453 case ERR_FMT_SS: 2454 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); 2455 break; 2456 } 2457 2458 free ((char *) msg); 2459 } 2460 2461 /* Initialize vr4120_conflicts. There is a bit of duplication here: 2462 the idea is to make it obvious at a glance that each errata is 2463 included. */ 2464 2465 static void 2466 init_vr4120_conflicts (void) 2467 { 2468 #define CONFLICT(FIRST, SECOND) \ 2469 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND 2470 2471 /* Errata 21 - [D]DIV[U] after [D]MACC */ 2472 CONFLICT (MACC, DIV); 2473 CONFLICT (DMACC, DIV); 2474 2475 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ 2476 CONFLICT (DMULT, DMULT); 2477 CONFLICT (DMULT, DMACC); 2478 CONFLICT (DMACC, DMULT); 2479 CONFLICT (DMACC, DMACC); 2480 2481 /* Errata 24 - MT{LO,HI} after [D]MACC */ 2482 CONFLICT (MACC, MTHILO); 2483 CONFLICT (DMACC, MTHILO); 2484 2485 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU 2486 instruction is executed immediately after a MACC or DMACC 2487 instruction, the result of [either instruction] is incorrect." */ 2488 CONFLICT (MACC, MULT); 2489 CONFLICT (MACC, DMULT); 2490 CONFLICT (DMACC, MULT); 2491 CONFLICT (DMACC, DMULT); 2492 2493 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is 2494 executed immediately after a DMULT, DMULTU, DIV, DIVU, 2495 DDIV or DDIVU instruction, the result of the MACC or 2496 DMACC instruction is incorrect.". */ 2497 CONFLICT (DMULT, MACC); 2498 CONFLICT (DMULT, DMACC); 2499 CONFLICT (DIV, MACC); 2500 CONFLICT (DIV, DMACC); 2501 2502 #undef CONFLICT 2503 } 2504 2505 struct regname { 2506 const char *name; 2507 unsigned int num; 2508 }; 2509 2510 #define RNUM_MASK 0x00000ff 2511 #define RTYPE_MASK 0x0ffff00 2512 #define RTYPE_NUM 0x0000100 2513 #define RTYPE_FPU 0x0000200 2514 #define RTYPE_FCC 0x0000400 2515 #define RTYPE_VEC 0x0000800 2516 #define RTYPE_GP 0x0001000 2517 #define RTYPE_CP0 0x0002000 2518 #define RTYPE_PC 0x0004000 2519 #define RTYPE_ACC 0x0008000 2520 #define RTYPE_CCC 0x0010000 2521 #define RTYPE_VI 0x0020000 2522 #define RTYPE_VF 0x0040000 2523 #define RTYPE_R5900_I 0x0080000 2524 #define RTYPE_R5900_Q 0x0100000 2525 #define RTYPE_R5900_R 0x0200000 2526 #define RTYPE_R5900_ACC 0x0400000 2527 #define RTYPE_MSA 0x0800000 2528 #define RWARN 0x8000000 2529 2530 #define GENERIC_REGISTER_NUMBERS \ 2531 {"$0", RTYPE_NUM | 0}, \ 2532 {"$1", RTYPE_NUM | 1}, \ 2533 {"$2", RTYPE_NUM | 2}, \ 2534 {"$3", RTYPE_NUM | 3}, \ 2535 {"$4", RTYPE_NUM | 4}, \ 2536 {"$5", RTYPE_NUM | 5}, \ 2537 {"$6", RTYPE_NUM | 6}, \ 2538 {"$7", RTYPE_NUM | 7}, \ 2539 {"$8", RTYPE_NUM | 8}, \ 2540 {"$9", RTYPE_NUM | 9}, \ 2541 {"$10", RTYPE_NUM | 10}, \ 2542 {"$11", RTYPE_NUM | 11}, \ 2543 {"$12", RTYPE_NUM | 12}, \ 2544 {"$13", RTYPE_NUM | 13}, \ 2545 {"$14", RTYPE_NUM | 14}, \ 2546 {"$15", RTYPE_NUM | 15}, \ 2547 {"$16", RTYPE_NUM | 16}, \ 2548 {"$17", RTYPE_NUM | 17}, \ 2549 {"$18", RTYPE_NUM | 18}, \ 2550 {"$19", RTYPE_NUM | 19}, \ 2551 {"$20", RTYPE_NUM | 20}, \ 2552 {"$21", RTYPE_NUM | 21}, \ 2553 {"$22", RTYPE_NUM | 22}, \ 2554 {"$23", RTYPE_NUM | 23}, \ 2555 {"$24", RTYPE_NUM | 24}, \ 2556 {"$25", RTYPE_NUM | 25}, \ 2557 {"$26", RTYPE_NUM | 26}, \ 2558 {"$27", RTYPE_NUM | 27}, \ 2559 {"$28", RTYPE_NUM | 28}, \ 2560 {"$29", RTYPE_NUM | 29}, \ 2561 {"$30", RTYPE_NUM | 30}, \ 2562 {"$31", RTYPE_NUM | 31} 2563 2564 #define FPU_REGISTER_NAMES \ 2565 {"$f0", RTYPE_FPU | 0}, \ 2566 {"$f1", RTYPE_FPU | 1}, \ 2567 {"$f2", RTYPE_FPU | 2}, \ 2568 {"$f3", RTYPE_FPU | 3}, \ 2569 {"$f4", RTYPE_FPU | 4}, \ 2570 {"$f5", RTYPE_FPU | 5}, \ 2571 {"$f6", RTYPE_FPU | 6}, \ 2572 {"$f7", RTYPE_FPU | 7}, \ 2573 {"$f8", RTYPE_FPU | 8}, \ 2574 {"$f9", RTYPE_FPU | 9}, \ 2575 {"$f10", RTYPE_FPU | 10}, \ 2576 {"$f11", RTYPE_FPU | 11}, \ 2577 {"$f12", RTYPE_FPU | 12}, \ 2578 {"$f13", RTYPE_FPU | 13}, \ 2579 {"$f14", RTYPE_FPU | 14}, \ 2580 {"$f15", RTYPE_FPU | 15}, \ 2581 {"$f16", RTYPE_FPU | 16}, \ 2582 {"$f17", RTYPE_FPU | 17}, \ 2583 {"$f18", RTYPE_FPU | 18}, \ 2584 {"$f19", RTYPE_FPU | 19}, \ 2585 {"$f20", RTYPE_FPU | 20}, \ 2586 {"$f21", RTYPE_FPU | 21}, \ 2587 {"$f22", RTYPE_FPU | 22}, \ 2588 {"$f23", RTYPE_FPU | 23}, \ 2589 {"$f24", RTYPE_FPU | 24}, \ 2590 {"$f25", RTYPE_FPU | 25}, \ 2591 {"$f26", RTYPE_FPU | 26}, \ 2592 {"$f27", RTYPE_FPU | 27}, \ 2593 {"$f28", RTYPE_FPU | 28}, \ 2594 {"$f29", RTYPE_FPU | 29}, \ 2595 {"$f30", RTYPE_FPU | 30}, \ 2596 {"$f31", RTYPE_FPU | 31} 2597 2598 #define FPU_CONDITION_CODE_NAMES \ 2599 {"$fcc0", RTYPE_FCC | 0}, \ 2600 {"$fcc1", RTYPE_FCC | 1}, \ 2601 {"$fcc2", RTYPE_FCC | 2}, \ 2602 {"$fcc3", RTYPE_FCC | 3}, \ 2603 {"$fcc4", RTYPE_FCC | 4}, \ 2604 {"$fcc5", RTYPE_FCC | 5}, \ 2605 {"$fcc6", RTYPE_FCC | 6}, \ 2606 {"$fcc7", RTYPE_FCC | 7} 2607 2608 #define COPROC_CONDITION_CODE_NAMES \ 2609 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ 2610 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ 2611 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ 2612 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ 2613 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ 2614 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ 2615 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ 2616 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} 2617 2618 #define N32N64_SYMBOLIC_REGISTER_NAMES \ 2619 {"$a4", RTYPE_GP | 8}, \ 2620 {"$a5", RTYPE_GP | 9}, \ 2621 {"$a6", RTYPE_GP | 10}, \ 2622 {"$a7", RTYPE_GP | 11}, \ 2623 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ 2624 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ 2625 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ 2626 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ 2627 {"$t0", RTYPE_GP | 12}, \ 2628 {"$t1", RTYPE_GP | 13}, \ 2629 {"$t2", RTYPE_GP | 14}, \ 2630 {"$t3", RTYPE_GP | 15} 2631 2632 #define O32_SYMBOLIC_REGISTER_NAMES \ 2633 {"$t0", RTYPE_GP | 8}, \ 2634 {"$t1", RTYPE_GP | 9}, \ 2635 {"$t2", RTYPE_GP | 10}, \ 2636 {"$t3", RTYPE_GP | 11}, \ 2637 {"$t4", RTYPE_GP | 12}, \ 2638 {"$t5", RTYPE_GP | 13}, \ 2639 {"$t6", RTYPE_GP | 14}, \ 2640 {"$t7", RTYPE_GP | 15}, \ 2641 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ 2642 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ 2643 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ 2644 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ 2645 2646 /* Remaining symbolic register names */ 2647 #define SYMBOLIC_REGISTER_NAMES \ 2648 {"$zero", RTYPE_GP | 0}, \ 2649 {"$at", RTYPE_GP | 1}, \ 2650 {"$AT", RTYPE_GP | 1}, \ 2651 {"$v0", RTYPE_GP | 2}, \ 2652 {"$v1", RTYPE_GP | 3}, \ 2653 {"$a0", RTYPE_GP | 4}, \ 2654 {"$a1", RTYPE_GP | 5}, \ 2655 {"$a2", RTYPE_GP | 6}, \ 2656 {"$a3", RTYPE_GP | 7}, \ 2657 {"$s0", RTYPE_GP | 16}, \ 2658 {"$s1", RTYPE_GP | 17}, \ 2659 {"$s2", RTYPE_GP | 18}, \ 2660 {"$s3", RTYPE_GP | 19}, \ 2661 {"$s4", RTYPE_GP | 20}, \ 2662 {"$s5", RTYPE_GP | 21}, \ 2663 {"$s6", RTYPE_GP | 22}, \ 2664 {"$s7", RTYPE_GP | 23}, \ 2665 {"$t8", RTYPE_GP | 24}, \ 2666 {"$t9", RTYPE_GP | 25}, \ 2667 {"$k0", RTYPE_GP | 26}, \ 2668 {"$kt0", RTYPE_GP | 26}, \ 2669 {"$k1", RTYPE_GP | 27}, \ 2670 {"$kt1", RTYPE_GP | 27}, \ 2671 {"$gp", RTYPE_GP | 28}, \ 2672 {"$sp", RTYPE_GP | 29}, \ 2673 {"$s8", RTYPE_GP | 30}, \ 2674 {"$fp", RTYPE_GP | 30}, \ 2675 {"$ra", RTYPE_GP | 31} 2676 2677 #define MIPS16_SPECIAL_REGISTER_NAMES \ 2678 {"$pc", RTYPE_PC | 0} 2679 2680 #define MDMX_VECTOR_REGISTER_NAMES \ 2681 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ 2682 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ 2683 {"$v2", RTYPE_VEC | 2}, \ 2684 {"$v3", RTYPE_VEC | 3}, \ 2685 {"$v4", RTYPE_VEC | 4}, \ 2686 {"$v5", RTYPE_VEC | 5}, \ 2687 {"$v6", RTYPE_VEC | 6}, \ 2688 {"$v7", RTYPE_VEC | 7}, \ 2689 {"$v8", RTYPE_VEC | 8}, \ 2690 {"$v9", RTYPE_VEC | 9}, \ 2691 {"$v10", RTYPE_VEC | 10}, \ 2692 {"$v11", RTYPE_VEC | 11}, \ 2693 {"$v12", RTYPE_VEC | 12}, \ 2694 {"$v13", RTYPE_VEC | 13}, \ 2695 {"$v14", RTYPE_VEC | 14}, \ 2696 {"$v15", RTYPE_VEC | 15}, \ 2697 {"$v16", RTYPE_VEC | 16}, \ 2698 {"$v17", RTYPE_VEC | 17}, \ 2699 {"$v18", RTYPE_VEC | 18}, \ 2700 {"$v19", RTYPE_VEC | 19}, \ 2701 {"$v20", RTYPE_VEC | 20}, \ 2702 {"$v21", RTYPE_VEC | 21}, \ 2703 {"$v22", RTYPE_VEC | 22}, \ 2704 {"$v23", RTYPE_VEC | 23}, \ 2705 {"$v24", RTYPE_VEC | 24}, \ 2706 {"$v25", RTYPE_VEC | 25}, \ 2707 {"$v26", RTYPE_VEC | 26}, \ 2708 {"$v27", RTYPE_VEC | 27}, \ 2709 {"$v28", RTYPE_VEC | 28}, \ 2710 {"$v29", RTYPE_VEC | 29}, \ 2711 {"$v30", RTYPE_VEC | 30}, \ 2712 {"$v31", RTYPE_VEC | 31} 2713 2714 #define R5900_I_NAMES \ 2715 {"$I", RTYPE_R5900_I | 0} 2716 2717 #define R5900_Q_NAMES \ 2718 {"$Q", RTYPE_R5900_Q | 0} 2719 2720 #define R5900_R_NAMES \ 2721 {"$R", RTYPE_R5900_R | 0} 2722 2723 #define R5900_ACC_NAMES \ 2724 {"$ACC", RTYPE_R5900_ACC | 0 } 2725 2726 #define MIPS_DSP_ACCUMULATOR_NAMES \ 2727 {"$ac0", RTYPE_ACC | 0}, \ 2728 {"$ac1", RTYPE_ACC | 1}, \ 2729 {"$ac2", RTYPE_ACC | 2}, \ 2730 {"$ac3", RTYPE_ACC | 3} 2731 2732 static const struct regname reg_names[] = { 2733 GENERIC_REGISTER_NUMBERS, 2734 FPU_REGISTER_NAMES, 2735 FPU_CONDITION_CODE_NAMES, 2736 COPROC_CONDITION_CODE_NAMES, 2737 2738 /* The $txx registers depends on the abi, 2739 these will be added later into the symbol table from 2740 one of the tables below once mips_abi is set after 2741 parsing of arguments from the command line. */ 2742 SYMBOLIC_REGISTER_NAMES, 2743 2744 MIPS16_SPECIAL_REGISTER_NAMES, 2745 MDMX_VECTOR_REGISTER_NAMES, 2746 R5900_I_NAMES, 2747 R5900_Q_NAMES, 2748 R5900_R_NAMES, 2749 R5900_ACC_NAMES, 2750 MIPS_DSP_ACCUMULATOR_NAMES, 2751 {0, 0} 2752 }; 2753 2754 static const struct regname reg_names_o32[] = { 2755 O32_SYMBOLIC_REGISTER_NAMES, 2756 {0, 0} 2757 }; 2758 2759 static const struct regname reg_names_n32n64[] = { 2760 N32N64_SYMBOLIC_REGISTER_NAMES, 2761 {0, 0} 2762 }; 2763 2764 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be 2765 interpreted as vector registers 0 and 1. If SYMVAL is the value of one 2766 of these register symbols, return the associated vector register, 2767 otherwise return SYMVAL itself. */ 2768 2769 static unsigned int 2770 mips_prefer_vec_regno (unsigned int symval) 2771 { 2772 if ((symval & -2) == (RTYPE_GP | 2)) 2773 return RTYPE_VEC | (symval & 1); 2774 return symval; 2775 } 2776 2777 /* Return true if string [S, E) is a valid register name, storing its 2778 symbol value in *SYMVAL_PTR if so. */ 2779 2780 static bfd_boolean 2781 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) 2782 { 2783 char save_c; 2784 symbolS *symbol; 2785 2786 /* Terminate name. */ 2787 save_c = *e; 2788 *e = '\0'; 2789 2790 /* Look up the name. */ 2791 symbol = symbol_find (s); 2792 *e = save_c; 2793 2794 if (!symbol || S_GET_SEGMENT (symbol) != reg_section) 2795 return FALSE; 2796 2797 *symval_ptr = S_GET_VALUE (symbol); 2798 return TRUE; 2799 } 2800 2801 /* Return true if the string at *SPTR is a valid register name. Allow it 2802 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR 2803 is nonnull. 2804 2805 When returning true, move *SPTR past the register, store the 2806 register's symbol value in *SYMVAL_PTR and the channel mask in 2807 *CHANNELS_PTR (if nonnull). The symbol value includes the register 2808 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask 2809 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ 2810 2811 static bfd_boolean 2812 mips_parse_register (char **sptr, unsigned int *symval_ptr, 2813 unsigned int *channels_ptr) 2814 { 2815 char *s, *e, *m; 2816 const char *q; 2817 unsigned int channels, symval, bit; 2818 2819 /* Find end of name. */ 2820 s = e = *sptr; 2821 if (is_name_beginner (*e)) 2822 ++e; 2823 while (is_part_of_name (*e)) 2824 ++e; 2825 2826 channels = 0; 2827 if (!mips_parse_register_1 (s, e, &symval)) 2828 { 2829 if (!channels_ptr) 2830 return FALSE; 2831 2832 /* Eat characters from the end of the string that are valid 2833 channel suffixes. The preceding register must be $ACC or 2834 end with a digit, so there is no ambiguity. */ 2835 bit = 1; 2836 m = e; 2837 for (q = "wzyx"; *q; q++, bit <<= 1) 2838 if (m > s && m[-1] == *q) 2839 { 2840 --m; 2841 channels |= bit; 2842 } 2843 2844 if (channels == 0 2845 || !mips_parse_register_1 (s, m, &symval) 2846 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) 2847 return FALSE; 2848 } 2849 2850 *sptr = e; 2851 *symval_ptr = symval; 2852 if (channels_ptr) 2853 *channels_ptr = channels; 2854 return TRUE; 2855 } 2856 2857 /* Check if SPTR points at a valid register specifier according to TYPES. 2858 If so, then return 1, advance S to consume the specifier and store 2859 the register's number in REGNOP, otherwise return 0. */ 2860 2861 static int 2862 reg_lookup (char **s, unsigned int types, unsigned int *regnop) 2863 { 2864 unsigned int regno; 2865 2866 if (mips_parse_register (s, ®no, NULL)) 2867 { 2868 if (types & RTYPE_VEC) 2869 regno = mips_prefer_vec_regno (regno); 2870 if (regno & types) 2871 regno &= RNUM_MASK; 2872 else 2873 regno = ~0; 2874 } 2875 else 2876 { 2877 if (types & RWARN) 2878 as_warn (_("unrecognized register name `%s'"), *s); 2879 regno = ~0; 2880 } 2881 if (regnop) 2882 *regnop = regno; 2883 return regno <= RNUM_MASK; 2884 } 2885 2886 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated 2887 mask in *CHANNELS. Return a pointer to the first unconsumed character. */ 2888 2889 static char * 2890 mips_parse_vu0_channels (char *s, unsigned int *channels) 2891 { 2892 unsigned int i; 2893 2894 *channels = 0; 2895 for (i = 0; i < 4; i++) 2896 if (*s == "xyzw"[i]) 2897 { 2898 *channels |= 1 << (3 - i); 2899 ++s; 2900 } 2901 return s; 2902 } 2903 2904 /* Token types for parsed operand lists. */ 2905 enum mips_operand_token_type { 2906 /* A plain register, e.g. $f2. */ 2907 OT_REG, 2908 2909 /* A 4-bit XYZW channel mask. */ 2910 OT_CHANNELS, 2911 2912 /* A constant vector index, e.g. [1]. */ 2913 OT_INTEGER_INDEX, 2914 2915 /* A register vector index, e.g. [$2]. */ 2916 OT_REG_INDEX, 2917 2918 /* A continuous range of registers, e.g. $s0-$s4. */ 2919 OT_REG_RANGE, 2920 2921 /* A (possibly relocated) expression. */ 2922 OT_INTEGER, 2923 2924 /* A floating-point value. */ 2925 OT_FLOAT, 2926 2927 /* A single character. This can be '(', ')' or ',', but '(' only appears 2928 before OT_REGs. */ 2929 OT_CHAR, 2930 2931 /* A doubled character, either "--" or "++". */ 2932 OT_DOUBLE_CHAR, 2933 2934 /* The end of the operand list. */ 2935 OT_END 2936 }; 2937 2938 /* A parsed operand token. */ 2939 struct mips_operand_token 2940 { 2941 /* The type of token. */ 2942 enum mips_operand_token_type type; 2943 union 2944 { 2945 /* The register symbol value for an OT_REG or OT_REG_INDEX. */ 2946 unsigned int regno; 2947 2948 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ 2949 unsigned int channels; 2950 2951 /* The integer value of an OT_INTEGER_INDEX. */ 2952 addressT index; 2953 2954 /* The two register symbol values involved in an OT_REG_RANGE. */ 2955 struct { 2956 unsigned int regno1; 2957 unsigned int regno2; 2958 } reg_range; 2959 2960 /* The value of an OT_INTEGER. The value is represented as an 2961 expression and the relocation operators that were applied to 2962 that expression. The reloc entries are BFD_RELOC_UNUSED if no 2963 relocation operators were used. */ 2964 struct { 2965 expressionS value; 2966 bfd_reloc_code_real_type relocs[3]; 2967 } integer; 2968 2969 /* The binary data for an OT_FLOAT constant, and the number of bytes 2970 in the constant. */ 2971 struct { 2972 unsigned char data[8]; 2973 int length; 2974 } flt; 2975 2976 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ 2977 char ch; 2978 } u; 2979 }; 2980 2981 /* An obstack used to construct lists of mips_operand_tokens. */ 2982 static struct obstack mips_operand_tokens; 2983 2984 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ 2985 2986 static void 2987 mips_add_token (struct mips_operand_token *token, 2988 enum mips_operand_token_type type) 2989 { 2990 token->type = type; 2991 obstack_grow (&mips_operand_tokens, token, sizeof (*token)); 2992 } 2993 2994 /* Check whether S is '(' followed by a register name. Add OT_CHAR 2995 and OT_REG tokens for them if so, and return a pointer to the first 2996 unconsumed character. Return null otherwise. */ 2997 2998 static char * 2999 mips_parse_base_start (char *s) 3000 { 3001 struct mips_operand_token token; 3002 unsigned int regno, channels; 3003 bfd_boolean decrement_p; 3004 3005 if (*s != '(') 3006 return 0; 3007 3008 ++s; 3009 SKIP_SPACE_TABS (s); 3010 3011 /* Only match "--" as part of a base expression. In other contexts "--X" 3012 is a double negative. */ 3013 decrement_p = (s[0] == '-' && s[1] == '-'); 3014 if (decrement_p) 3015 { 3016 s += 2; 3017 SKIP_SPACE_TABS (s); 3018 } 3019 3020 /* Allow a channel specifier because that leads to better error messages 3021 than treating something like "$vf0x++" as an expression. */ 3022 if (!mips_parse_register (&s, ®no, &channels)) 3023 return 0; 3024 3025 token.u.ch = '('; 3026 mips_add_token (&token, OT_CHAR); 3027 3028 if (decrement_p) 3029 { 3030 token.u.ch = '-'; 3031 mips_add_token (&token, OT_DOUBLE_CHAR); 3032 } 3033 3034 token.u.regno = regno; 3035 mips_add_token (&token, OT_REG); 3036 3037 if (channels) 3038 { 3039 token.u.channels = channels; 3040 mips_add_token (&token, OT_CHANNELS); 3041 } 3042 3043 /* For consistency, only match "++" as part of base expressions too. */ 3044 SKIP_SPACE_TABS (s); 3045 if (s[0] == '+' && s[1] == '+') 3046 { 3047 s += 2; 3048 token.u.ch = '+'; 3049 mips_add_token (&token, OT_DOUBLE_CHAR); 3050 } 3051 3052 return s; 3053 } 3054 3055 /* Parse one or more tokens from S. Return a pointer to the first 3056 unconsumed character on success. Return null if an error was found 3057 and store the error text in insn_error. FLOAT_FORMAT is as for 3058 mips_parse_arguments. */ 3059 3060 static char * 3061 mips_parse_argument_token (char *s, char float_format) 3062 { 3063 char *end, *save_in; 3064 const char *err; 3065 unsigned int regno1, regno2, channels; 3066 struct mips_operand_token token; 3067 3068 /* First look for "($reg", since we want to treat that as an 3069 OT_CHAR and OT_REG rather than an expression. */ 3070 end = mips_parse_base_start (s); 3071 if (end) 3072 return end; 3073 3074 /* Handle other characters that end up as OT_CHARs. */ 3075 if (*s == ')' || *s == ',') 3076 { 3077 token.u.ch = *s; 3078 mips_add_token (&token, OT_CHAR); 3079 ++s; 3080 return s; 3081 } 3082 3083 /* Handle tokens that start with a register. */ 3084 if (mips_parse_register (&s, ®no1, &channels)) 3085 { 3086 if (channels) 3087 { 3088 /* A register and a VU0 channel suffix. */ 3089 token.u.regno = regno1; 3090 mips_add_token (&token, OT_REG); 3091 3092 token.u.channels = channels; 3093 mips_add_token (&token, OT_CHANNELS); 3094 return s; 3095 } 3096 3097 SKIP_SPACE_TABS (s); 3098 if (*s == '-') 3099 { 3100 /* A register range. */ 3101 ++s; 3102 SKIP_SPACE_TABS (s); 3103 if (!mips_parse_register (&s, ®no2, NULL)) 3104 { 3105 set_insn_error (0, _("invalid register range")); 3106 return 0; 3107 } 3108 3109 token.u.reg_range.regno1 = regno1; 3110 token.u.reg_range.regno2 = regno2; 3111 mips_add_token (&token, OT_REG_RANGE); 3112 return s; 3113 } 3114 3115 /* Add the register itself. */ 3116 token.u.regno = regno1; 3117 mips_add_token (&token, OT_REG); 3118 3119 /* Check for a vector index. */ 3120 if (*s == '[') 3121 { 3122 ++s; 3123 SKIP_SPACE_TABS (s); 3124 if (mips_parse_register (&s, &token.u.regno, NULL)) 3125 mips_add_token (&token, OT_REG_INDEX); 3126 else 3127 { 3128 expressionS element; 3129 3130 my_getExpression (&element, s); 3131 if (element.X_op != O_constant) 3132 { 3133 set_insn_error (0, _("vector element must be constant")); 3134 return 0; 3135 } 3136 s = expr_end; 3137 token.u.index = element.X_add_number; 3138 mips_add_token (&token, OT_INTEGER_INDEX); 3139 } 3140 SKIP_SPACE_TABS (s); 3141 if (*s != ']') 3142 { 3143 set_insn_error (0, _("missing `]'")); 3144 return 0; 3145 } 3146 ++s; 3147 } 3148 return s; 3149 } 3150 3151 if (float_format) 3152 { 3153 /* First try to treat expressions as floats. */ 3154 save_in = input_line_pointer; 3155 input_line_pointer = s; 3156 err = md_atof (float_format, (char *) token.u.flt.data, 3157 &token.u.flt.length); 3158 end = input_line_pointer; 3159 input_line_pointer = save_in; 3160 if (err && *err) 3161 { 3162 set_insn_error (0, err); 3163 return 0; 3164 } 3165 if (s != end) 3166 { 3167 mips_add_token (&token, OT_FLOAT); 3168 return end; 3169 } 3170 } 3171 3172 /* Treat everything else as an integer expression. */ 3173 token.u.integer.relocs[0] = BFD_RELOC_UNUSED; 3174 token.u.integer.relocs[1] = BFD_RELOC_UNUSED; 3175 token.u.integer.relocs[2] = BFD_RELOC_UNUSED; 3176 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); 3177 s = expr_end; 3178 mips_add_token (&token, OT_INTEGER); 3179 return s; 3180 } 3181 3182 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' 3183 if expressions should be treated as 32-bit floating-point constants, 3184 'd' if they should be treated as 64-bit floating-point constants, 3185 or 0 if they should be treated as integer expressions (the usual case). 3186 3187 Return a list of tokens on success, otherwise return 0. The caller 3188 must obstack_free the list after use. */ 3189 3190 static struct mips_operand_token * 3191 mips_parse_arguments (char *s, char float_format) 3192 { 3193 struct mips_operand_token token; 3194 3195 SKIP_SPACE_TABS (s); 3196 while (*s) 3197 { 3198 s = mips_parse_argument_token (s, float_format); 3199 if (!s) 3200 { 3201 obstack_free (&mips_operand_tokens, 3202 obstack_finish (&mips_operand_tokens)); 3203 return 0; 3204 } 3205 SKIP_SPACE_TABS (s); 3206 } 3207 mips_add_token (&token, OT_END); 3208 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); 3209 } 3210 3211 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE 3212 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ 3213 3214 static bfd_boolean 3215 is_opcode_valid (const struct mips_opcode *mo) 3216 { 3217 int isa = mips_opts.isa; 3218 int ase = mips_opts.ase; 3219 int fp_s, fp_d; 3220 unsigned int i; 3221 3222 if (ISA_HAS_64BIT_REGS (mips_opts.isa)) 3223 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 3224 if ((ase & mips_ases[i].flags) == mips_ases[i].flags) 3225 ase |= mips_ases[i].flags64; 3226 3227 if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) 3228 return FALSE; 3229 3230 /* Check whether the instruction or macro requires single-precision or 3231 double-precision floating-point support. Note that this information is 3232 stored differently in the opcode table for insns and macros. */ 3233 if (mo->pinfo == INSN_MACRO) 3234 { 3235 fp_s = mo->pinfo2 & INSN2_M_FP_S; 3236 fp_d = mo->pinfo2 & INSN2_M_FP_D; 3237 } 3238 else 3239 { 3240 fp_s = mo->pinfo & FP_S; 3241 fp_d = mo->pinfo & FP_D; 3242 } 3243 3244 if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) 3245 return FALSE; 3246 3247 if (fp_s && mips_opts.soft_float) 3248 return FALSE; 3249 3250 return TRUE; 3251 } 3252 3253 /* Return TRUE if the MIPS16 opcode MO is valid on the currently 3254 selected ISA and architecture. */ 3255 3256 static bfd_boolean 3257 is_opcode_valid_16 (const struct mips_opcode *mo) 3258 { 3259 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); 3260 } 3261 3262 /* Return TRUE if the size of the microMIPS opcode MO matches one 3263 explicitly requested. Always TRUE in the standard MIPS mode. */ 3264 3265 static bfd_boolean 3266 is_size_valid (const struct mips_opcode *mo) 3267 { 3268 if (!mips_opts.micromips) 3269 return TRUE; 3270 3271 if (mips_opts.insn32) 3272 { 3273 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) 3274 return FALSE; 3275 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) 3276 return FALSE; 3277 } 3278 if (!forced_insn_length) 3279 return TRUE; 3280 if (mo->pinfo == INSN_MACRO) 3281 return FALSE; 3282 return forced_insn_length == micromips_insn_length (mo); 3283 } 3284 3285 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot 3286 of the preceding instruction. Always TRUE in the standard MIPS mode. 3287 3288 We don't accept macros in 16-bit delay slots to avoid a case where 3289 a macro expansion fails because it relies on a preceding 32-bit real 3290 instruction to have matched and does not handle the operands correctly. 3291 The only macros that may expand to 16-bit instructions are JAL that 3292 cannot be placed in a delay slot anyway, and corner cases of BALIGN 3293 and BGT (that likewise cannot be placed in a delay slot) that decay to 3294 a NOP. In all these cases the macros precede any corresponding real 3295 instruction definitions in the opcode table, so they will match in the 3296 second pass where the size of the delay slot is ignored and therefore 3297 produce correct code. */ 3298 3299 static bfd_boolean 3300 is_delay_slot_valid (const struct mips_opcode *mo) 3301 { 3302 if (!mips_opts.micromips) 3303 return TRUE; 3304 3305 if (mo->pinfo == INSN_MACRO) 3306 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; 3307 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 3308 && micromips_insn_length (mo) != 4) 3309 return FALSE; 3310 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 3311 && micromips_insn_length (mo) != 2) 3312 return FALSE; 3313 3314 return TRUE; 3315 } 3316 3317 /* For consistency checking, verify that all bits of OPCODE are specified 3318 either by the match/mask part of the instruction definition, or by the 3319 operand list. Also build up a list of operands in OPERANDS. 3320 3321 INSN_BITS says which bits of the instruction are significant. 3322 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND 3323 provides the mips_operand description of each operand. DECODE_OPERAND 3324 is null for MIPS16 instructions. */ 3325 3326 static int 3327 validate_mips_insn (const struct mips_opcode *opcode, 3328 unsigned long insn_bits, 3329 const struct mips_operand *(*decode_operand) (const char *), 3330 struct mips_operand_array *operands) 3331 { 3332 const char *s; 3333 unsigned long used_bits, doubled, undefined, opno, mask; 3334 const struct mips_operand *operand; 3335 3336 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); 3337 if ((mask & opcode->match) != opcode->match) 3338 { 3339 as_bad (_("internal: bad mips opcode (mask error): %s %s"), 3340 opcode->name, opcode->args); 3341 return 0; 3342 } 3343 used_bits = 0; 3344 opno = 0; 3345 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 3346 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); 3347 for (s = opcode->args; *s; ++s) 3348 switch (*s) 3349 { 3350 case ',': 3351 case '(': 3352 case ')': 3353 break; 3354 3355 case '#': 3356 s++; 3357 break; 3358 3359 default: 3360 if (!decode_operand) 3361 operand = decode_mips16_operand (*s, FALSE); 3362 else 3363 operand = decode_operand (s); 3364 if (!operand && opcode->pinfo != INSN_MACRO) 3365 { 3366 as_bad (_("internal: unknown operand type: %s %s"), 3367 opcode->name, opcode->args); 3368 return 0; 3369 } 3370 gas_assert (opno < MAX_OPERANDS); 3371 operands->operand[opno] = operand; 3372 if (operand && operand->type != OP_VU0_MATCH_SUFFIX) 3373 { 3374 used_bits = mips_insert_operand (operand, used_bits, -1); 3375 if (operand->type == OP_MDMX_IMM_REG) 3376 /* Bit 5 is the format selector (OB vs QH). The opcode table 3377 has separate entries for each format. */ 3378 used_bits &= ~(1 << (operand->lsb + 5)); 3379 if (operand->type == OP_ENTRY_EXIT_LIST) 3380 used_bits &= ~(mask & 0x700); 3381 } 3382 /* Skip prefix characters. */ 3383 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) 3384 ++s; 3385 opno += 1; 3386 break; 3387 } 3388 doubled = used_bits & mask & insn_bits; 3389 if (doubled) 3390 { 3391 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" 3392 " %s %s"), doubled, opcode->name, opcode->args); 3393 return 0; 3394 } 3395 used_bits |= mask; 3396 undefined = ~used_bits & insn_bits; 3397 if (opcode->pinfo != INSN_MACRO && undefined) 3398 { 3399 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), 3400 undefined, opcode->name, opcode->args); 3401 return 0; 3402 } 3403 used_bits &= ~insn_bits; 3404 if (used_bits) 3405 { 3406 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), 3407 used_bits, opcode->name, opcode->args); 3408 return 0; 3409 } 3410 return 1; 3411 } 3412 3413 /* The MIPS16 version of validate_mips_insn. */ 3414 3415 static int 3416 validate_mips16_insn (const struct mips_opcode *opcode, 3417 struct mips_operand_array *operands) 3418 { 3419 if (opcode->args[0] == 'a' || opcode->args[0] == 'i') 3420 { 3421 /* In this case OPCODE defines the first 16 bits in a 32-bit jump 3422 instruction. Use TMP to describe the full instruction. */ 3423 struct mips_opcode tmp; 3424 3425 tmp = *opcode; 3426 tmp.match <<= 16; 3427 tmp.mask <<= 16; 3428 return validate_mips_insn (&tmp, 0xffffffff, 0, operands); 3429 } 3430 return validate_mips_insn (opcode, 0xffff, 0, operands); 3431 } 3432 3433 /* The microMIPS version of validate_mips_insn. */ 3434 3435 static int 3436 validate_micromips_insn (const struct mips_opcode *opc, 3437 struct mips_operand_array *operands) 3438 { 3439 unsigned long insn_bits; 3440 unsigned long major; 3441 unsigned int length; 3442 3443 if (opc->pinfo == INSN_MACRO) 3444 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, 3445 operands); 3446 3447 length = micromips_insn_length (opc); 3448 if (length != 2 && length != 4) 3449 { 3450 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " 3451 "%s %s"), length, opc->name, opc->args); 3452 return 0; 3453 } 3454 major = opc->match >> (10 + 8 * (length - 2)); 3455 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) 3456 || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) 3457 { 3458 as_bad (_("internal error: bad microMIPS opcode " 3459 "(opcode/length mismatch): %s %s"), opc->name, opc->args); 3460 return 0; 3461 } 3462 3463 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ 3464 insn_bits = 1 << 4 * length; 3465 insn_bits <<= 4 * length; 3466 insn_bits -= 1; 3467 return validate_mips_insn (opc, insn_bits, decode_micromips_operand, 3468 operands); 3469 } 3470 3471 /* This function is called once, at assembler startup time. It should set up 3472 all the tables, etc. that the MD part of the assembler will need. */ 3473 3474 void 3475 md_begin (void) 3476 { 3477 const char *retval = NULL; 3478 int i = 0; 3479 int broken = 0; 3480 3481 if (mips_pic != NO_PIC) 3482 { 3483 if (g_switch_seen && g_switch_value != 0) 3484 as_bad (_("-G may not be used in position-independent code")); 3485 g_switch_value = 0; 3486 } 3487 else if (mips_abicalls) 3488 { 3489 if (g_switch_seen && g_switch_value != 0) 3490 as_bad (_("-G may not be used with abicalls")); 3491 g_switch_value = 0; 3492 } 3493 3494 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 3495 as_warn (_("could not set architecture and machine")); 3496 3497 op_hash = hash_new (); 3498 3499 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); 3500 for (i = 0; i < NUMOPCODES;) 3501 { 3502 const char *name = mips_opcodes[i].name; 3503 3504 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); 3505 if (retval != NULL) 3506 { 3507 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 3508 mips_opcodes[i].name, retval); 3509 /* Probably a memory allocation problem? Give up now. */ 3510 as_fatal (_("broken assembler, no assembly attempted")); 3511 } 3512 do 3513 { 3514 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, 3515 decode_mips_operand, &mips_operands[i])) 3516 broken = 1; 3517 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3518 { 3519 create_insn (&nop_insn, mips_opcodes + i); 3520 if (mips_fix_loongson2f_nop) 3521 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; 3522 nop_insn.fixed_p = 1; 3523 } 3524 ++i; 3525 } 3526 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); 3527 } 3528 3529 mips16_op_hash = hash_new (); 3530 mips16_operands = XCNEWVEC (struct mips_operand_array, 3531 bfd_mips16_num_opcodes); 3532 3533 i = 0; 3534 while (i < bfd_mips16_num_opcodes) 3535 { 3536 const char *name = mips16_opcodes[i].name; 3537 3538 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); 3539 if (retval != NULL) 3540 as_fatal (_("internal: can't hash `%s': %s"), 3541 mips16_opcodes[i].name, retval); 3542 do 3543 { 3544 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) 3545 broken = 1; 3546 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3547 { 3548 create_insn (&mips16_nop_insn, mips16_opcodes + i); 3549 mips16_nop_insn.fixed_p = 1; 3550 } 3551 ++i; 3552 } 3553 while (i < bfd_mips16_num_opcodes 3554 && strcmp (mips16_opcodes[i].name, name) == 0); 3555 } 3556 3557 micromips_op_hash = hash_new (); 3558 micromips_operands = XCNEWVEC (struct mips_operand_array, 3559 bfd_micromips_num_opcodes); 3560 3561 i = 0; 3562 while (i < bfd_micromips_num_opcodes) 3563 { 3564 const char *name = micromips_opcodes[i].name; 3565 3566 retval = hash_insert (micromips_op_hash, name, 3567 (void *) µmips_opcodes[i]); 3568 if (retval != NULL) 3569 as_fatal (_("internal: can't hash `%s': %s"), 3570 micromips_opcodes[i].name, retval); 3571 do 3572 { 3573 struct mips_cl_insn *micromips_nop_insn; 3574 3575 if (!validate_micromips_insn (µmips_opcodes[i], 3576 µmips_operands[i])) 3577 broken = 1; 3578 3579 if (micromips_opcodes[i].pinfo != INSN_MACRO) 3580 { 3581 if (micromips_insn_length (micromips_opcodes + i) == 2) 3582 micromips_nop_insn = µmips_nop16_insn; 3583 else if (micromips_insn_length (micromips_opcodes + i) == 4) 3584 micromips_nop_insn = µmips_nop32_insn; 3585 else 3586 continue; 3587 3588 if (micromips_nop_insn->insn_mo == NULL 3589 && strcmp (name, "nop") == 0) 3590 { 3591 create_insn (micromips_nop_insn, micromips_opcodes + i); 3592 micromips_nop_insn->fixed_p = 1; 3593 } 3594 } 3595 } 3596 while (++i < bfd_micromips_num_opcodes 3597 && strcmp (micromips_opcodes[i].name, name) == 0); 3598 } 3599 3600 if (broken) 3601 as_fatal (_("broken assembler, no assembly attempted")); 3602 3603 /* We add all the general register names to the symbol table. This 3604 helps us detect invalid uses of them. */ 3605 for (i = 0; reg_names[i].name; i++) 3606 symbol_table_insert (symbol_new (reg_names[i].name, reg_section, 3607 reg_names[i].num, /* & RNUM_MASK, */ 3608 &zero_address_frag)); 3609 if (HAVE_NEWABI) 3610 for (i = 0; reg_names_n32n64[i].name; i++) 3611 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, 3612 reg_names_n32n64[i].num, /* & RNUM_MASK, */ 3613 &zero_address_frag)); 3614 else 3615 for (i = 0; reg_names_o32[i].name; i++) 3616 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, 3617 reg_names_o32[i].num, /* & RNUM_MASK, */ 3618 &zero_address_frag)); 3619 3620 for (i = 0; i < 32; i++) 3621 { 3622 char regname[6]; 3623 3624 /* R5900 VU0 floating-point register. */ 3625 sprintf (regname, "$vf%d", i); 3626 symbol_table_insert (symbol_new (regname, reg_section, 3627 RTYPE_VF | i, &zero_address_frag)); 3628 3629 /* R5900 VU0 integer register. */ 3630 sprintf (regname, "$vi%d", i); 3631 symbol_table_insert (symbol_new (regname, reg_section, 3632 RTYPE_VI | i, &zero_address_frag)); 3633 3634 /* MSA register. */ 3635 sprintf (regname, "$w%d", i); 3636 symbol_table_insert (symbol_new (regname, reg_section, 3637 RTYPE_MSA | i, &zero_address_frag)); 3638 } 3639 3640 obstack_init (&mips_operand_tokens); 3641 3642 mips_no_prev_insn (); 3643 3644 mips_gprmask = 0; 3645 mips_cprmask[0] = 0; 3646 mips_cprmask[1] = 0; 3647 mips_cprmask[2] = 0; 3648 mips_cprmask[3] = 0; 3649 3650 /* set the default alignment for the text section (2**2) */ 3651 record_alignment (text_section, 2); 3652 3653 bfd_set_gp_size (stdoutput, g_switch_value); 3654 3655 /* On a native system other than VxWorks, sections must be aligned 3656 to 16 byte boundaries. When configured for an embedded ELF 3657 target, we don't bother. */ 3658 if (strncmp (TARGET_OS, "elf", 3) != 0 3659 && strncmp (TARGET_OS, "vxworks", 7) != 0) 3660 { 3661 (void) bfd_set_section_alignment (stdoutput, text_section, 4); 3662 (void) bfd_set_section_alignment (stdoutput, data_section, 4); 3663 (void) bfd_set_section_alignment (stdoutput, bss_section, 4); 3664 } 3665 3666 /* Create a .reginfo section for register masks and a .mdebug 3667 section for debugging information. */ 3668 { 3669 segT seg; 3670 subsegT subseg; 3671 flagword flags; 3672 segT sec; 3673 3674 seg = now_seg; 3675 subseg = now_subseg; 3676 3677 /* The ABI says this section should be loaded so that the 3678 running program can access it. However, we don't load it 3679 if we are configured for an embedded target */ 3680 flags = SEC_READONLY | SEC_DATA; 3681 if (strncmp (TARGET_OS, "elf", 3) != 0) 3682 flags |= SEC_ALLOC | SEC_LOAD; 3683 3684 if (mips_abi != N64_ABI) 3685 { 3686 sec = subseg_new (".reginfo", (subsegT) 0); 3687 3688 bfd_set_section_flags (stdoutput, sec, flags); 3689 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); 3690 3691 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); 3692 } 3693 else 3694 { 3695 /* The 64-bit ABI uses a .MIPS.options section rather than 3696 .reginfo section. */ 3697 sec = subseg_new (".MIPS.options", (subsegT) 0); 3698 bfd_set_section_flags (stdoutput, sec, flags); 3699 bfd_set_section_alignment (stdoutput, sec, 3); 3700 3701 /* Set up the option header. */ 3702 { 3703 Elf_Internal_Options opthdr; 3704 char *f; 3705 3706 opthdr.kind = ODK_REGINFO; 3707 opthdr.size = (sizeof (Elf_External_Options) 3708 + sizeof (Elf64_External_RegInfo)); 3709 opthdr.section = 0; 3710 opthdr.info = 0; 3711 f = frag_more (sizeof (Elf_External_Options)); 3712 bfd_mips_elf_swap_options_out (stdoutput, &opthdr, 3713 (Elf_External_Options *) f); 3714 3715 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); 3716 } 3717 } 3718 3719 sec = subseg_new (".MIPS.abiflags", (subsegT) 0); 3720 bfd_set_section_flags (stdoutput, sec, 3721 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); 3722 bfd_set_section_alignment (stdoutput, sec, 3); 3723 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); 3724 3725 if (ECOFF_DEBUGGING) 3726 { 3727 sec = subseg_new (".mdebug", (subsegT) 0); 3728 (void) bfd_set_section_flags (stdoutput, sec, 3729 SEC_HAS_CONTENTS | SEC_READONLY); 3730 (void) bfd_set_section_alignment (stdoutput, sec, 2); 3731 } 3732 else if (mips_flag_pdr) 3733 { 3734 pdr_seg = subseg_new (".pdr", (subsegT) 0); 3735 (void) bfd_set_section_flags (stdoutput, pdr_seg, 3736 SEC_READONLY | SEC_RELOC 3737 | SEC_DEBUGGING); 3738 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); 3739 } 3740 3741 subseg_set (seg, subseg); 3742 } 3743 3744 if (mips_fix_vr4120) 3745 init_vr4120_conflicts (); 3746 } 3747 3748 static inline void 3749 fpabi_incompatible_with (int fpabi, const char *what) 3750 { 3751 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), 3752 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3753 } 3754 3755 static inline void 3756 fpabi_requires (int fpabi, const char *what) 3757 { 3758 as_warn (_(".gnu_attribute %d,%d requires `%s'"), 3759 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3760 } 3761 3762 /* Check -mabi and register sizes against the specified FP ABI. */ 3763 static void 3764 check_fpabi (int fpabi) 3765 { 3766 switch (fpabi) 3767 { 3768 case Val_GNU_MIPS_ABI_FP_DOUBLE: 3769 if (file_mips_opts.soft_float) 3770 fpabi_incompatible_with (fpabi, "softfloat"); 3771 else if (file_mips_opts.single_float) 3772 fpabi_incompatible_with (fpabi, "singlefloat"); 3773 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) 3774 fpabi_incompatible_with (fpabi, "gp=64 fp=32"); 3775 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) 3776 fpabi_incompatible_with (fpabi, "gp=32 fp=64"); 3777 break; 3778 3779 case Val_GNU_MIPS_ABI_FP_XX: 3780 if (mips_abi != O32_ABI) 3781 fpabi_requires (fpabi, "-mabi=32"); 3782 else if (file_mips_opts.soft_float) 3783 fpabi_incompatible_with (fpabi, "softfloat"); 3784 else if (file_mips_opts.single_float) 3785 fpabi_incompatible_with (fpabi, "singlefloat"); 3786 else if (file_mips_opts.fp != 0) 3787 fpabi_requires (fpabi, "fp=xx"); 3788 break; 3789 3790 case Val_GNU_MIPS_ABI_FP_64A: 3791 case Val_GNU_MIPS_ABI_FP_64: 3792 if (mips_abi != O32_ABI) 3793 fpabi_requires (fpabi, "-mabi=32"); 3794 else if (file_mips_opts.soft_float) 3795 fpabi_incompatible_with (fpabi, "softfloat"); 3796 else if (file_mips_opts.single_float) 3797 fpabi_incompatible_with (fpabi, "singlefloat"); 3798 else if (file_mips_opts.fp != 64) 3799 fpabi_requires (fpabi, "fp=64"); 3800 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) 3801 fpabi_incompatible_with (fpabi, "nooddspreg"); 3802 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) 3803 fpabi_requires (fpabi, "nooddspreg"); 3804 break; 3805 3806 case Val_GNU_MIPS_ABI_FP_SINGLE: 3807 if (file_mips_opts.soft_float) 3808 fpabi_incompatible_with (fpabi, "softfloat"); 3809 else if (!file_mips_opts.single_float) 3810 fpabi_requires (fpabi, "singlefloat"); 3811 break; 3812 3813 case Val_GNU_MIPS_ABI_FP_SOFT: 3814 if (!file_mips_opts.soft_float) 3815 fpabi_requires (fpabi, "softfloat"); 3816 break; 3817 3818 case Val_GNU_MIPS_ABI_FP_OLD_64: 3819 as_warn (_(".gnu_attribute %d,%d is no longer supported"), 3820 Tag_GNU_MIPS_ABI_FP, fpabi); 3821 break; 3822 3823 case Val_GNU_MIPS_ABI_FP_NAN2008: 3824 /* Silently ignore compatibility value. */ 3825 break; 3826 3827 default: 3828 as_warn (_(".gnu_attribute %d,%d is not a recognized" 3829 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); 3830 break; 3831 } 3832 } 3833 3834 /* Perform consistency checks on the current options. */ 3835 3836 static void 3837 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) 3838 { 3839 /* Check the size of integer registers agrees with the ABI and ISA. */ 3840 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) 3841 as_bad (_("`gp=64' used with a 32-bit processor")); 3842 else if (abi_checks 3843 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) 3844 as_bad (_("`gp=32' used with a 64-bit ABI")); 3845 else if (abi_checks 3846 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) 3847 as_bad (_("`gp=64' used with a 32-bit ABI")); 3848 3849 /* Check the size of the float registers agrees with the ABI and ISA. */ 3850 switch (opts->fp) 3851 { 3852 case 0: 3853 if (!CPU_HAS_LDC1_SDC1 (opts->arch)) 3854 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); 3855 else if (opts->single_float == 1) 3856 as_bad (_("`fp=xx' cannot be used with `singlefloat'")); 3857 break; 3858 case 64: 3859 if (!ISA_HAS_64BIT_FPRS (opts->isa)) 3860 as_bad (_("`fp=64' used with a 32-bit fpu")); 3861 else if (abi_checks 3862 && ABI_NEEDS_32BIT_REGS (mips_abi) 3863 && !ISA_HAS_MXHC1 (opts->isa)) 3864 as_warn (_("`fp=64' used with a 32-bit ABI")); 3865 break; 3866 case 32: 3867 if (abi_checks 3868 && ABI_NEEDS_64BIT_REGS (mips_abi)) 3869 as_warn (_("`fp=32' used with a 64-bit ABI")); 3870 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) 3871 as_bad (_("`fp=32' used with a MIPS R6 cpu")); 3872 break; 3873 default: 3874 as_bad (_("Unknown size of floating point registers")); 3875 break; 3876 } 3877 3878 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) 3879 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); 3880 3881 if (opts->micromips == 1 && opts->mips16 == 1) 3882 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); 3883 else if (ISA_IS_R6 (opts->isa) 3884 && (opts->micromips == 1 3885 || opts->mips16 == 1)) 3886 as_fatal (_("`%s' cannot be used with `%s'"), 3887 opts->micromips ? "micromips" : "mips16", 3888 mips_cpu_info_from_isa (opts->isa)->name); 3889 3890 if (ISA_IS_R6 (opts->isa) && mips_relax_branch) 3891 as_fatal (_("branch relaxation is not supported in `%s'"), 3892 mips_cpu_info_from_isa (opts->isa)->name); 3893 } 3894 3895 /* Perform consistency checks on the module level options exactly once. 3896 This is a deferred check that happens: 3897 at the first .set directive 3898 or, at the first pseudo op that generates code (inc .dc.a) 3899 or, at the first instruction 3900 or, at the end. */ 3901 3902 static void 3903 file_mips_check_options (void) 3904 { 3905 const struct mips_cpu_info *arch_info = 0; 3906 3907 if (file_mips_opts_checked) 3908 return; 3909 3910 /* The following code determines the register size. 3911 Similar code was added to GCC 3.3 (see override_options() in 3912 config/mips/mips.c). The GAS and GCC code should be kept in sync 3913 as much as possible. */ 3914 3915 if (file_mips_opts.gp < 0) 3916 { 3917 /* Infer the integer register size from the ABI and processor. 3918 Restrict ourselves to 32-bit registers if that's all the 3919 processor has, or if the ABI cannot handle 64-bit registers. */ 3920 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) 3921 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) 3922 ? 32 : 64; 3923 } 3924 3925 if (file_mips_opts.fp < 0) 3926 { 3927 /* No user specified float register size. 3928 ??? GAS treats single-float processors as though they had 64-bit 3929 float registers (although it complains when double-precision 3930 instructions are used). As things stand, saying they have 32-bit 3931 registers would lead to spurious "register must be even" messages. 3932 So here we assume float registers are never smaller than the 3933 integer ones. */ 3934 if (file_mips_opts.gp == 64) 3935 /* 64-bit integer registers implies 64-bit float registers. */ 3936 file_mips_opts.fp = 64; 3937 else if ((file_mips_opts.ase & FP64_ASES) 3938 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) 3939 /* Handle ASEs that require 64-bit float registers, if possible. */ 3940 file_mips_opts.fp = 64; 3941 else if (ISA_IS_R6 (mips_opts.isa)) 3942 /* R6 implies 64-bit float registers. */ 3943 file_mips_opts.fp = 64; 3944 else 3945 /* 32-bit float registers. */ 3946 file_mips_opts.fp = 32; 3947 } 3948 3949 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); 3950 3951 /* Disable operations on odd-numbered floating-point registers by default 3952 when using the FPXX ABI. */ 3953 if (file_mips_opts.oddspreg < 0) 3954 { 3955 if (file_mips_opts.fp == 0) 3956 file_mips_opts.oddspreg = 0; 3957 else 3958 file_mips_opts.oddspreg = 1; 3959 } 3960 3961 /* End of GCC-shared inference code. */ 3962 3963 /* This flag is set when we have a 64-bit capable CPU but use only 3964 32-bit wide registers. Note that EABI does not use it. */ 3965 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) 3966 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) 3967 || mips_abi == O32_ABI)) 3968 mips_32bitmode = 1; 3969 3970 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) 3971 as_bad (_("trap exception not supported at ISA 1")); 3972 3973 /* If the selected architecture includes support for ASEs, enable 3974 generation of code for them. */ 3975 if (file_mips_opts.mips16 == -1) 3976 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; 3977 if (file_mips_opts.micromips == -1) 3978 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) 3979 ? 1 : 0; 3980 3981 if (mips_nan2008 == -1) 3982 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; 3983 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) 3984 as_fatal (_("`%s' does not support legacy NaN"), 3985 mips_cpu_info_from_arch (file_mips_opts.arch)->name); 3986 3987 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from 3988 being selected implicitly. */ 3989 if (file_mips_opts.fp != 64) 3990 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; 3991 3992 /* If the user didn't explicitly select or deselect a particular ASE, 3993 use the default setting for the CPU. */ 3994 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); 3995 3996 /* Set up the current options. These may change throughout assembly. */ 3997 mips_opts = file_mips_opts; 3998 3999 mips_check_isa_supports_ases (); 4000 mips_check_options (&file_mips_opts, TRUE); 4001 file_mips_opts_checked = TRUE; 4002 4003 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 4004 as_warn (_("could not set architecture and machine")); 4005 } 4006 4007 void 4008 md_assemble (char *str) 4009 { 4010 struct mips_cl_insn insn; 4011 bfd_reloc_code_real_type unused_reloc[3] 4012 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 4013 4014 file_mips_check_options (); 4015 4016 imm_expr.X_op = O_absent; 4017 offset_expr.X_op = O_absent; 4018 offset_reloc[0] = BFD_RELOC_UNUSED; 4019 offset_reloc[1] = BFD_RELOC_UNUSED; 4020 offset_reloc[2] = BFD_RELOC_UNUSED; 4021 4022 mips_mark_labels (); 4023 mips_assembling_insn = TRUE; 4024 clear_insn_error (); 4025 4026 if (mips_opts.mips16) 4027 mips16_ip (str, &insn); 4028 else 4029 { 4030 mips_ip (str, &insn); 4031 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), 4032 str, insn.insn_opcode)); 4033 } 4034 4035 if (insn_error.msg) 4036 report_insn_error (str); 4037 else if (insn.insn_mo->pinfo == INSN_MACRO) 4038 { 4039 macro_start (); 4040 if (mips_opts.mips16) 4041 mips16_macro (&insn); 4042 else 4043 macro (&insn, str); 4044 macro_end (); 4045 } 4046 else 4047 { 4048 if (offset_expr.X_op != O_absent) 4049 append_insn (&insn, &offset_expr, offset_reloc, FALSE); 4050 else 4051 append_insn (&insn, NULL, unused_reloc, FALSE); 4052 } 4053 4054 mips_assembling_insn = FALSE; 4055 } 4056 4057 /* Convenience functions for abstracting away the differences between 4058 MIPS16 and non-MIPS16 relocations. */ 4059 4060 static inline bfd_boolean 4061 mips16_reloc_p (bfd_reloc_code_real_type reloc) 4062 { 4063 switch (reloc) 4064 { 4065 case BFD_RELOC_MIPS16_JMP: 4066 case BFD_RELOC_MIPS16_GPREL: 4067 case BFD_RELOC_MIPS16_GOT16: 4068 case BFD_RELOC_MIPS16_CALL16: 4069 case BFD_RELOC_MIPS16_HI16_S: 4070 case BFD_RELOC_MIPS16_HI16: 4071 case BFD_RELOC_MIPS16_LO16: 4072 case BFD_RELOC_MIPS16_16_PCREL_S1: 4073 return TRUE; 4074 4075 default: 4076 return FALSE; 4077 } 4078 } 4079 4080 static inline bfd_boolean 4081 micromips_reloc_p (bfd_reloc_code_real_type reloc) 4082 { 4083 switch (reloc) 4084 { 4085 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4086 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4087 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4088 case BFD_RELOC_MICROMIPS_GPREL16: 4089 case BFD_RELOC_MICROMIPS_JMP: 4090 case BFD_RELOC_MICROMIPS_HI16: 4091 case BFD_RELOC_MICROMIPS_HI16_S: 4092 case BFD_RELOC_MICROMIPS_LO16: 4093 case BFD_RELOC_MICROMIPS_LITERAL: 4094 case BFD_RELOC_MICROMIPS_GOT16: 4095 case BFD_RELOC_MICROMIPS_CALL16: 4096 case BFD_RELOC_MICROMIPS_GOT_HI16: 4097 case BFD_RELOC_MICROMIPS_GOT_LO16: 4098 case BFD_RELOC_MICROMIPS_CALL_HI16: 4099 case BFD_RELOC_MICROMIPS_CALL_LO16: 4100 case BFD_RELOC_MICROMIPS_SUB: 4101 case BFD_RELOC_MICROMIPS_GOT_PAGE: 4102 case BFD_RELOC_MICROMIPS_GOT_OFST: 4103 case BFD_RELOC_MICROMIPS_GOT_DISP: 4104 case BFD_RELOC_MICROMIPS_HIGHEST: 4105 case BFD_RELOC_MICROMIPS_HIGHER: 4106 case BFD_RELOC_MICROMIPS_SCN_DISP: 4107 case BFD_RELOC_MICROMIPS_JALR: 4108 return TRUE; 4109 4110 default: 4111 return FALSE; 4112 } 4113 } 4114 4115 static inline bfd_boolean 4116 jmp_reloc_p (bfd_reloc_code_real_type reloc) 4117 { 4118 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; 4119 } 4120 4121 static inline bfd_boolean 4122 b_reloc_p (bfd_reloc_code_real_type reloc) 4123 { 4124 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 4125 || reloc == BFD_RELOC_MIPS_21_PCREL_S2 4126 || reloc == BFD_RELOC_16_PCREL_S2 4127 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 4128 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 4129 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 4130 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); 4131 } 4132 4133 static inline bfd_boolean 4134 got16_reloc_p (bfd_reloc_code_real_type reloc) 4135 { 4136 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 4137 || reloc == BFD_RELOC_MICROMIPS_GOT16); 4138 } 4139 4140 static inline bfd_boolean 4141 hi16_reloc_p (bfd_reloc_code_real_type reloc) 4142 { 4143 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S 4144 || reloc == BFD_RELOC_MICROMIPS_HI16_S); 4145 } 4146 4147 static inline bfd_boolean 4148 lo16_reloc_p (bfd_reloc_code_real_type reloc) 4149 { 4150 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 4151 || reloc == BFD_RELOC_MICROMIPS_LO16); 4152 } 4153 4154 static inline bfd_boolean 4155 jalr_reloc_p (bfd_reloc_code_real_type reloc) 4156 { 4157 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; 4158 } 4159 4160 static inline bfd_boolean 4161 gprel16_reloc_p (bfd_reloc_code_real_type reloc) 4162 { 4163 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL 4164 || reloc == BFD_RELOC_MICROMIPS_GPREL16); 4165 } 4166 4167 /* Return true if RELOC is a PC-relative relocation that does not have 4168 full address range. */ 4169 4170 static inline bfd_boolean 4171 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) 4172 { 4173 switch (reloc) 4174 { 4175 case BFD_RELOC_16_PCREL_S2: 4176 case BFD_RELOC_MIPS16_16_PCREL_S1: 4177 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4178 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4179 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4180 case BFD_RELOC_MIPS_21_PCREL_S2: 4181 case BFD_RELOC_MIPS_26_PCREL_S2: 4182 case BFD_RELOC_MIPS_18_PCREL_S3: 4183 case BFD_RELOC_MIPS_19_PCREL_S2: 4184 return TRUE; 4185 4186 case BFD_RELOC_32_PCREL: 4187 case BFD_RELOC_HI16_S_PCREL: 4188 case BFD_RELOC_LO16_PCREL: 4189 return HAVE_64BIT_ADDRESSES; 4190 4191 default: 4192 return FALSE; 4193 } 4194 } 4195 4196 /* Return true if the given relocation might need a matching %lo(). 4197 This is only "might" because SVR4 R_MIPS_GOT16 relocations only 4198 need a matching %lo() when applied to local symbols. */ 4199 4200 static inline bfd_boolean 4201 reloc_needs_lo_p (bfd_reloc_code_real_type reloc) 4202 { 4203 return (HAVE_IN_PLACE_ADDENDS 4204 && (hi16_reloc_p (reloc) 4205 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); 4206 all GOT16 relocations evaluate to "G". */ 4207 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); 4208 } 4209 4210 /* Return the type of %lo() reloc needed by RELOC, given that 4211 reloc_needs_lo_p. */ 4212 4213 static inline bfd_reloc_code_real_type 4214 matching_lo_reloc (bfd_reloc_code_real_type reloc) 4215 { 4216 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 4217 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 4218 : BFD_RELOC_LO16)); 4219 } 4220 4221 /* Return true if the given fixup is followed by a matching R_MIPS_LO16 4222 relocation. */ 4223 4224 static inline bfd_boolean 4225 fixup_has_matching_lo_p (fixS *fixp) 4226 { 4227 return (fixp->fx_next != NULL 4228 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) 4229 && fixp->fx_addsy == fixp->fx_next->fx_addsy 4230 && fixp->fx_offset == fixp->fx_next->fx_offset); 4231 } 4232 4233 /* Move all labels in LABELS to the current insertion point. TEXT_P 4234 says whether the labels refer to text or data. */ 4235 4236 static void 4237 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) 4238 { 4239 struct insn_label_list *l; 4240 valueT val; 4241 4242 for (l = labels; l != NULL; l = l->next) 4243 { 4244 gas_assert (S_GET_SEGMENT (l->label) == now_seg); 4245 symbol_set_frag (l->label, frag_now); 4246 val = (valueT) frag_now_fix (); 4247 /* MIPS16/microMIPS text labels are stored as odd. */ 4248 if (text_p && HAVE_CODE_COMPRESSION) 4249 ++val; 4250 S_SET_VALUE (l->label, val); 4251 } 4252 } 4253 4254 /* Move all labels in insn_labels to the current insertion point 4255 and treat them as text labels. */ 4256 4257 static void 4258 mips_move_text_labels (void) 4259 { 4260 mips_move_labels (seg_info (now_seg)->label_list, TRUE); 4261 } 4262 4263 static bfd_boolean 4264 s_is_linkonce (symbolS *sym, segT from_seg) 4265 { 4266 bfd_boolean linkonce = FALSE; 4267 segT symseg = S_GET_SEGMENT (sym); 4268 4269 if (symseg != from_seg && !S_IS_LOCAL (sym)) 4270 { 4271 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) 4272 linkonce = TRUE; 4273 /* The GNU toolchain uses an extension for ELF: a section 4274 beginning with the magic string .gnu.linkonce is a 4275 linkonce section. */ 4276 if (strncmp (segment_name (symseg), ".gnu.linkonce", 4277 sizeof ".gnu.linkonce" - 1) == 0) 4278 linkonce = TRUE; 4279 } 4280 return linkonce; 4281 } 4282 4283 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the 4284 linker to handle them specially, such as generating jalx instructions 4285 when needed. We also make them odd for the duration of the assembly, 4286 in order to generate the right sort of code. We will make them even 4287 in the adjust_symtab routine, while leaving them marked. This is 4288 convenient for the debugger and the disassembler. The linker knows 4289 to make them odd again. */ 4290 4291 static void 4292 mips_compressed_mark_label (symbolS *label) 4293 { 4294 gas_assert (HAVE_CODE_COMPRESSION); 4295 4296 if (mips_opts.mips16) 4297 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); 4298 else 4299 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); 4300 if ((S_GET_VALUE (label) & 1) == 0 4301 /* Don't adjust the address if the label is global or weak, or 4302 in a link-once section, since we'll be emitting symbol reloc 4303 references to it which will be patched up by the linker, and 4304 the final value of the symbol may or may not be MIPS16/microMIPS. */ 4305 && !S_IS_WEAK (label) 4306 && !S_IS_EXTERNAL (label) 4307 && !s_is_linkonce (label, now_seg)) 4308 S_SET_VALUE (label, S_GET_VALUE (label) | 1); 4309 } 4310 4311 /* Mark preceding MIPS16 or microMIPS instruction labels. */ 4312 4313 static void 4314 mips_compressed_mark_labels (void) 4315 { 4316 struct insn_label_list *l; 4317 4318 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) 4319 mips_compressed_mark_label (l->label); 4320 } 4321 4322 /* End the current frag. Make it a variant frag and record the 4323 relaxation info. */ 4324 4325 static void 4326 relax_close_frag (void) 4327 { 4328 mips_macro_warning.first_frag = frag_now; 4329 frag_var (rs_machine_dependent, 0, 0, 4330 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), 4331 mips_relax.symbol, 0, (char *) mips_relax.first_fixup); 4332 4333 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); 4334 mips_relax.first_fixup = 0; 4335 } 4336 4337 /* Start a new relaxation sequence whose expansion depends on SYMBOL. 4338 See the comment above RELAX_ENCODE for more details. */ 4339 4340 static void 4341 relax_start (symbolS *symbol) 4342 { 4343 gas_assert (mips_relax.sequence == 0); 4344 mips_relax.sequence = 1; 4345 mips_relax.symbol = symbol; 4346 } 4347 4348 /* Start generating the second version of a relaxable sequence. 4349 See the comment above RELAX_ENCODE for more details. */ 4350 4351 static void 4352 relax_switch (void) 4353 { 4354 gas_assert (mips_relax.sequence == 1); 4355 mips_relax.sequence = 2; 4356 } 4357 4358 /* End the current relaxable sequence. */ 4359 4360 static void 4361 relax_end (void) 4362 { 4363 gas_assert (mips_relax.sequence == 2); 4364 relax_close_frag (); 4365 mips_relax.sequence = 0; 4366 } 4367 4368 /* Return true if IP is a delayed branch or jump. */ 4369 4370 static inline bfd_boolean 4371 delayed_branch_p (const struct mips_cl_insn *ip) 4372 { 4373 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY 4374 | INSN_COND_BRANCH_DELAY 4375 | INSN_COND_BRANCH_LIKELY)) != 0; 4376 } 4377 4378 /* Return true if IP is a compact branch or jump. */ 4379 4380 static inline bfd_boolean 4381 compact_branch_p (const struct mips_cl_insn *ip) 4382 { 4383 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH 4384 | INSN2_COND_BRANCH)) != 0; 4385 } 4386 4387 /* Return true if IP is an unconditional branch or jump. */ 4388 4389 static inline bfd_boolean 4390 uncond_branch_p (const struct mips_cl_insn *ip) 4391 { 4392 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 4393 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); 4394 } 4395 4396 /* Return true if IP is a branch-likely instruction. */ 4397 4398 static inline bfd_boolean 4399 branch_likely_p (const struct mips_cl_insn *ip) 4400 { 4401 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; 4402 } 4403 4404 /* Return the type of nop that should be used to fill the delay slot 4405 of delayed branch IP. */ 4406 4407 static struct mips_cl_insn * 4408 get_delay_slot_nop (const struct mips_cl_insn *ip) 4409 { 4410 if (mips_opts.micromips 4411 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 4412 return µmips_nop32_insn; 4413 return NOP_INSN; 4414 } 4415 4416 /* Return a mask that has bit N set if OPCODE reads the register(s) 4417 in operand N. */ 4418 4419 static unsigned int 4420 insn_read_mask (const struct mips_opcode *opcode) 4421 { 4422 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; 4423 } 4424 4425 /* Return a mask that has bit N set if OPCODE writes to the register(s) 4426 in operand N. */ 4427 4428 static unsigned int 4429 insn_write_mask (const struct mips_opcode *opcode) 4430 { 4431 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; 4432 } 4433 4434 /* Return a mask of the registers specified by operand OPERAND of INSN. 4435 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4436 is set. */ 4437 4438 static unsigned int 4439 operand_reg_mask (const struct mips_cl_insn *insn, 4440 const struct mips_operand *operand, 4441 unsigned int type_mask) 4442 { 4443 unsigned int uval, vsel; 4444 4445 switch (operand->type) 4446 { 4447 case OP_INT: 4448 case OP_MAPPED_INT: 4449 case OP_MSB: 4450 case OP_PCREL: 4451 case OP_PERF_REG: 4452 case OP_ADDIUSP_INT: 4453 case OP_ENTRY_EXIT_LIST: 4454 case OP_REPEAT_DEST_REG: 4455 case OP_REPEAT_PREV_REG: 4456 case OP_PC: 4457 case OP_VU0_SUFFIX: 4458 case OP_VU0_MATCH_SUFFIX: 4459 case OP_IMM_INDEX: 4460 abort (); 4461 4462 case OP_REG: 4463 case OP_OPTIONAL_REG: 4464 { 4465 const struct mips_reg_operand *reg_op; 4466 4467 reg_op = (const struct mips_reg_operand *) operand; 4468 if (!(type_mask & (1 << reg_op->reg_type))) 4469 return 0; 4470 uval = insn_extract_operand (insn, operand); 4471 return 1 << mips_decode_reg_operand (reg_op, uval); 4472 } 4473 4474 case OP_REG_PAIR: 4475 { 4476 const struct mips_reg_pair_operand *pair_op; 4477 4478 pair_op = (const struct mips_reg_pair_operand *) operand; 4479 if (!(type_mask & (1 << pair_op->reg_type))) 4480 return 0; 4481 uval = insn_extract_operand (insn, operand); 4482 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); 4483 } 4484 4485 case OP_CLO_CLZ_DEST: 4486 if (!(type_mask & (1 << OP_REG_GP))) 4487 return 0; 4488 uval = insn_extract_operand (insn, operand); 4489 return (1 << (uval & 31)) | (1 << (uval >> 5)); 4490 4491 case OP_SAME_RS_RT: 4492 if (!(type_mask & (1 << OP_REG_GP))) 4493 return 0; 4494 uval = insn_extract_operand (insn, operand); 4495 gas_assert ((uval & 31) == (uval >> 5)); 4496 return 1 << (uval & 31); 4497 4498 case OP_CHECK_PREV: 4499 case OP_NON_ZERO_REG: 4500 if (!(type_mask & (1 << OP_REG_GP))) 4501 return 0; 4502 uval = insn_extract_operand (insn, operand); 4503 return 1 << (uval & 31); 4504 4505 case OP_LWM_SWM_LIST: 4506 abort (); 4507 4508 case OP_SAVE_RESTORE_LIST: 4509 abort (); 4510 4511 case OP_MDMX_IMM_REG: 4512 if (!(type_mask & (1 << OP_REG_VEC))) 4513 return 0; 4514 uval = insn_extract_operand (insn, operand); 4515 vsel = uval >> 5; 4516 if ((vsel & 0x18) == 0x18) 4517 return 0; 4518 return 1 << (uval & 31); 4519 4520 case OP_REG_INDEX: 4521 if (!(type_mask & (1 << OP_REG_GP))) 4522 return 0; 4523 return 1 << insn_extract_operand (insn, operand); 4524 } 4525 abort (); 4526 } 4527 4528 /* Return a mask of the registers specified by operands OPNO_MASK of INSN, 4529 where bit N of OPNO_MASK is set if operand N should be included. 4530 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4531 is set. */ 4532 4533 static unsigned int 4534 insn_reg_mask (const struct mips_cl_insn *insn, 4535 unsigned int type_mask, unsigned int opno_mask) 4536 { 4537 unsigned int opno, reg_mask; 4538 4539 opno = 0; 4540 reg_mask = 0; 4541 while (opno_mask != 0) 4542 { 4543 if (opno_mask & 1) 4544 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); 4545 opno_mask >>= 1; 4546 opno += 1; 4547 } 4548 return reg_mask; 4549 } 4550 4551 /* Return the mask of core registers that IP reads. */ 4552 4553 static unsigned int 4554 gpr_read_mask (const struct mips_cl_insn *ip) 4555 { 4556 unsigned long pinfo, pinfo2; 4557 unsigned int mask; 4558 4559 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); 4560 pinfo = ip->insn_mo->pinfo; 4561 pinfo2 = ip->insn_mo->pinfo2; 4562 if (pinfo & INSN_UDI) 4563 { 4564 /* UDI instructions have traditionally been assumed to read RS 4565 and RT. */ 4566 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); 4567 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); 4568 } 4569 if (pinfo & INSN_READ_GPR_24) 4570 mask |= 1 << 24; 4571 if (pinfo2 & INSN2_READ_GPR_16) 4572 mask |= 1 << 16; 4573 if (pinfo2 & INSN2_READ_SP) 4574 mask |= 1 << SP; 4575 if (pinfo2 & INSN2_READ_GPR_31) 4576 mask |= 1 << 31; 4577 /* Don't include register 0. */ 4578 return mask & ~1; 4579 } 4580 4581 /* Return the mask of core registers that IP writes. */ 4582 4583 static unsigned int 4584 gpr_write_mask (const struct mips_cl_insn *ip) 4585 { 4586 unsigned long pinfo, pinfo2; 4587 unsigned int mask; 4588 4589 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); 4590 pinfo = ip->insn_mo->pinfo; 4591 pinfo2 = ip->insn_mo->pinfo2; 4592 if (pinfo & INSN_WRITE_GPR_24) 4593 mask |= 1 << 24; 4594 if (pinfo & INSN_WRITE_GPR_31) 4595 mask |= 1 << 31; 4596 if (pinfo & INSN_UDI) 4597 /* UDI instructions have traditionally been assumed to write to RD. */ 4598 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); 4599 if (pinfo2 & INSN2_WRITE_SP) 4600 mask |= 1 << SP; 4601 /* Don't include register 0. */ 4602 return mask & ~1; 4603 } 4604 4605 /* Return the mask of floating-point registers that IP reads. */ 4606 4607 static unsigned int 4608 fpr_read_mask (const struct mips_cl_insn *ip) 4609 { 4610 unsigned long pinfo; 4611 unsigned int mask; 4612 4613 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4614 | (1 << OP_REG_MSA)), 4615 insn_read_mask (ip->insn_mo)); 4616 pinfo = ip->insn_mo->pinfo; 4617 /* Conservatively treat all operands to an FP_D instruction are doubles. 4618 (This is overly pessimistic for things like cvt.d.s.) */ 4619 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4620 mask |= mask << 1; 4621 return mask; 4622 } 4623 4624 /* Return the mask of floating-point registers that IP writes. */ 4625 4626 static unsigned int 4627 fpr_write_mask (const struct mips_cl_insn *ip) 4628 { 4629 unsigned long pinfo; 4630 unsigned int mask; 4631 4632 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4633 | (1 << OP_REG_MSA)), 4634 insn_write_mask (ip->insn_mo)); 4635 pinfo = ip->insn_mo->pinfo; 4636 /* Conservatively treat all operands to an FP_D instruction are doubles. 4637 (This is overly pessimistic for things like cvt.s.d.) */ 4638 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4639 mask |= mask << 1; 4640 return mask; 4641 } 4642 4643 /* Operand OPNUM of INSN is an odd-numbered floating-point register. 4644 Check whether that is allowed. */ 4645 4646 static bfd_boolean 4647 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) 4648 { 4649 const char *s = insn->name; 4650 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) 4651 || FPR_SIZE == 64) 4652 && mips_opts.oddspreg; 4653 4654 if (insn->pinfo == INSN_MACRO) 4655 /* Let a macro pass, we'll catch it later when it is expanded. */ 4656 return TRUE; 4657 4658 /* Single-precision coprocessor loads and moves are OK for 32-bit registers, 4659 otherwise it depends on oddspreg. */ 4660 if ((insn->pinfo & FP_S) 4661 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY 4662 | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) 4663 return FPR_SIZE == 32 || oddspreg; 4664 4665 /* Allow odd registers for single-precision ops and double-precision if the 4666 floating-point registers are 64-bit wide. */ 4667 switch (insn->pinfo & (FP_S | FP_D)) 4668 { 4669 case FP_S: 4670 case 0: 4671 return oddspreg; 4672 case FP_D: 4673 return FPR_SIZE == 64; 4674 default: 4675 break; 4676 } 4677 4678 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ 4679 s = strchr (insn->name, '.'); 4680 if (s != NULL && opnum == 2) 4681 s = strchr (s + 1, '.'); 4682 if (s != NULL && (s[1] == 'w' || s[1] == 's')) 4683 return oddspreg; 4684 4685 return FPR_SIZE == 64; 4686 } 4687 4688 /* Information about an instruction argument that we're trying to match. */ 4689 struct mips_arg_info 4690 { 4691 /* The instruction so far. */ 4692 struct mips_cl_insn *insn; 4693 4694 /* The first unconsumed operand token. */ 4695 struct mips_operand_token *token; 4696 4697 /* The 1-based operand number, in terms of insn->insn_mo->args. */ 4698 int opnum; 4699 4700 /* The 1-based argument number, for error reporting. This does not 4701 count elided optional registers, etc.. */ 4702 int argnum; 4703 4704 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ 4705 unsigned int last_regno; 4706 4707 /* If the first operand was an OP_REG, this is the register that it 4708 specified, otherwise it is ILLEGAL_REG. */ 4709 unsigned int dest_regno; 4710 4711 /* The value of the last OP_INT operand. Only used for OP_MSB, 4712 where it gives the lsb position. */ 4713 unsigned int last_op_int; 4714 4715 /* If true, match routines should assume that no later instruction 4716 alternative matches and should therefore be as accomodating as 4717 possible. Match routines should not report errors if something 4718 is only invalid for !LAX_MATCH. */ 4719 bfd_boolean lax_match; 4720 4721 /* True if a reference to the current AT register was seen. */ 4722 bfd_boolean seen_at; 4723 }; 4724 4725 /* Record that the argument is out of range. */ 4726 4727 static void 4728 match_out_of_range (struct mips_arg_info *arg) 4729 { 4730 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); 4731 } 4732 4733 /* Record that the argument isn't constant but needs to be. */ 4734 4735 static void 4736 match_not_constant (struct mips_arg_info *arg) 4737 { 4738 set_insn_error_i (arg->argnum, _("operand %d must be constant"), 4739 arg->argnum); 4740 } 4741 4742 /* Try to match an OT_CHAR token for character CH. Consume the token 4743 and return true on success, otherwise return false. */ 4744 4745 static bfd_boolean 4746 match_char (struct mips_arg_info *arg, char ch) 4747 { 4748 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) 4749 { 4750 ++arg->token; 4751 if (ch == ',') 4752 arg->argnum += 1; 4753 return TRUE; 4754 } 4755 return FALSE; 4756 } 4757 4758 /* Try to get an expression from the next tokens in ARG. Consume the 4759 tokens and return true on success, storing the expression value in 4760 VALUE and relocation types in R. */ 4761 4762 static bfd_boolean 4763 match_expression (struct mips_arg_info *arg, expressionS *value, 4764 bfd_reloc_code_real_type *r) 4765 { 4766 /* If the next token is a '(' that was parsed as being part of a base 4767 expression, assume we have an elided offset. The later match will fail 4768 if this turns out to be wrong. */ 4769 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') 4770 { 4771 value->X_op = O_constant; 4772 value->X_add_number = 0; 4773 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; 4774 return TRUE; 4775 } 4776 4777 /* Reject register-based expressions such as "0+$2" and "(($2))". 4778 For plain registers the default error seems more appropriate. */ 4779 if (arg->token->type == OT_INTEGER 4780 && arg->token->u.integer.value.X_op == O_register) 4781 { 4782 set_insn_error (arg->argnum, _("register value used as expression")); 4783 return FALSE; 4784 } 4785 4786 if (arg->token->type == OT_INTEGER) 4787 { 4788 *value = arg->token->u.integer.value; 4789 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); 4790 ++arg->token; 4791 return TRUE; 4792 } 4793 4794 set_insn_error_i 4795 (arg->argnum, _("operand %d must be an immediate expression"), 4796 arg->argnum); 4797 return FALSE; 4798 } 4799 4800 /* Try to get a constant expression from the next tokens in ARG. Consume 4801 the tokens and return return true on success, storing the constant value 4802 in *VALUE. Use FALLBACK as the value if the match succeeded with an 4803 error. */ 4804 4805 static bfd_boolean 4806 match_const_int (struct mips_arg_info *arg, offsetT *value) 4807 { 4808 expressionS ex; 4809 bfd_reloc_code_real_type r[3]; 4810 4811 if (!match_expression (arg, &ex, r)) 4812 return FALSE; 4813 4814 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) 4815 *value = ex.X_add_number; 4816 else 4817 { 4818 match_not_constant (arg); 4819 return FALSE; 4820 } 4821 return TRUE; 4822 } 4823 4824 /* Return the RTYPE_* flags for a register operand of type TYPE that 4825 appears in instruction OPCODE. */ 4826 4827 static unsigned int 4828 convert_reg_type (const struct mips_opcode *opcode, 4829 enum mips_reg_operand_type type) 4830 { 4831 switch (type) 4832 { 4833 case OP_REG_GP: 4834 return RTYPE_NUM | RTYPE_GP; 4835 4836 case OP_REG_FP: 4837 /* Allow vector register names for MDMX if the instruction is a 64-bit 4838 FPR load, store or move (including moves to and from GPRs). */ 4839 if ((mips_opts.ase & ASE_MDMX) 4840 && (opcode->pinfo & FP_D) 4841 && (opcode->pinfo & (INSN_COPROC_MOVE 4842 | INSN_COPROC_MEMORY_DELAY 4843 | INSN_LOAD_COPROC 4844 | INSN_LOAD_MEMORY 4845 | INSN_STORE_MEMORY))) 4846 return RTYPE_FPU | RTYPE_VEC; 4847 return RTYPE_FPU; 4848 4849 case OP_REG_CCC: 4850 if (opcode->pinfo & (FP_D | FP_S)) 4851 return RTYPE_CCC | RTYPE_FCC; 4852 return RTYPE_CCC; 4853 4854 case OP_REG_VEC: 4855 if (opcode->membership & INSN_5400) 4856 return RTYPE_FPU; 4857 return RTYPE_FPU | RTYPE_VEC; 4858 4859 case OP_REG_ACC: 4860 return RTYPE_ACC; 4861 4862 case OP_REG_COPRO: 4863 if (opcode->name[strlen (opcode->name) - 1] == '0') 4864 return RTYPE_NUM | RTYPE_CP0; 4865 return RTYPE_NUM; 4866 4867 case OP_REG_HW: 4868 return RTYPE_NUM; 4869 4870 case OP_REG_VI: 4871 return RTYPE_NUM | RTYPE_VI; 4872 4873 case OP_REG_VF: 4874 return RTYPE_NUM | RTYPE_VF; 4875 4876 case OP_REG_R5900_I: 4877 return RTYPE_R5900_I; 4878 4879 case OP_REG_R5900_Q: 4880 return RTYPE_R5900_Q; 4881 4882 case OP_REG_R5900_R: 4883 return RTYPE_R5900_R; 4884 4885 case OP_REG_R5900_ACC: 4886 return RTYPE_R5900_ACC; 4887 4888 case OP_REG_MSA: 4889 return RTYPE_MSA; 4890 4891 case OP_REG_MSA_CTRL: 4892 return RTYPE_NUM; 4893 } 4894 abort (); 4895 } 4896 4897 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ 4898 4899 static void 4900 check_regno (struct mips_arg_info *arg, 4901 enum mips_reg_operand_type type, unsigned int regno) 4902 { 4903 if (AT && type == OP_REG_GP && regno == AT) 4904 arg->seen_at = TRUE; 4905 4906 if (type == OP_REG_FP 4907 && (regno & 1) != 0 4908 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) 4909 { 4910 /* This was a warning prior to introducing O32 FPXX and FP64 support 4911 so maintain a warning for FP32 but raise an error for the new 4912 cases. */ 4913 if (FPR_SIZE == 32) 4914 as_warn (_("float register should be even, was %d"), regno); 4915 else 4916 as_bad (_("float register should be even, was %d"), regno); 4917 } 4918 4919 if (type == OP_REG_CCC) 4920 { 4921 const char *name; 4922 size_t length; 4923 4924 name = arg->insn->insn_mo->name; 4925 length = strlen (name); 4926 if ((regno & 1) != 0 4927 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) 4928 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) 4929 as_warn (_("condition code register should be even for %s, was %d"), 4930 name, regno); 4931 4932 if ((regno & 3) != 0 4933 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) 4934 as_warn (_("condition code register should be 0 or 4 for %s, was %d"), 4935 name, regno); 4936 } 4937 } 4938 4939 /* ARG is a register with symbol value SYMVAL. Try to interpret it as 4940 a register of type TYPE. Return true on success, storing the register 4941 number in *REGNO and warning about any dubious uses. */ 4942 4943 static bfd_boolean 4944 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4945 unsigned int symval, unsigned int *regno) 4946 { 4947 if (type == OP_REG_VEC) 4948 symval = mips_prefer_vec_regno (symval); 4949 if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) 4950 return FALSE; 4951 4952 *regno = symval & RNUM_MASK; 4953 check_regno (arg, type, *regno); 4954 return TRUE; 4955 } 4956 4957 /* Try to interpret the next token in ARG as a register of type TYPE. 4958 Consume the token and return true on success, storing the register 4959 number in *REGNO. Return false on failure. */ 4960 4961 static bfd_boolean 4962 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4963 unsigned int *regno) 4964 { 4965 if (arg->token->type == OT_REG 4966 && match_regno (arg, type, arg->token->u.regno, regno)) 4967 { 4968 ++arg->token; 4969 return TRUE; 4970 } 4971 return FALSE; 4972 } 4973 4974 /* Try to interpret the next token in ARG as a range of registers of type TYPE. 4975 Consume the token and return true on success, storing the register numbers 4976 in *REGNO1 and *REGNO2. Return false on failure. */ 4977 4978 static bfd_boolean 4979 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4980 unsigned int *regno1, unsigned int *regno2) 4981 { 4982 if (match_reg (arg, type, regno1)) 4983 { 4984 *regno2 = *regno1; 4985 return TRUE; 4986 } 4987 if (arg->token->type == OT_REG_RANGE 4988 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) 4989 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) 4990 && *regno1 <= *regno2) 4991 { 4992 ++arg->token; 4993 return TRUE; 4994 } 4995 return FALSE; 4996 } 4997 4998 /* OP_INT matcher. */ 4999 5000 static bfd_boolean 5001 match_int_operand (struct mips_arg_info *arg, 5002 const struct mips_operand *operand_base) 5003 { 5004 const struct mips_int_operand *operand; 5005 unsigned int uval; 5006 int min_val, max_val, factor; 5007 offsetT sval; 5008 5009 operand = (const struct mips_int_operand *) operand_base; 5010 factor = 1 << operand->shift; 5011 min_val = mips_int_operand_min (operand); 5012 max_val = mips_int_operand_max (operand); 5013 5014 if (operand_base->lsb == 0 5015 && operand_base->size == 16 5016 && operand->shift == 0 5017 && operand->bias == 0 5018 && (operand->max_val == 32767 || operand->max_val == 65535)) 5019 { 5020 /* The operand can be relocated. */ 5021 if (!match_expression (arg, &offset_expr, offset_reloc)) 5022 return FALSE; 5023 5024 if (offset_reloc[0] != BFD_RELOC_UNUSED) 5025 /* Relocation operators were used. Accept the arguent and 5026 leave the relocation value in offset_expr and offset_relocs 5027 for the caller to process. */ 5028 return TRUE; 5029 5030 if (offset_expr.X_op != O_constant) 5031 { 5032 /* Accept non-constant operands if no later alternative matches, 5033 leaving it for the caller to process. */ 5034 if (!arg->lax_match) 5035 return FALSE; 5036 offset_reloc[0] = BFD_RELOC_LO16; 5037 return TRUE; 5038 } 5039 5040 /* Clear the global state; we're going to install the operand 5041 ourselves. */ 5042 sval = offset_expr.X_add_number; 5043 offset_expr.X_op = O_absent; 5044 5045 /* For compatibility with older assemblers, we accept 5046 0x8000-0xffff as signed 16-bit numbers when only 5047 signed numbers are allowed. */ 5048 if (sval > max_val) 5049 { 5050 max_val = ((1 << operand_base->size) - 1) << operand->shift; 5051 if (!arg->lax_match && sval <= max_val) 5052 return FALSE; 5053 } 5054 } 5055 else 5056 { 5057 if (!match_const_int (arg, &sval)) 5058 return FALSE; 5059 } 5060 5061 arg->last_op_int = sval; 5062 5063 if (sval < min_val || sval > max_val || sval % factor) 5064 { 5065 match_out_of_range (arg); 5066 return FALSE; 5067 } 5068 5069 uval = (unsigned int) sval >> operand->shift; 5070 uval -= operand->bias; 5071 5072 /* Handle -mfix-cn63xxp1. */ 5073 if (arg->opnum == 1 5074 && mips_fix_cn63xxp1 5075 && !mips_opts.micromips 5076 && strcmp ("pref", arg->insn->insn_mo->name) == 0) 5077 switch (uval) 5078 { 5079 case 5: 5080 case 25: 5081 case 26: 5082 case 27: 5083 case 28: 5084 case 29: 5085 case 30: 5086 case 31: 5087 /* These are ok. */ 5088 break; 5089 5090 default: 5091 /* The rest must be changed to 28. */ 5092 uval = 28; 5093 break; 5094 } 5095 5096 insn_insert_operand (arg->insn, operand_base, uval); 5097 return TRUE; 5098 } 5099 5100 /* OP_MAPPED_INT matcher. */ 5101 5102 static bfd_boolean 5103 match_mapped_int_operand (struct mips_arg_info *arg, 5104 const struct mips_operand *operand_base) 5105 { 5106 const struct mips_mapped_int_operand *operand; 5107 unsigned int uval, num_vals; 5108 offsetT sval; 5109 5110 operand = (const struct mips_mapped_int_operand *) operand_base; 5111 if (!match_const_int (arg, &sval)) 5112 return FALSE; 5113 5114 num_vals = 1 << operand_base->size; 5115 for (uval = 0; uval < num_vals; uval++) 5116 if (operand->int_map[uval] == sval) 5117 break; 5118 if (uval == num_vals) 5119 { 5120 match_out_of_range (arg); 5121 return FALSE; 5122 } 5123 5124 insn_insert_operand (arg->insn, operand_base, uval); 5125 return TRUE; 5126 } 5127 5128 /* OP_MSB matcher. */ 5129 5130 static bfd_boolean 5131 match_msb_operand (struct mips_arg_info *arg, 5132 const struct mips_operand *operand_base) 5133 { 5134 const struct mips_msb_operand *operand; 5135 int min_val, max_val, max_high; 5136 offsetT size, sval, high; 5137 5138 operand = (const struct mips_msb_operand *) operand_base; 5139 min_val = operand->bias; 5140 max_val = min_val + (1 << operand_base->size) - 1; 5141 max_high = operand->opsize; 5142 5143 if (!match_const_int (arg, &size)) 5144 return FALSE; 5145 5146 high = size + arg->last_op_int; 5147 sval = operand->add_lsb ? high : size; 5148 5149 if (size < 0 || high > max_high || sval < min_val || sval > max_val) 5150 { 5151 match_out_of_range (arg); 5152 return FALSE; 5153 } 5154 insn_insert_operand (arg->insn, operand_base, sval - min_val); 5155 return TRUE; 5156 } 5157 5158 /* OP_REG matcher. */ 5159 5160 static bfd_boolean 5161 match_reg_operand (struct mips_arg_info *arg, 5162 const struct mips_operand *operand_base) 5163 { 5164 const struct mips_reg_operand *operand; 5165 unsigned int regno, uval, num_vals; 5166 5167 operand = (const struct mips_reg_operand *) operand_base; 5168 if (!match_reg (arg, operand->reg_type, ®no)) 5169 return FALSE; 5170 5171 if (operand->reg_map) 5172 { 5173 num_vals = 1 << operand->root.size; 5174 for (uval = 0; uval < num_vals; uval++) 5175 if (operand->reg_map[uval] == regno) 5176 break; 5177 if (num_vals == uval) 5178 return FALSE; 5179 } 5180 else 5181 uval = regno; 5182 5183 arg->last_regno = regno; 5184 if (arg->opnum == 1) 5185 arg->dest_regno = regno; 5186 insn_insert_operand (arg->insn, operand_base, uval); 5187 return TRUE; 5188 } 5189 5190 /* OP_REG_PAIR matcher. */ 5191 5192 static bfd_boolean 5193 match_reg_pair_operand (struct mips_arg_info *arg, 5194 const struct mips_operand *operand_base) 5195 { 5196 const struct mips_reg_pair_operand *operand; 5197 unsigned int regno1, regno2, uval, num_vals; 5198 5199 operand = (const struct mips_reg_pair_operand *) operand_base; 5200 if (!match_reg (arg, operand->reg_type, ®no1) 5201 || !match_char (arg, ',') 5202 || !match_reg (arg, operand->reg_type, ®no2)) 5203 return FALSE; 5204 5205 num_vals = 1 << operand_base->size; 5206 for (uval = 0; uval < num_vals; uval++) 5207 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) 5208 break; 5209 if (uval == num_vals) 5210 return FALSE; 5211 5212 insn_insert_operand (arg->insn, operand_base, uval); 5213 return TRUE; 5214 } 5215 5216 /* OP_PCREL matcher. The caller chooses the relocation type. */ 5217 5218 static bfd_boolean 5219 match_pcrel_operand (struct mips_arg_info *arg) 5220 { 5221 bfd_reloc_code_real_type r[3]; 5222 5223 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; 5224 } 5225 5226 /* OP_PERF_REG matcher. */ 5227 5228 static bfd_boolean 5229 match_perf_reg_operand (struct mips_arg_info *arg, 5230 const struct mips_operand *operand) 5231 { 5232 offsetT sval; 5233 5234 if (!match_const_int (arg, &sval)) 5235 return FALSE; 5236 5237 if (sval != 0 5238 && (sval != 1 5239 || (mips_opts.arch == CPU_R5900 5240 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 5241 || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) 5242 { 5243 set_insn_error (arg->argnum, _("invalid performance register")); 5244 return FALSE; 5245 } 5246 5247 insn_insert_operand (arg->insn, operand, sval); 5248 return TRUE; 5249 } 5250 5251 /* OP_ADDIUSP matcher. */ 5252 5253 static bfd_boolean 5254 match_addiusp_operand (struct mips_arg_info *arg, 5255 const struct mips_operand *operand) 5256 { 5257 offsetT sval; 5258 unsigned int uval; 5259 5260 if (!match_const_int (arg, &sval)) 5261 return FALSE; 5262 5263 if (sval % 4) 5264 { 5265 match_out_of_range (arg); 5266 return FALSE; 5267 } 5268 5269 sval /= 4; 5270 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) 5271 { 5272 match_out_of_range (arg); 5273 return FALSE; 5274 } 5275 5276 uval = (unsigned int) sval; 5277 uval = ((uval >> 1) & ~0xff) | (uval & 0xff); 5278 insn_insert_operand (arg->insn, operand, uval); 5279 return TRUE; 5280 } 5281 5282 /* OP_CLO_CLZ_DEST matcher. */ 5283 5284 static bfd_boolean 5285 match_clo_clz_dest_operand (struct mips_arg_info *arg, 5286 const struct mips_operand *operand) 5287 { 5288 unsigned int regno; 5289 5290 if (!match_reg (arg, OP_REG_GP, ®no)) 5291 return FALSE; 5292 5293 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5294 return TRUE; 5295 } 5296 5297 /* OP_CHECK_PREV matcher. */ 5298 5299 static bfd_boolean 5300 match_check_prev_operand (struct mips_arg_info *arg, 5301 const struct mips_operand *operand_base) 5302 { 5303 const struct mips_check_prev_operand *operand; 5304 unsigned int regno; 5305 5306 operand = (const struct mips_check_prev_operand *) operand_base; 5307 5308 if (!match_reg (arg, OP_REG_GP, ®no)) 5309 return FALSE; 5310 5311 if (!operand->zero_ok && regno == 0) 5312 return FALSE; 5313 5314 if ((operand->less_than_ok && regno < arg->last_regno) 5315 || (operand->greater_than_ok && regno > arg->last_regno) 5316 || (operand->equal_ok && regno == arg->last_regno)) 5317 { 5318 arg->last_regno = regno; 5319 insn_insert_operand (arg->insn, operand_base, regno); 5320 return TRUE; 5321 } 5322 5323 return FALSE; 5324 } 5325 5326 /* OP_SAME_RS_RT matcher. */ 5327 5328 static bfd_boolean 5329 match_same_rs_rt_operand (struct mips_arg_info *arg, 5330 const struct mips_operand *operand) 5331 { 5332 unsigned int regno; 5333 5334 if (!match_reg (arg, OP_REG_GP, ®no)) 5335 return FALSE; 5336 5337 if (regno == 0) 5338 { 5339 set_insn_error (arg->argnum, _("the source register must not be $0")); 5340 return FALSE; 5341 } 5342 5343 arg->last_regno = regno; 5344 5345 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5346 return TRUE; 5347 } 5348 5349 /* OP_LWM_SWM_LIST matcher. */ 5350 5351 static bfd_boolean 5352 match_lwm_swm_list_operand (struct mips_arg_info *arg, 5353 const struct mips_operand *operand) 5354 { 5355 unsigned int reglist, sregs, ra, regno1, regno2; 5356 struct mips_arg_info reset; 5357 5358 reglist = 0; 5359 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5360 return FALSE; 5361 do 5362 { 5363 if (regno2 == FP && regno1 >= S0 && regno1 <= S7) 5364 { 5365 reglist |= 1 << FP; 5366 regno2 = S7; 5367 } 5368 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); 5369 reset = *arg; 5370 } 5371 while (match_char (arg, ',') 5372 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); 5373 *arg = reset; 5374 5375 if (operand->size == 2) 5376 { 5377 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: 5378 5379 s0, ra 5380 s0, s1, ra, s2, s3 5381 s0-s2, ra 5382 5383 and any permutations of these. */ 5384 if ((reglist & 0xfff1ffff) != 0x80010000) 5385 return FALSE; 5386 5387 sregs = (reglist >> 17) & 7; 5388 ra = 0; 5389 } 5390 else 5391 { 5392 /* The list must include at least one of ra and s0-sN, 5393 for 0 <= N <= 8. (Note that there is a gap between s7 and s8, 5394 which are $23 and $30 respectively.) E.g.: 5395 5396 ra 5397 s0 5398 ra, s0, s1, s2 5399 s0-s8 5400 s0-s5, ra 5401 5402 and any permutations of these. */ 5403 if ((reglist & 0x3f00ffff) != 0) 5404 return FALSE; 5405 5406 ra = (reglist >> 27) & 0x10; 5407 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); 5408 } 5409 sregs += 1; 5410 if ((sregs & -sregs) != sregs) 5411 return FALSE; 5412 5413 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); 5414 return TRUE; 5415 } 5416 5417 /* OP_ENTRY_EXIT_LIST matcher. */ 5418 5419 static unsigned int 5420 match_entry_exit_operand (struct mips_arg_info *arg, 5421 const struct mips_operand *operand) 5422 { 5423 unsigned int mask; 5424 bfd_boolean is_exit; 5425 5426 /* The format is the same for both ENTRY and EXIT, but the constraints 5427 are different. */ 5428 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; 5429 mask = (is_exit ? 7 << 3 : 0); 5430 do 5431 { 5432 unsigned int regno1, regno2; 5433 bfd_boolean is_freg; 5434 5435 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5436 is_freg = FALSE; 5437 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) 5438 is_freg = TRUE; 5439 else 5440 return FALSE; 5441 5442 if (is_exit && is_freg && regno1 == 0 && regno2 < 2) 5443 { 5444 mask &= ~(7 << 3); 5445 mask |= (5 + regno2) << 3; 5446 } 5447 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) 5448 mask |= (regno2 - 3) << 3; 5449 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) 5450 mask |= (regno2 - 15) << 1; 5451 else if (regno1 == RA && regno2 == RA) 5452 mask |= 1; 5453 else 5454 return FALSE; 5455 } 5456 while (match_char (arg, ',')); 5457 5458 insn_insert_operand (arg->insn, operand, mask); 5459 return TRUE; 5460 } 5461 5462 /* OP_SAVE_RESTORE_LIST matcher. */ 5463 5464 static bfd_boolean 5465 match_save_restore_list_operand (struct mips_arg_info *arg) 5466 { 5467 unsigned int opcode, args, statics, sregs; 5468 unsigned int num_frame_sizes, num_args, num_statics, num_sregs; 5469 offsetT frame_size; 5470 5471 opcode = arg->insn->insn_opcode; 5472 frame_size = 0; 5473 num_frame_sizes = 0; 5474 args = 0; 5475 statics = 0; 5476 sregs = 0; 5477 do 5478 { 5479 unsigned int regno1, regno2; 5480 5481 if (arg->token->type == OT_INTEGER) 5482 { 5483 /* Handle the frame size. */ 5484 if (!match_const_int (arg, &frame_size)) 5485 return FALSE; 5486 num_frame_sizes += 1; 5487 } 5488 else 5489 { 5490 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5491 return FALSE; 5492 5493 while (regno1 <= regno2) 5494 { 5495 if (regno1 >= 4 && regno1 <= 7) 5496 { 5497 if (num_frame_sizes == 0) 5498 /* args $a0-$a3 */ 5499 args |= 1 << (regno1 - 4); 5500 else 5501 /* statics $a0-$a3 */ 5502 statics |= 1 << (regno1 - 4); 5503 } 5504 else if (regno1 >= 16 && regno1 <= 23) 5505 /* $s0-$s7 */ 5506 sregs |= 1 << (regno1 - 16); 5507 else if (regno1 == 30) 5508 /* $s8 */ 5509 sregs |= 1 << 8; 5510 else if (regno1 == 31) 5511 /* Add $ra to insn. */ 5512 opcode |= 0x40; 5513 else 5514 return FALSE; 5515 regno1 += 1; 5516 if (regno1 == 24) 5517 regno1 = 30; 5518 } 5519 } 5520 } 5521 while (match_char (arg, ',')); 5522 5523 /* Encode args/statics combination. */ 5524 if (args & statics) 5525 return FALSE; 5526 else if (args == 0xf) 5527 /* All $a0-$a3 are args. */ 5528 opcode |= MIPS16_ALL_ARGS << 16; 5529 else if (statics == 0xf) 5530 /* All $a0-$a3 are statics. */ 5531 opcode |= MIPS16_ALL_STATICS << 16; 5532 else 5533 { 5534 /* Count arg registers. */ 5535 num_args = 0; 5536 while (args & 0x1) 5537 { 5538 args >>= 1; 5539 num_args += 1; 5540 } 5541 if (args != 0) 5542 return FALSE; 5543 5544 /* Count static registers. */ 5545 num_statics = 0; 5546 while (statics & 0x8) 5547 { 5548 statics = (statics << 1) & 0xf; 5549 num_statics += 1; 5550 } 5551 if (statics != 0) 5552 return FALSE; 5553 5554 /* Encode args/statics. */ 5555 opcode |= ((num_args << 2) | num_statics) << 16; 5556 } 5557 5558 /* Encode $s0/$s1. */ 5559 if (sregs & (1 << 0)) /* $s0 */ 5560 opcode |= 0x20; 5561 if (sregs & (1 << 1)) /* $s1 */ 5562 opcode |= 0x10; 5563 sregs >>= 2; 5564 5565 /* Encode $s2-$s8. */ 5566 num_sregs = 0; 5567 while (sregs & 1) 5568 { 5569 sregs >>= 1; 5570 num_sregs += 1; 5571 } 5572 if (sregs != 0) 5573 return FALSE; 5574 opcode |= num_sregs << 24; 5575 5576 /* Encode frame size. */ 5577 if (num_frame_sizes == 0) 5578 { 5579 set_insn_error (arg->argnum, _("missing frame size")); 5580 return FALSE; 5581 } 5582 if (num_frame_sizes > 1) 5583 { 5584 set_insn_error (arg->argnum, _("frame size specified twice")); 5585 return FALSE; 5586 } 5587 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) 5588 { 5589 set_insn_error (arg->argnum, _("invalid frame size")); 5590 return FALSE; 5591 } 5592 if (frame_size != 128 || (opcode >> 16) != 0) 5593 { 5594 frame_size /= 8; 5595 opcode |= (((frame_size & 0xf0) << 16) 5596 | (frame_size & 0x0f)); 5597 } 5598 5599 /* Finally build the instruction. */ 5600 if ((opcode >> 16) != 0 || frame_size == 0) 5601 opcode |= MIPS16_EXTEND; 5602 arg->insn->insn_opcode = opcode; 5603 return TRUE; 5604 } 5605 5606 /* OP_MDMX_IMM_REG matcher. */ 5607 5608 static bfd_boolean 5609 match_mdmx_imm_reg_operand (struct mips_arg_info *arg, 5610 const struct mips_operand *operand) 5611 { 5612 unsigned int regno, uval; 5613 bfd_boolean is_qh; 5614 const struct mips_opcode *opcode; 5615 5616 /* The mips_opcode records whether this is an octobyte or quadhalf 5617 instruction. Start out with that bit in place. */ 5618 opcode = arg->insn->insn_mo; 5619 uval = mips_extract_operand (operand, opcode->match); 5620 is_qh = (uval != 0); 5621 5622 if (arg->token->type == OT_REG) 5623 { 5624 if ((opcode->membership & INSN_5400) 5625 && strcmp (opcode->name, "rzu.ob") == 0) 5626 { 5627 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), 5628 arg->argnum); 5629 return FALSE; 5630 } 5631 5632 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) 5633 return FALSE; 5634 ++arg->token; 5635 5636 /* Check whether this is a vector register or a broadcast of 5637 a single element. */ 5638 if (arg->token->type == OT_INTEGER_INDEX) 5639 { 5640 if (arg->token->u.index > (is_qh ? 3 : 7)) 5641 { 5642 set_insn_error (arg->argnum, _("invalid element selector")); 5643 return FALSE; 5644 } 5645 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; 5646 ++arg->token; 5647 } 5648 else 5649 { 5650 /* A full vector. */ 5651 if ((opcode->membership & INSN_5400) 5652 && (strcmp (opcode->name, "sll.ob") == 0 5653 || strcmp (opcode->name, "srl.ob") == 0)) 5654 { 5655 set_insn_error_i (arg->argnum, _("operand %d must be scalar"), 5656 arg->argnum); 5657 return FALSE; 5658 } 5659 5660 if (is_qh) 5661 uval |= MDMX_FMTSEL_VEC_QH << 5; 5662 else 5663 uval |= MDMX_FMTSEL_VEC_OB << 5; 5664 } 5665 uval |= regno; 5666 } 5667 else 5668 { 5669 offsetT sval; 5670 5671 if (!match_const_int (arg, &sval)) 5672 return FALSE; 5673 if (sval < 0 || sval > 31) 5674 { 5675 match_out_of_range (arg); 5676 return FALSE; 5677 } 5678 uval |= (sval & 31); 5679 if (is_qh) 5680 uval |= MDMX_FMTSEL_IMM_QH << 5; 5681 else 5682 uval |= MDMX_FMTSEL_IMM_OB << 5; 5683 } 5684 insn_insert_operand (arg->insn, operand, uval); 5685 return TRUE; 5686 } 5687 5688 /* OP_IMM_INDEX matcher. */ 5689 5690 static bfd_boolean 5691 match_imm_index_operand (struct mips_arg_info *arg, 5692 const struct mips_operand *operand) 5693 { 5694 unsigned int max_val; 5695 5696 if (arg->token->type != OT_INTEGER_INDEX) 5697 return FALSE; 5698 5699 max_val = (1 << operand->size) - 1; 5700 if (arg->token->u.index > max_val) 5701 { 5702 match_out_of_range (arg); 5703 return FALSE; 5704 } 5705 insn_insert_operand (arg->insn, operand, arg->token->u.index); 5706 ++arg->token; 5707 return TRUE; 5708 } 5709 5710 /* OP_REG_INDEX matcher. */ 5711 5712 static bfd_boolean 5713 match_reg_index_operand (struct mips_arg_info *arg, 5714 const struct mips_operand *operand) 5715 { 5716 unsigned int regno; 5717 5718 if (arg->token->type != OT_REG_INDEX) 5719 return FALSE; 5720 5721 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) 5722 return FALSE; 5723 5724 insn_insert_operand (arg->insn, operand, regno); 5725 ++arg->token; 5726 return TRUE; 5727 } 5728 5729 /* OP_PC matcher. */ 5730 5731 static bfd_boolean 5732 match_pc_operand (struct mips_arg_info *arg) 5733 { 5734 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) 5735 { 5736 ++arg->token; 5737 return TRUE; 5738 } 5739 return FALSE; 5740 } 5741 5742 /* OP_NON_ZERO_REG matcher. */ 5743 5744 static bfd_boolean 5745 match_non_zero_reg_operand (struct mips_arg_info *arg, 5746 const struct mips_operand *operand) 5747 { 5748 unsigned int regno; 5749 5750 if (!match_reg (arg, OP_REG_GP, ®no)) 5751 return FALSE; 5752 5753 if (regno == 0) 5754 return FALSE; 5755 5756 arg->last_regno = regno; 5757 insn_insert_operand (arg->insn, operand, regno); 5758 return TRUE; 5759 } 5760 5761 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the 5762 register that we need to match. */ 5763 5764 static bfd_boolean 5765 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) 5766 { 5767 unsigned int regno; 5768 5769 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; 5770 } 5771 5772 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is 5773 the length of the value in bytes (4 for float, 8 for double) and 5774 USING_GPRS says whether the destination is a GPR rather than an FPR. 5775 5776 Return the constant in IMM and OFFSET as follows: 5777 5778 - If the constant should be loaded via memory, set IMM to O_absent and 5779 OFFSET to the memory address. 5780 5781 - Otherwise, if the constant should be loaded into two 32-bit registers, 5782 set IMM to the O_constant to load into the high register and OFFSET 5783 to the corresponding value for the low register. 5784 5785 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. 5786 5787 These constants only appear as the last operand in an instruction, 5788 and every instruction that accepts them in any variant accepts them 5789 in all variants. This means we don't have to worry about backing out 5790 any changes if the instruction does not match. We just match 5791 unconditionally and report an error if the constant is invalid. */ 5792 5793 static bfd_boolean 5794 match_float_constant (struct mips_arg_info *arg, expressionS *imm, 5795 expressionS *offset, int length, bfd_boolean using_gprs) 5796 { 5797 char *p; 5798 segT seg, new_seg; 5799 subsegT subseg; 5800 const char *newname; 5801 unsigned char *data; 5802 5803 /* Where the constant is placed is based on how the MIPS assembler 5804 does things: 5805 5806 length == 4 && using_gprs -- immediate value only 5807 length == 8 && using_gprs -- .rdata or immediate value 5808 length == 4 && !using_gprs -- .lit4 or immediate value 5809 length == 8 && !using_gprs -- .lit8 or immediate value 5810 5811 The .lit4 and .lit8 sections are only used if permitted by the 5812 -G argument. */ 5813 if (arg->token->type != OT_FLOAT) 5814 { 5815 set_insn_error (arg->argnum, _("floating-point expression required")); 5816 return FALSE; 5817 } 5818 5819 gas_assert (arg->token->u.flt.length == length); 5820 data = arg->token->u.flt.data; 5821 ++arg->token; 5822 5823 /* Handle 32-bit constants for which an immediate value is best. */ 5824 if (length == 4 5825 && (using_gprs 5826 || g_switch_value < 4 5827 || (data[0] == 0 && data[1] == 0) 5828 || (data[2] == 0 && data[3] == 0))) 5829 { 5830 imm->X_op = O_constant; 5831 if (!target_big_endian) 5832 imm->X_add_number = bfd_getl32 (data); 5833 else 5834 imm->X_add_number = bfd_getb32 (data); 5835 offset->X_op = O_absent; 5836 return TRUE; 5837 } 5838 5839 /* Handle 64-bit constants for which an immediate value is best. */ 5840 if (length == 8 5841 && !mips_disable_float_construction 5842 /* Constants can only be constructed in GPRs and copied to FPRs if the 5843 GPRs are at least as wide as the FPRs or MTHC1 is available. 5844 Unlike most tests for 32-bit floating-point registers this check 5845 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not 5846 permit 64-bit moves without MXHC1. 5847 Force the constant into memory otherwise. */ 5848 && (using_gprs 5849 || GPR_SIZE == 64 5850 || ISA_HAS_MXHC1 (mips_opts.isa) 5851 || FPR_SIZE == 32) 5852 && ((data[0] == 0 && data[1] == 0) 5853 || (data[2] == 0 && data[3] == 0)) 5854 && ((data[4] == 0 && data[5] == 0) 5855 || (data[6] == 0 && data[7] == 0))) 5856 { 5857 /* The value is simple enough to load with a couple of instructions. 5858 If using 32-bit registers, set IMM to the high order 32 bits and 5859 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire 5860 64 bit constant. */ 5861 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) 5862 { 5863 imm->X_op = O_constant; 5864 offset->X_op = O_constant; 5865 if (!target_big_endian) 5866 { 5867 imm->X_add_number = bfd_getl32 (data + 4); 5868 offset->X_add_number = bfd_getl32 (data); 5869 } 5870 else 5871 { 5872 imm->X_add_number = bfd_getb32 (data); 5873 offset->X_add_number = bfd_getb32 (data + 4); 5874 } 5875 if (offset->X_add_number == 0) 5876 offset->X_op = O_absent; 5877 } 5878 else 5879 { 5880 imm->X_op = O_constant; 5881 if (!target_big_endian) 5882 imm->X_add_number = bfd_getl64 (data); 5883 else 5884 imm->X_add_number = bfd_getb64 (data); 5885 offset->X_op = O_absent; 5886 } 5887 return TRUE; 5888 } 5889 5890 /* Switch to the right section. */ 5891 seg = now_seg; 5892 subseg = now_subseg; 5893 if (length == 4) 5894 { 5895 gas_assert (!using_gprs && g_switch_value >= 4); 5896 newname = ".lit4"; 5897 } 5898 else 5899 { 5900 if (using_gprs || g_switch_value < 8) 5901 newname = RDATA_SECTION_NAME; 5902 else 5903 newname = ".lit8"; 5904 } 5905 5906 new_seg = subseg_new (newname, (subsegT) 0); 5907 bfd_set_section_flags (stdoutput, new_seg, 5908 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); 5909 frag_align (length == 4 ? 2 : 3, 0, 0); 5910 if (strncmp (TARGET_OS, "elf", 3) != 0) 5911 record_alignment (new_seg, 4); 5912 else 5913 record_alignment (new_seg, length == 4 ? 2 : 3); 5914 if (seg == now_seg) 5915 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); 5916 5917 /* Set the argument to the current address in the section. */ 5918 imm->X_op = O_absent; 5919 offset->X_op = O_symbol; 5920 offset->X_add_symbol = symbol_temp_new_now (); 5921 offset->X_add_number = 0; 5922 5923 /* Put the floating point number into the section. */ 5924 p = frag_more (length); 5925 memcpy (p, data, length); 5926 5927 /* Switch back to the original section. */ 5928 subseg_set (seg, subseg); 5929 return TRUE; 5930 } 5931 5932 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between 5933 them. */ 5934 5935 static bfd_boolean 5936 match_vu0_suffix_operand (struct mips_arg_info *arg, 5937 const struct mips_operand *operand, 5938 bfd_boolean match_p) 5939 { 5940 unsigned int uval; 5941 5942 /* The operand can be an XYZW mask or a single 2-bit channel index 5943 (with X being 0). */ 5944 gas_assert (operand->size == 2 || operand->size == 4); 5945 5946 /* The suffix can be omitted when it is already part of the opcode. */ 5947 if (arg->token->type != OT_CHANNELS) 5948 return match_p; 5949 5950 uval = arg->token->u.channels; 5951 if (operand->size == 2) 5952 { 5953 /* Check that a single bit is set and convert it into a 2-bit index. */ 5954 if ((uval & -uval) != uval) 5955 return FALSE; 5956 uval = 4 - ffs (uval); 5957 } 5958 5959 if (match_p && insn_extract_operand (arg->insn, operand) != uval) 5960 return FALSE; 5961 5962 ++arg->token; 5963 if (!match_p) 5964 insn_insert_operand (arg->insn, operand, uval); 5965 return TRUE; 5966 } 5967 5968 /* S is the text seen for ARG. Match it against OPERAND. Return the end 5969 of the argument text if the match is successful, otherwise return null. */ 5970 5971 static bfd_boolean 5972 match_operand (struct mips_arg_info *arg, 5973 const struct mips_operand *operand) 5974 { 5975 switch (operand->type) 5976 { 5977 case OP_INT: 5978 return match_int_operand (arg, operand); 5979 5980 case OP_MAPPED_INT: 5981 return match_mapped_int_operand (arg, operand); 5982 5983 case OP_MSB: 5984 return match_msb_operand (arg, operand); 5985 5986 case OP_REG: 5987 case OP_OPTIONAL_REG: 5988 return match_reg_operand (arg, operand); 5989 5990 case OP_REG_PAIR: 5991 return match_reg_pair_operand (arg, operand); 5992 5993 case OP_PCREL: 5994 return match_pcrel_operand (arg); 5995 5996 case OP_PERF_REG: 5997 return match_perf_reg_operand (arg, operand); 5998 5999 case OP_ADDIUSP_INT: 6000 return match_addiusp_operand (arg, operand); 6001 6002 case OP_CLO_CLZ_DEST: 6003 return match_clo_clz_dest_operand (arg, operand); 6004 6005 case OP_LWM_SWM_LIST: 6006 return match_lwm_swm_list_operand (arg, operand); 6007 6008 case OP_ENTRY_EXIT_LIST: 6009 return match_entry_exit_operand (arg, operand); 6010 6011 case OP_SAVE_RESTORE_LIST: 6012 return match_save_restore_list_operand (arg); 6013 6014 case OP_MDMX_IMM_REG: 6015 return match_mdmx_imm_reg_operand (arg, operand); 6016 6017 case OP_REPEAT_DEST_REG: 6018 return match_tied_reg_operand (arg, arg->dest_regno); 6019 6020 case OP_REPEAT_PREV_REG: 6021 return match_tied_reg_operand (arg, arg->last_regno); 6022 6023 case OP_PC: 6024 return match_pc_operand (arg); 6025 6026 case OP_VU0_SUFFIX: 6027 return match_vu0_suffix_operand (arg, operand, FALSE); 6028 6029 case OP_VU0_MATCH_SUFFIX: 6030 return match_vu0_suffix_operand (arg, operand, TRUE); 6031 6032 case OP_IMM_INDEX: 6033 return match_imm_index_operand (arg, operand); 6034 6035 case OP_REG_INDEX: 6036 return match_reg_index_operand (arg, operand); 6037 6038 case OP_SAME_RS_RT: 6039 return match_same_rs_rt_operand (arg, operand); 6040 6041 case OP_CHECK_PREV: 6042 return match_check_prev_operand (arg, operand); 6043 6044 case OP_NON_ZERO_REG: 6045 return match_non_zero_reg_operand (arg, operand); 6046 } 6047 abort (); 6048 } 6049 6050 /* ARG is the state after successfully matching an instruction. 6051 Issue any queued-up warnings. */ 6052 6053 static void 6054 check_completed_insn (struct mips_arg_info *arg) 6055 { 6056 if (arg->seen_at) 6057 { 6058 if (AT == ATREG) 6059 as_warn (_("used $at without \".set noat\"")); 6060 else 6061 as_warn (_("used $%u with \".set at=$%u\""), AT, AT); 6062 } 6063 } 6064 6065 /* Return true if modifying general-purpose register REG needs a delay. */ 6066 6067 static bfd_boolean 6068 reg_needs_delay (unsigned int reg) 6069 { 6070 unsigned long prev_pinfo; 6071 6072 prev_pinfo = history[0].insn_mo->pinfo; 6073 if (!mips_opts.noreorder 6074 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) 6075 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) 6076 && (gpr_write_mask (&history[0]) & (1 << reg))) 6077 return TRUE; 6078 6079 return FALSE; 6080 } 6081 6082 /* Classify an instruction according to the FIX_VR4120_* enumeration. 6083 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected 6084 by VR4120 errata. */ 6085 6086 static unsigned int 6087 classify_vr4120_insn (const char *name) 6088 { 6089 if (strncmp (name, "macc", 4) == 0) 6090 return FIX_VR4120_MACC; 6091 if (strncmp (name, "dmacc", 5) == 0) 6092 return FIX_VR4120_DMACC; 6093 if (strncmp (name, "mult", 4) == 0) 6094 return FIX_VR4120_MULT; 6095 if (strncmp (name, "dmult", 5) == 0) 6096 return FIX_VR4120_DMULT; 6097 if (strstr (name, "div")) 6098 return FIX_VR4120_DIV; 6099 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) 6100 return FIX_VR4120_MTHILO; 6101 return NUM_FIX_VR4120_CLASSES; 6102 } 6103 6104 #define INSN_ERET 0x42000018 6105 #define INSN_DERET 0x4200001f 6106 #define INSN_DMULT 0x1c 6107 #define INSN_DMULTU 0x1d 6108 6109 /* Return the number of instructions that must separate INSN1 and INSN2, 6110 where INSN1 is the earlier instruction. Return the worst-case value 6111 for any INSN2 if INSN2 is null. */ 6112 6113 static unsigned int 6114 insns_between (const struct mips_cl_insn *insn1, 6115 const struct mips_cl_insn *insn2) 6116 { 6117 unsigned long pinfo1, pinfo2; 6118 unsigned int mask; 6119 6120 /* If INFO2 is null, pessimistically assume that all flags are set for 6121 the second instruction. */ 6122 pinfo1 = insn1->insn_mo->pinfo; 6123 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; 6124 6125 /* For most targets, write-after-read dependencies on the HI and LO 6126 registers must be separated by at least two instructions. */ 6127 if (!hilo_interlocks) 6128 { 6129 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) 6130 return 2; 6131 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) 6132 return 2; 6133 } 6134 6135 /* If we're working around r7000 errata, there must be two instructions 6136 between an mfhi or mflo and any instruction that uses the result. */ 6137 if (mips_7000_hilo_fix 6138 && !mips_opts.micromips 6139 && MF_HILO_INSN (pinfo1) 6140 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) 6141 return 2; 6142 6143 /* If we're working around 24K errata, one instruction is required 6144 if an ERET or DERET is followed by a branch instruction. */ 6145 if (mips_fix_24k && !mips_opts.micromips) 6146 { 6147 if (insn1->insn_opcode == INSN_ERET 6148 || insn1->insn_opcode == INSN_DERET) 6149 { 6150 if (insn2 == NULL 6151 || insn2->insn_opcode == INSN_ERET 6152 || insn2->insn_opcode == INSN_DERET 6153 || delayed_branch_p (insn2)) 6154 return 1; 6155 } 6156 } 6157 6158 /* If we're working around PMC RM7000 errata, there must be three 6159 nops between a dmult and a load instruction. */ 6160 if (mips_fix_rm7000 && !mips_opts.micromips) 6161 { 6162 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT 6163 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) 6164 { 6165 if (pinfo2 & INSN_LOAD_MEMORY) 6166 return 3; 6167 } 6168 } 6169 6170 /* If working around VR4120 errata, check for combinations that need 6171 a single intervening instruction. */ 6172 if (mips_fix_vr4120 && !mips_opts.micromips) 6173 { 6174 unsigned int class1, class2; 6175 6176 class1 = classify_vr4120_insn (insn1->insn_mo->name); 6177 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) 6178 { 6179 if (insn2 == NULL) 6180 return 1; 6181 class2 = classify_vr4120_insn (insn2->insn_mo->name); 6182 if (vr4120_conflicts[class1] & (1 << class2)) 6183 return 1; 6184 } 6185 } 6186 6187 if (!HAVE_CODE_COMPRESSION) 6188 { 6189 /* Check for GPR or coprocessor load delays. All such delays 6190 are on the RT register. */ 6191 /* Itbl support may require additional care here. */ 6192 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) 6193 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) 6194 { 6195 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) 6196 return 1; 6197 } 6198 6199 /* Check for generic coprocessor hazards. 6200 6201 This case is not handled very well. There is no special 6202 knowledge of CP0 handling, and the coprocessors other than 6203 the floating point unit are not distinguished at all. */ 6204 /* Itbl support may require additional care here. FIXME! 6205 Need to modify this to include knowledge about 6206 user specified delays! */ 6207 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) 6208 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) 6209 { 6210 /* Handle cases where INSN1 writes to a known general coprocessor 6211 register. There must be a one instruction delay before INSN2 6212 if INSN2 reads that register, otherwise no delay is needed. */ 6213 mask = fpr_write_mask (insn1); 6214 if (mask != 0) 6215 { 6216 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) 6217 return 1; 6218 } 6219 else 6220 { 6221 /* Read-after-write dependencies on the control registers 6222 require a two-instruction gap. */ 6223 if ((pinfo1 & INSN_WRITE_COND_CODE) 6224 && (pinfo2 & INSN_READ_COND_CODE)) 6225 return 2; 6226 6227 /* We don't know exactly what INSN1 does. If INSN2 is 6228 also a coprocessor instruction, assume there must be 6229 a one instruction gap. */ 6230 if (pinfo2 & INSN_COP) 6231 return 1; 6232 } 6233 } 6234 6235 /* Check for read-after-write dependencies on the coprocessor 6236 control registers in cases where INSN1 does not need a general 6237 coprocessor delay. This means that INSN1 is a floating point 6238 comparison instruction. */ 6239 /* Itbl support may require additional care here. */ 6240 else if (!cop_interlocks 6241 && (pinfo1 & INSN_WRITE_COND_CODE) 6242 && (pinfo2 & INSN_READ_COND_CODE)) 6243 return 1; 6244 } 6245 6246 /* Forbidden slots can not contain Control Transfer Instructions (CTIs) 6247 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait 6248 and pause. */ 6249 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) 6250 && ((pinfo2 & INSN_NO_DELAY_SLOT) 6251 || (insn2 && delayed_branch_p (insn2)))) 6252 return 1; 6253 6254 return 0; 6255 } 6256 6257 /* Return the number of nops that would be needed to work around the 6258 VR4130 mflo/mfhi errata if instruction INSN immediately followed 6259 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards 6260 that are contained within the first IGNORE instructions of HIST. */ 6261 6262 static int 6263 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, 6264 const struct mips_cl_insn *insn) 6265 { 6266 int i, j; 6267 unsigned int mask; 6268 6269 /* Check if the instruction writes to HI or LO. MTHI and MTLO 6270 are not affected by the errata. */ 6271 if (insn != 0 6272 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 6273 || strcmp (insn->insn_mo->name, "mtlo") == 0 6274 || strcmp (insn->insn_mo->name, "mthi") == 0)) 6275 return 0; 6276 6277 /* Search for the first MFLO or MFHI. */ 6278 for (i = 0; i < MAX_VR4130_NOPS; i++) 6279 if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) 6280 { 6281 /* Extract the destination register. */ 6282 mask = gpr_write_mask (&hist[i]); 6283 6284 /* No nops are needed if INSN reads that register. */ 6285 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) 6286 return 0; 6287 6288 /* ...or if any of the intervening instructions do. */ 6289 for (j = 0; j < i; j++) 6290 if (gpr_read_mask (&hist[j]) & mask) 6291 return 0; 6292 6293 if (i >= ignore) 6294 return MAX_VR4130_NOPS - i; 6295 } 6296 return 0; 6297 } 6298 6299 #define BASE_REG_EQ(INSN1, INSN2) \ 6300 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ 6301 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) 6302 6303 /* Return the minimum alignment for this store instruction. */ 6304 6305 static int 6306 fix_24k_align_to (const struct mips_opcode *mo) 6307 { 6308 if (strcmp (mo->name, "sh") == 0) 6309 return 2; 6310 6311 if (strcmp (mo->name, "swc1") == 0 6312 || strcmp (mo->name, "swc2") == 0 6313 || strcmp (mo->name, "sw") == 0 6314 || strcmp (mo->name, "sc") == 0 6315 || strcmp (mo->name, "s.s") == 0) 6316 return 4; 6317 6318 if (strcmp (mo->name, "sdc1") == 0 6319 || strcmp (mo->name, "sdc2") == 0 6320 || strcmp (mo->name, "s.d") == 0) 6321 return 8; 6322 6323 /* sb, swl, swr */ 6324 return 1; 6325 } 6326 6327 struct fix_24k_store_info 6328 { 6329 /* Immediate offset, if any, for this store instruction. */ 6330 short off; 6331 /* Alignment required by this store instruction. */ 6332 int align_to; 6333 /* True for register offsets. */ 6334 int register_offset; 6335 }; 6336 6337 /* Comparison function used by qsort. */ 6338 6339 static int 6340 fix_24k_sort (const void *a, const void *b) 6341 { 6342 const struct fix_24k_store_info *pos1 = a; 6343 const struct fix_24k_store_info *pos2 = b; 6344 6345 return (pos1->off - pos2->off); 6346 } 6347 6348 /* INSN is a store instruction. Try to record the store information 6349 in STINFO. Return false if the information isn't known. */ 6350 6351 static bfd_boolean 6352 fix_24k_record_store_info (struct fix_24k_store_info *stinfo, 6353 const struct mips_cl_insn *insn) 6354 { 6355 /* The instruction must have a known offset. */ 6356 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) 6357 return FALSE; 6358 6359 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; 6360 stinfo->align_to = fix_24k_align_to (insn->insn_mo); 6361 return TRUE; 6362 } 6363 6364 /* Return the number of nops that would be needed to work around the 24k 6365 "lost data on stores during refill" errata if instruction INSN 6366 immediately followed the 2 instructions described by HIST. 6367 Ignore hazards that are contained within the first IGNORE 6368 instructions of HIST. 6369 6370 Problem: The FSB (fetch store buffer) acts as an intermediate buffer 6371 for the data cache refills and store data. The following describes 6372 the scenario where the store data could be lost. 6373 6374 * A data cache miss, due to either a load or a store, causing fill 6375 data to be supplied by the memory subsystem 6376 * The first three doublewords of fill data are returned and written 6377 into the cache 6378 * A sequence of four stores occurs in consecutive cycles around the 6379 final doubleword of the fill: 6380 * Store A 6381 * Store B 6382 * Store C 6383 * Zero, One or more instructions 6384 * Store D 6385 6386 The four stores A-D must be to different doublewords of the line that 6387 is being filled. The fourth instruction in the sequence above permits 6388 the fill of the final doubleword to be transferred from the FSB into 6389 the cache. In the sequence above, the stores may be either integer 6390 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, 6391 swxc1, sdxc1, suxc1) stores, as long as the four stores are to 6392 different doublewords on the line. If the floating point unit is 6393 running in 1:2 mode, it is not possible to create the sequence above 6394 using only floating point store instructions. 6395 6396 In this case, the cache line being filled is incorrectly marked 6397 invalid, thereby losing the data from any store to the line that 6398 occurs between the original miss and the completion of the five 6399 cycle sequence shown above. 6400 6401 The workarounds are: 6402 6403 * Run the data cache in write-through mode. 6404 * Insert a non-store instruction between 6405 Store A and Store B or Store B and Store C. */ 6406 6407 static int 6408 nops_for_24k (int ignore, const struct mips_cl_insn *hist, 6409 const struct mips_cl_insn *insn) 6410 { 6411 struct fix_24k_store_info pos[3]; 6412 int align, i, base_offset; 6413 6414 if (ignore >= 2) 6415 return 0; 6416 6417 /* If the previous instruction wasn't a store, there's nothing to 6418 worry about. */ 6419 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6420 return 0; 6421 6422 /* If the instructions after the previous one are unknown, we have 6423 to assume the worst. */ 6424 if (!insn) 6425 return 1; 6426 6427 /* Check whether we are dealing with three consecutive stores. */ 6428 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 6429 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6430 return 0; 6431 6432 /* If we don't know the relationship between the store addresses, 6433 assume the worst. */ 6434 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) 6435 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) 6436 return 1; 6437 6438 if (!fix_24k_record_store_info (&pos[0], insn) 6439 || !fix_24k_record_store_info (&pos[1], &hist[0]) 6440 || !fix_24k_record_store_info (&pos[2], &hist[1])) 6441 return 1; 6442 6443 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); 6444 6445 /* Pick a value of ALIGN and X such that all offsets are adjusted by 6446 X bytes and such that the base register + X is known to be aligned 6447 to align bytes. */ 6448 6449 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) 6450 align = 8; 6451 else 6452 { 6453 align = pos[0].align_to; 6454 base_offset = pos[0].off; 6455 for (i = 1; i < 3; i++) 6456 if (align < pos[i].align_to) 6457 { 6458 align = pos[i].align_to; 6459 base_offset = pos[i].off; 6460 } 6461 for (i = 0; i < 3; i++) 6462 pos[i].off -= base_offset; 6463 } 6464 6465 pos[0].off &= ~align + 1; 6466 pos[1].off &= ~align + 1; 6467 pos[2].off &= ~align + 1; 6468 6469 /* If any two stores write to the same chunk, they also write to the 6470 same doubleword. The offsets are still sorted at this point. */ 6471 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) 6472 return 0; 6473 6474 /* A range of at least 9 bytes is needed for the stores to be in 6475 non-overlapping doublewords. */ 6476 if (pos[2].off - pos[0].off <= 8) 6477 return 0; 6478 6479 if (pos[2].off - pos[1].off >= 24 6480 || pos[1].off - pos[0].off >= 24 6481 || pos[2].off - pos[0].off >= 32) 6482 return 0; 6483 6484 return 1; 6485 } 6486 6487 /* Return the number of nops that would be needed if instruction INSN 6488 immediately followed the MAX_NOPS instructions given by HIST, 6489 where HIST[0] is the most recent instruction. Ignore hazards 6490 between INSN and the first IGNORE instructions in HIST. 6491 6492 If INSN is null, return the worse-case number of nops for any 6493 instruction. */ 6494 6495 static int 6496 nops_for_insn (int ignore, const struct mips_cl_insn *hist, 6497 const struct mips_cl_insn *insn) 6498 { 6499 int i, nops, tmp_nops; 6500 6501 nops = 0; 6502 for (i = ignore; i < MAX_DELAY_NOPS; i++) 6503 { 6504 tmp_nops = insns_between (hist + i, insn) - i; 6505 if (tmp_nops > nops) 6506 nops = tmp_nops; 6507 } 6508 6509 if (mips_fix_vr4130 && !mips_opts.micromips) 6510 { 6511 tmp_nops = nops_for_vr4130 (ignore, hist, insn); 6512 if (tmp_nops > nops) 6513 nops = tmp_nops; 6514 } 6515 6516 if (mips_fix_24k && !mips_opts.micromips) 6517 { 6518 tmp_nops = nops_for_24k (ignore, hist, insn); 6519 if (tmp_nops > nops) 6520 nops = tmp_nops; 6521 } 6522 6523 return nops; 6524 } 6525 6526 /* The variable arguments provide NUM_INSNS extra instructions that 6527 might be added to HIST. Return the largest number of nops that 6528 would be needed after the extended sequence, ignoring hazards 6529 in the first IGNORE instructions. */ 6530 6531 static int 6532 nops_for_sequence (int num_insns, int ignore, 6533 const struct mips_cl_insn *hist, ...) 6534 { 6535 va_list args; 6536 struct mips_cl_insn buffer[MAX_NOPS]; 6537 struct mips_cl_insn *cursor; 6538 int nops; 6539 6540 va_start (args, hist); 6541 cursor = buffer + num_insns; 6542 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); 6543 while (cursor > buffer) 6544 *--cursor = *va_arg (args, const struct mips_cl_insn *); 6545 6546 nops = nops_for_insn (ignore, buffer, NULL); 6547 va_end (args); 6548 return nops; 6549 } 6550 6551 /* Like nops_for_insn, but if INSN is a branch, take into account the 6552 worst-case delay for the branch target. */ 6553 6554 static int 6555 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, 6556 const struct mips_cl_insn *insn) 6557 { 6558 int nops, tmp_nops; 6559 6560 nops = nops_for_insn (ignore, hist, insn); 6561 if (delayed_branch_p (insn)) 6562 { 6563 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, 6564 hist, insn, get_delay_slot_nop (insn)); 6565 if (tmp_nops > nops) 6566 nops = tmp_nops; 6567 } 6568 else if (compact_branch_p (insn)) 6569 { 6570 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); 6571 if (tmp_nops > nops) 6572 nops = tmp_nops; 6573 } 6574 return nops; 6575 } 6576 6577 /* Fix NOP issue: Replace nops by "or at,at,zero". */ 6578 6579 static void 6580 fix_loongson2f_nop (struct mips_cl_insn * ip) 6581 { 6582 gas_assert (!HAVE_CODE_COMPRESSION); 6583 if (strcmp (ip->insn_mo->name, "nop") == 0) 6584 ip->insn_opcode = LOONGSON2F_NOP_INSN; 6585 } 6586 6587 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region 6588 jr target pc &= 'hffff_ffff_cfff_ffff. */ 6589 6590 static void 6591 fix_loongson2f_jump (struct mips_cl_insn * ip) 6592 { 6593 gas_assert (!HAVE_CODE_COMPRESSION); 6594 if (strcmp (ip->insn_mo->name, "j") == 0 6595 || strcmp (ip->insn_mo->name, "jr") == 0 6596 || strcmp (ip->insn_mo->name, "jalr") == 0) 6597 { 6598 int sreg; 6599 expressionS ep; 6600 6601 if (! mips_opts.at) 6602 return; 6603 6604 sreg = EXTRACT_OPERAND (0, RS, *ip); 6605 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) 6606 return; 6607 6608 ep.X_op = O_constant; 6609 ep.X_add_number = 0xcfff0000; 6610 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); 6611 ep.X_add_number = 0xffff; 6612 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); 6613 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); 6614 } 6615 } 6616 6617 static void 6618 fix_loongson2f (struct mips_cl_insn * ip) 6619 { 6620 if (mips_fix_loongson2f_nop) 6621 fix_loongson2f_nop (ip); 6622 6623 if (mips_fix_loongson2f_jump) 6624 fix_loongson2f_jump (ip); 6625 } 6626 6627 /* IP is a branch that has a delay slot, and we need to fill it 6628 automatically. Return true if we can do that by swapping IP 6629 with the previous instruction. 6630 ADDRESS_EXPR is an operand of the instruction to be used with 6631 RELOC_TYPE. */ 6632 6633 static bfd_boolean 6634 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, 6635 bfd_reloc_code_real_type *reloc_type) 6636 { 6637 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; 6638 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; 6639 unsigned int fpr_read, prev_fpr_write; 6640 6641 /* -O2 and above is required for this optimization. */ 6642 if (mips_optimize < 2) 6643 return FALSE; 6644 6645 /* If we have seen .set volatile or .set nomove, don't optimize. */ 6646 if (mips_opts.nomove) 6647 return FALSE; 6648 6649 /* We can't swap if the previous instruction's position is fixed. */ 6650 if (history[0].fixed_p) 6651 return FALSE; 6652 6653 /* If the previous previous insn was in a .set noreorder, we can't 6654 swap. Actually, the MIPS assembler will swap in this situation. 6655 However, gcc configured -with-gnu-as will generate code like 6656 6657 .set noreorder 6658 lw $4,XXX 6659 .set reorder 6660 INSN 6661 bne $4,$0,foo 6662 6663 in which we can not swap the bne and INSN. If gcc is not configured 6664 -with-gnu-as, it does not output the .set pseudo-ops. */ 6665 if (history[1].noreorder_p) 6666 return FALSE; 6667 6668 /* If the previous instruction had a fixup in mips16 mode, we can not swap. 6669 This means that the previous instruction was a 4-byte one anyhow. */ 6670 if (mips_opts.mips16 && history[0].fixp[0]) 6671 return FALSE; 6672 6673 /* If the branch is itself the target of a branch, we can not swap. 6674 We cheat on this; all we check for is whether there is a label on 6675 this instruction. If there are any branches to anything other than 6676 a label, users must use .set noreorder. */ 6677 if (seg_info (now_seg)->label_list) 6678 return FALSE; 6679 6680 /* If the previous instruction is in a variant frag other than this 6681 branch's one, we cannot do the swap. This does not apply to 6682 MIPS16 code, which uses variant frags for different purposes. */ 6683 if (!mips_opts.mips16 6684 && history[0].frag 6685 && history[0].frag->fr_type == rs_machine_dependent) 6686 return FALSE; 6687 6688 /* We do not swap with instructions that cannot architecturally 6689 be placed in a branch delay slot, such as SYNC or ERET. We 6690 also refrain from swapping with a trap instruction, since it 6691 complicates trap handlers to have the trap instruction be in 6692 a delay slot. */ 6693 prev_pinfo = history[0].insn_mo->pinfo; 6694 if (prev_pinfo & INSN_NO_DELAY_SLOT) 6695 return FALSE; 6696 6697 /* Check for conflicts between the branch and the instructions 6698 before the candidate delay slot. */ 6699 if (nops_for_insn (0, history + 1, ip) > 0) 6700 return FALSE; 6701 6702 /* Check for conflicts between the swapped sequence and the 6703 target of the branch. */ 6704 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) 6705 return FALSE; 6706 6707 /* If the branch reads a register that the previous 6708 instruction sets, we can not swap. */ 6709 gpr_read = gpr_read_mask (ip); 6710 prev_gpr_write = gpr_write_mask (&history[0]); 6711 if (gpr_read & prev_gpr_write) 6712 return FALSE; 6713 6714 fpr_read = fpr_read_mask (ip); 6715 prev_fpr_write = fpr_write_mask (&history[0]); 6716 if (fpr_read & prev_fpr_write) 6717 return FALSE; 6718 6719 /* If the branch writes a register that the previous 6720 instruction sets, we can not swap. */ 6721 gpr_write = gpr_write_mask (ip); 6722 if (gpr_write & prev_gpr_write) 6723 return FALSE; 6724 6725 /* If the branch writes a register that the previous 6726 instruction reads, we can not swap. */ 6727 prev_gpr_read = gpr_read_mask (&history[0]); 6728 if (gpr_write & prev_gpr_read) 6729 return FALSE; 6730 6731 /* If one instruction sets a condition code and the 6732 other one uses a condition code, we can not swap. */ 6733 pinfo = ip->insn_mo->pinfo; 6734 if ((pinfo & INSN_READ_COND_CODE) 6735 && (prev_pinfo & INSN_WRITE_COND_CODE)) 6736 return FALSE; 6737 if ((pinfo & INSN_WRITE_COND_CODE) 6738 && (prev_pinfo & INSN_READ_COND_CODE)) 6739 return FALSE; 6740 6741 /* If the previous instruction uses the PC, we can not swap. */ 6742 prev_pinfo2 = history[0].insn_mo->pinfo2; 6743 if (prev_pinfo2 & INSN2_READ_PC) 6744 return FALSE; 6745 6746 /* If the previous instruction has an incorrect size for a fixed 6747 branch delay slot in microMIPS mode, we cannot swap. */ 6748 pinfo2 = ip->insn_mo->pinfo2; 6749 if (mips_opts.micromips 6750 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) 6751 && insn_length (history) != 2) 6752 return FALSE; 6753 if (mips_opts.micromips 6754 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) 6755 && insn_length (history) != 4) 6756 return FALSE; 6757 6758 /* On R5900 short loops need to be fixed by inserting a nop in 6759 the branch delay slots. 6760 A short loop can be terminated too early. */ 6761 if (mips_opts.arch == CPU_R5900 6762 /* Check if instruction has a parameter, ignore "j $31". */ 6763 && (address_expr != NULL) 6764 /* Parameter must be 16 bit. */ 6765 && (*reloc_type == BFD_RELOC_16_PCREL_S2) 6766 /* Branch to same segment. */ 6767 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) 6768 /* Branch to same code fragment. */ 6769 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) 6770 /* Can only calculate branch offset if value is known. */ 6771 && symbol_constant_p (address_expr->X_add_symbol) 6772 /* Check if branch is really conditional. */ 6773 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 6774 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ 6775 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 6776 { 6777 int distance; 6778 /* Check if loop is shorter than 6 instructions including 6779 branch and delay slot. */ 6780 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); 6781 if (distance <= 20) 6782 { 6783 int i; 6784 int rv; 6785 6786 rv = FALSE; 6787 /* When the loop includes branches or jumps, 6788 it is not a short loop. */ 6789 for (i = 0; i < (distance / 4); i++) 6790 { 6791 if ((history[i].cleared_p) 6792 || delayed_branch_p (&history[i])) 6793 { 6794 rv = TRUE; 6795 break; 6796 } 6797 } 6798 if (rv == FALSE) 6799 { 6800 /* Insert nop after branch to fix short loop. */ 6801 return FALSE; 6802 } 6803 } 6804 } 6805 6806 return TRUE; 6807 } 6808 6809 /* Decide how we should add IP to the instruction stream. 6810 ADDRESS_EXPR is an operand of the instruction to be used with 6811 RELOC_TYPE. */ 6812 6813 static enum append_method 6814 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, 6815 bfd_reloc_code_real_type *reloc_type) 6816 { 6817 /* The relaxed version of a macro sequence must be inherently 6818 hazard-free. */ 6819 if (mips_relax.sequence == 2) 6820 return APPEND_ADD; 6821 6822 /* We must not dabble with instructions in a ".set noreorder" block. */ 6823 if (mips_opts.noreorder) 6824 return APPEND_ADD; 6825 6826 /* Otherwise, it's our responsibility to fill branch delay slots. */ 6827 if (delayed_branch_p (ip)) 6828 { 6829 if (!branch_likely_p (ip) 6830 && can_swap_branch_p (ip, address_expr, reloc_type)) 6831 return APPEND_SWAP; 6832 6833 if (mips_opts.mips16 6834 && ISA_SUPPORTS_MIPS16E 6835 && gpr_read_mask (ip) != 0) 6836 return APPEND_ADD_COMPACT; 6837 6838 return APPEND_ADD_WITH_NOP; 6839 } 6840 6841 return APPEND_ADD; 6842 } 6843 6844 /* IP is a MIPS16 instruction whose opcode we have just changed. 6845 Point IP->insn_mo to the new opcode's definition. */ 6846 6847 static void 6848 find_altered_mips16_opcode (struct mips_cl_insn *ip) 6849 { 6850 const struct mips_opcode *mo, *end; 6851 6852 end = &mips16_opcodes[bfd_mips16_num_opcodes]; 6853 for (mo = ip->insn_mo; mo < end; mo++) 6854 if ((ip->insn_opcode & mo->mask) == mo->match) 6855 { 6856 ip->insn_mo = mo; 6857 return; 6858 } 6859 abort (); 6860 } 6861 6862 /* For microMIPS macros, we need to generate a local number label 6863 as the target of branches. */ 6864 #define MICROMIPS_LABEL_CHAR '\037' 6865 static unsigned long micromips_target_label; 6866 static char micromips_target_name[32]; 6867 6868 static char * 6869 micromips_label_name (void) 6870 { 6871 char *p = micromips_target_name; 6872 char symbol_name_temporary[24]; 6873 unsigned long l; 6874 int i; 6875 6876 if (*p) 6877 return p; 6878 6879 i = 0; 6880 l = micromips_target_label; 6881 #ifdef LOCAL_LABEL_PREFIX 6882 *p++ = LOCAL_LABEL_PREFIX; 6883 #endif 6884 *p++ = 'L'; 6885 *p++ = MICROMIPS_LABEL_CHAR; 6886 do 6887 { 6888 symbol_name_temporary[i++] = l % 10 + '0'; 6889 l /= 10; 6890 } 6891 while (l != 0); 6892 while (i > 0) 6893 *p++ = symbol_name_temporary[--i]; 6894 *p = '\0'; 6895 6896 return micromips_target_name; 6897 } 6898 6899 static void 6900 micromips_label_expr (expressionS *label_expr) 6901 { 6902 label_expr->X_op = O_symbol; 6903 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); 6904 label_expr->X_add_number = 0; 6905 } 6906 6907 static void 6908 micromips_label_inc (void) 6909 { 6910 micromips_target_label++; 6911 *micromips_target_name = '\0'; 6912 } 6913 6914 static void 6915 micromips_add_label (void) 6916 { 6917 symbolS *s; 6918 6919 s = colon (micromips_label_name ()); 6920 micromips_label_inc (); 6921 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); 6922 } 6923 6924 /* If assembling microMIPS code, then return the microMIPS reloc 6925 corresponding to the requested one if any. Otherwise return 6926 the reloc unchanged. */ 6927 6928 static bfd_reloc_code_real_type 6929 micromips_map_reloc (bfd_reloc_code_real_type reloc) 6930 { 6931 static const bfd_reloc_code_real_type relocs[][2] = 6932 { 6933 /* Keep sorted incrementally by the left-hand key. */ 6934 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, 6935 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, 6936 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, 6937 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, 6938 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, 6939 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, 6940 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, 6941 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, 6942 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, 6943 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, 6944 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, 6945 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, 6946 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, 6947 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, 6948 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, 6949 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, 6950 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, 6951 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, 6952 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, 6953 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, 6954 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, 6955 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, 6956 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, 6957 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, 6958 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, 6959 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, 6960 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } 6961 }; 6962 bfd_reloc_code_real_type r; 6963 size_t i; 6964 6965 if (!mips_opts.micromips) 6966 return reloc; 6967 for (i = 0; i < ARRAY_SIZE (relocs); i++) 6968 { 6969 r = relocs[i][0]; 6970 if (r > reloc) 6971 return reloc; 6972 if (r == reloc) 6973 return relocs[i][1]; 6974 } 6975 return reloc; 6976 } 6977 6978 /* Try to resolve relocation RELOC against constant OPERAND at assembly time. 6979 Return true on success, storing the resolved value in RESULT. */ 6980 6981 static bfd_boolean 6982 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, 6983 offsetT *result) 6984 { 6985 switch (reloc) 6986 { 6987 case BFD_RELOC_MIPS_HIGHEST: 6988 case BFD_RELOC_MICROMIPS_HIGHEST: 6989 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; 6990 return TRUE; 6991 6992 case BFD_RELOC_MIPS_HIGHER: 6993 case BFD_RELOC_MICROMIPS_HIGHER: 6994 *result = ((operand + 0x80008000ull) >> 32) & 0xffff; 6995 return TRUE; 6996 6997 case BFD_RELOC_HI16_S: 6998 case BFD_RELOC_HI16_S_PCREL: 6999 case BFD_RELOC_MICROMIPS_HI16_S: 7000 case BFD_RELOC_MIPS16_HI16_S: 7001 *result = ((operand + 0x8000) >> 16) & 0xffff; 7002 return TRUE; 7003 7004 case BFD_RELOC_HI16: 7005 case BFD_RELOC_MICROMIPS_HI16: 7006 case BFD_RELOC_MIPS16_HI16: 7007 *result = (operand >> 16) & 0xffff; 7008 return TRUE; 7009 7010 case BFD_RELOC_LO16: 7011 case BFD_RELOC_LO16_PCREL: 7012 case BFD_RELOC_MICROMIPS_LO16: 7013 case BFD_RELOC_MIPS16_LO16: 7014 *result = operand & 0xffff; 7015 return TRUE; 7016 7017 case BFD_RELOC_UNUSED: 7018 *result = operand; 7019 return TRUE; 7020 7021 default: 7022 return FALSE; 7023 } 7024 } 7025 7026 /* Output an instruction. IP is the instruction information. 7027 ADDRESS_EXPR is an operand of the instruction to be used with 7028 RELOC_TYPE. EXPANSIONP is true if the instruction is part of 7029 a macro expansion. */ 7030 7031 static void 7032 append_insn (struct mips_cl_insn *ip, expressionS *address_expr, 7033 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) 7034 { 7035 unsigned long prev_pinfo2, pinfo; 7036 bfd_boolean relaxed_branch = FALSE; 7037 enum append_method method; 7038 bfd_boolean relax32; 7039 int branch_disp; 7040 7041 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) 7042 fix_loongson2f (ip); 7043 7044 file_ase_mips16 |= mips_opts.mips16; 7045 file_ase_micromips |= mips_opts.micromips; 7046 7047 prev_pinfo2 = history[0].insn_mo->pinfo2; 7048 pinfo = ip->insn_mo->pinfo; 7049 7050 if (mips_opts.micromips 7051 && !expansionp 7052 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 7053 && micromips_insn_length (ip->insn_mo) != 2) 7054 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 7055 && micromips_insn_length (ip->insn_mo) != 4))) 7056 as_warn (_("wrong size instruction in a %u-bit branch delay slot"), 7057 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); 7058 7059 if (address_expr == NULL) 7060 ip->complete_p = 1; 7061 else if (reloc_type[0] <= BFD_RELOC_UNUSED 7062 && reloc_type[1] == BFD_RELOC_UNUSED 7063 && reloc_type[2] == BFD_RELOC_UNUSED 7064 && address_expr->X_op == O_constant) 7065 { 7066 switch (*reloc_type) 7067 { 7068 case BFD_RELOC_MIPS_JMP: 7069 { 7070 int shift; 7071 7072 /* Shift is 2, unusually, for microMIPS JALX. */ 7073 shift = (mips_opts.micromips 7074 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; 7075 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7076 as_bad (_("jump to misaligned address (0x%lx)"), 7077 (unsigned long) address_expr->X_add_number); 7078 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7079 & 0x3ffffff); 7080 ip->complete_p = 1; 7081 } 7082 break; 7083 7084 case BFD_RELOC_MIPS16_JMP: 7085 if ((address_expr->X_add_number & 3) != 0) 7086 as_bad (_("jump to misaligned address (0x%lx)"), 7087 (unsigned long) address_expr->X_add_number); 7088 ip->insn_opcode |= 7089 (((address_expr->X_add_number & 0x7c0000) << 3) 7090 | ((address_expr->X_add_number & 0xf800000) >> 7) 7091 | ((address_expr->X_add_number & 0x3fffc) >> 2)); 7092 ip->complete_p = 1; 7093 break; 7094 7095 case BFD_RELOC_16_PCREL_S2: 7096 { 7097 int shift; 7098 7099 shift = mips_opts.micromips ? 1 : 2; 7100 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7101 as_bad (_("branch to misaligned address (0x%lx)"), 7102 (unsigned long) address_expr->X_add_number); 7103 if (!mips_relax_branch) 7104 { 7105 if ((address_expr->X_add_number + (1 << (shift + 15))) 7106 & ~((1 << (shift + 16)) - 1)) 7107 as_bad (_("branch address range overflow (0x%lx)"), 7108 (unsigned long) address_expr->X_add_number); 7109 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7110 & 0xffff); 7111 } 7112 } 7113 break; 7114 7115 case BFD_RELOC_MIPS_21_PCREL_S2: 7116 { 7117 int shift; 7118 7119 shift = 2; 7120 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7121 as_bad (_("branch to misaligned address (0x%lx)"), 7122 (unsigned long) address_expr->X_add_number); 7123 if ((address_expr->X_add_number + (1 << (shift + 20))) 7124 & ~((1 << (shift + 21)) - 1)) 7125 as_bad (_("branch address range overflow (0x%lx)"), 7126 (unsigned long) address_expr->X_add_number); 7127 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7128 & 0x1fffff); 7129 } 7130 break; 7131 7132 case BFD_RELOC_MIPS_26_PCREL_S2: 7133 { 7134 int shift; 7135 7136 shift = 2; 7137 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7138 as_bad (_("branch to misaligned address (0x%lx)"), 7139 (unsigned long) address_expr->X_add_number); 7140 if ((address_expr->X_add_number + (1 << (shift + 25))) 7141 & ~((1 << (shift + 26)) - 1)) 7142 as_bad (_("branch address range overflow (0x%lx)"), 7143 (unsigned long) address_expr->X_add_number); 7144 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7145 & 0x3ffffff); 7146 } 7147 break; 7148 7149 default: 7150 { 7151 offsetT value; 7152 7153 if (calculate_reloc (*reloc_type, address_expr->X_add_number, 7154 &value)) 7155 { 7156 ip->insn_opcode |= value & 0xffff; 7157 ip->complete_p = 1; 7158 } 7159 } 7160 break; 7161 } 7162 } 7163 7164 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 7165 { 7166 /* There are a lot of optimizations we could do that we don't. 7167 In particular, we do not, in general, reorder instructions. 7168 If you use gcc with optimization, it will reorder 7169 instructions and generally do much more optimization then we 7170 do here; repeating all that work in the assembler would only 7171 benefit hand written assembly code, and does not seem worth 7172 it. */ 7173 int nops = (mips_optimize == 0 7174 ? nops_for_insn (0, history, NULL) 7175 : nops_for_insn_or_target (0, history, ip)); 7176 if (nops > 0) 7177 { 7178 fragS *old_frag; 7179 unsigned long old_frag_offset; 7180 int i; 7181 7182 old_frag = frag_now; 7183 old_frag_offset = frag_now_fix (); 7184 7185 for (i = 0; i < nops; i++) 7186 add_fixed_insn (NOP_INSN); 7187 insert_into_history (0, nops, NOP_INSN); 7188 7189 if (listing) 7190 { 7191 listing_prev_line (); 7192 /* We may be at the start of a variant frag. In case we 7193 are, make sure there is enough space for the frag 7194 after the frags created by listing_prev_line. The 7195 argument to frag_grow here must be at least as large 7196 as the argument to all other calls to frag_grow in 7197 this file. We don't have to worry about being in the 7198 middle of a variant frag, because the variants insert 7199 all needed nop instructions themselves. */ 7200 frag_grow (40); 7201 } 7202 7203 mips_move_text_labels (); 7204 7205 #ifndef NO_ECOFF_DEBUGGING 7206 if (ECOFF_DEBUGGING) 7207 ecoff_fix_loc (old_frag, old_frag_offset); 7208 #endif 7209 } 7210 } 7211 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) 7212 { 7213 int nops; 7214 7215 /* Work out how many nops in prev_nop_frag are needed by IP, 7216 ignoring hazards generated by the first prev_nop_frag_since 7217 instructions. */ 7218 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); 7219 gas_assert (nops <= prev_nop_frag_holds); 7220 7221 /* Enforce NOPS as a minimum. */ 7222 if (nops > prev_nop_frag_required) 7223 prev_nop_frag_required = nops; 7224 7225 if (prev_nop_frag_holds == prev_nop_frag_required) 7226 { 7227 /* Settle for the current number of nops. Update the history 7228 accordingly (for the benefit of any future .set reorder code). */ 7229 prev_nop_frag = NULL; 7230 insert_into_history (prev_nop_frag_since, 7231 prev_nop_frag_holds, NOP_INSN); 7232 } 7233 else 7234 { 7235 /* Allow this instruction to replace one of the nops that was 7236 tentatively added to prev_nop_frag. */ 7237 prev_nop_frag->fr_fix -= NOP_INSN_SIZE; 7238 prev_nop_frag_holds--; 7239 prev_nop_frag_since++; 7240 } 7241 } 7242 7243 method = get_append_method (ip, address_expr, reloc_type); 7244 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; 7245 7246 dwarf2_emit_insn (0); 7247 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, 7248 so "move" the instruction address accordingly. 7249 7250 Also, it doesn't seem appropriate for the assembler to reorder .loc 7251 entries. If this instruction is a branch that we are going to swap 7252 with the previous instruction, the two instructions should be 7253 treated as a unit, and the debug information for both instructions 7254 should refer to the start of the branch sequence. Using the 7255 current position is certainly wrong when swapping a 32-bit branch 7256 and a 16-bit delay slot, since the current position would then be 7257 in the middle of a branch. */ 7258 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); 7259 7260 relax32 = (mips_relax_branch 7261 /* Don't try branch relaxation within .set nomacro, or within 7262 .set noat if we use $at for PIC computations. If it turns 7263 out that the branch was out-of-range, we'll get an error. */ 7264 && !mips_opts.warn_about_macros 7265 && (mips_opts.at || mips_pic == NO_PIC) 7266 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F 7267 as they have no complementing branches. */ 7268 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); 7269 7270 if (!HAVE_CODE_COMPRESSION 7271 && address_expr 7272 && relax32 7273 && *reloc_type == BFD_RELOC_16_PCREL_S2 7274 && delayed_branch_p (ip)) 7275 { 7276 relaxed_branch = TRUE; 7277 add_relaxed_insn (ip, (relaxed_branch_length 7278 (NULL, NULL, 7279 uncond_branch_p (ip) ? -1 7280 : branch_likely_p (ip) ? 1 7281 : 0)), 4, 7282 RELAX_BRANCH_ENCODE 7283 (AT, 7284 uncond_branch_p (ip), 7285 branch_likely_p (ip), 7286 pinfo & INSN_WRITE_GPR_31, 7287 0), 7288 address_expr->X_add_symbol, 7289 address_expr->X_add_number); 7290 *reloc_type = BFD_RELOC_UNUSED; 7291 } 7292 else if (mips_opts.micromips 7293 && address_expr 7294 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) 7295 || *reloc_type > BFD_RELOC_UNUSED) 7296 && (delayed_branch_p (ip) || compact_branch_p (ip)) 7297 /* Don't try branch relaxation when users specify 7298 16-bit/32-bit instructions. */ 7299 && !forced_insn_length) 7300 { 7301 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; 7302 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; 7303 int uncond = uncond_branch_p (ip) ? -1 : 0; 7304 int compact = compact_branch_p (ip); 7305 int al = pinfo & INSN_WRITE_GPR_31; 7306 int length32; 7307 7308 gas_assert (address_expr != NULL); 7309 gas_assert (!mips_relax.sequence); 7310 7311 relaxed_branch = TRUE; 7312 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); 7313 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, 7314 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, 7315 relax32, 0, 0), 7316 address_expr->X_add_symbol, 7317 address_expr->X_add_number); 7318 *reloc_type = BFD_RELOC_UNUSED; 7319 } 7320 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) 7321 { 7322 symbolS *symbol; 7323 offsetT offset; 7324 7325 /* We need to set up a variant frag. */ 7326 gas_assert (address_expr != NULL); 7327 /* Pass any `O_symbol' expression unchanged as an `expr_section' 7328 symbol created by `make_expr_symbol' may not get a necessary 7329 external relocation produced. */ 7330 if (address_expr->X_op == O_symbol) 7331 { 7332 symbol = address_expr->X_add_symbol; 7333 offset = address_expr->X_add_number; 7334 } 7335 else 7336 { 7337 symbol = make_expr_symbol (address_expr); 7338 offset = 0; 7339 } 7340 add_relaxed_insn (ip, 4, 0, 7341 RELAX_MIPS16_ENCODE 7342 (*reloc_type - BFD_RELOC_UNUSED, 7343 forced_insn_length == 2, forced_insn_length == 4, 7344 delayed_branch_p (&history[0]), 7345 history[0].mips16_absolute_jump_p), 7346 symbol, offset); 7347 } 7348 else if (mips_opts.mips16 && insn_length (ip) == 2) 7349 { 7350 if (!delayed_branch_p (ip)) 7351 /* Make sure there is enough room to swap this instruction with 7352 a following jump instruction. */ 7353 frag_grow (6); 7354 add_fixed_insn (ip); 7355 } 7356 else 7357 { 7358 if (mips_opts.mips16 7359 && mips_opts.noreorder 7360 && delayed_branch_p (&history[0])) 7361 as_warn (_("extended instruction in delay slot")); 7362 7363 if (mips_relax.sequence) 7364 { 7365 /* If we've reached the end of this frag, turn it into a variant 7366 frag and record the information for the instructions we've 7367 written so far. */ 7368 if (frag_room () < 4) 7369 relax_close_frag (); 7370 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); 7371 } 7372 7373 if (mips_relax.sequence != 2) 7374 { 7375 if (mips_macro_warning.first_insn_sizes[0] == 0) 7376 mips_macro_warning.first_insn_sizes[0] = insn_length (ip); 7377 mips_macro_warning.sizes[0] += insn_length (ip); 7378 mips_macro_warning.insns[0]++; 7379 } 7380 if (mips_relax.sequence != 1) 7381 { 7382 if (mips_macro_warning.first_insn_sizes[1] == 0) 7383 mips_macro_warning.first_insn_sizes[1] = insn_length (ip); 7384 mips_macro_warning.sizes[1] += insn_length (ip); 7385 mips_macro_warning.insns[1]++; 7386 } 7387 7388 if (mips_opts.mips16) 7389 { 7390 ip->fixed_p = 1; 7391 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); 7392 } 7393 add_fixed_insn (ip); 7394 } 7395 7396 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) 7397 { 7398 bfd_reloc_code_real_type final_type[3]; 7399 reloc_howto_type *howto0; 7400 reloc_howto_type *howto; 7401 int i; 7402 7403 /* Perform any necessary conversion to microMIPS relocations 7404 and find out how many relocations there actually are. */ 7405 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) 7406 final_type[i] = micromips_map_reloc (reloc_type[i]); 7407 7408 /* In a compound relocation, it is the final (outermost) 7409 operator that determines the relocated field. */ 7410 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); 7411 if (!howto) 7412 abort (); 7413 7414 if (i > 1) 7415 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); 7416 ip->fixp[0] = fix_new_exp (ip->frag, ip->where, 7417 bfd_get_reloc_size (howto), 7418 address_expr, 7419 howto0 && howto0->pc_relative, 7420 final_type[0]); 7421 7422 /* Tag symbols that have a R_MIPS16_26 relocation against them. */ 7423 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) 7424 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; 7425 7426 /* These relocations can have an addend that won't fit in 7427 4 octets for 64bit assembly. */ 7428 if (GPR_SIZE == 64 7429 && ! howto->partial_inplace 7430 && (reloc_type[0] == BFD_RELOC_16 7431 || reloc_type[0] == BFD_RELOC_32 7432 || reloc_type[0] == BFD_RELOC_MIPS_JMP 7433 || reloc_type[0] == BFD_RELOC_GPREL16 7434 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL 7435 || reloc_type[0] == BFD_RELOC_GPREL32 7436 || reloc_type[0] == BFD_RELOC_64 7437 || reloc_type[0] == BFD_RELOC_CTOR 7438 || reloc_type[0] == BFD_RELOC_MIPS_SUB 7439 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST 7440 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER 7441 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP 7442 || reloc_type[0] == BFD_RELOC_MIPS_REL16 7443 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT 7444 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL 7445 || hi16_reloc_p (reloc_type[0]) 7446 || lo16_reloc_p (reloc_type[0]))) 7447 ip->fixp[0]->fx_no_overflow = 1; 7448 7449 /* These relocations can have an addend that won't fit in 2 octets. */ 7450 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 7451 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) 7452 ip->fixp[0]->fx_no_overflow = 1; 7453 7454 if (mips_relax.sequence) 7455 { 7456 if (mips_relax.first_fixup == 0) 7457 mips_relax.first_fixup = ip->fixp[0]; 7458 } 7459 else if (reloc_needs_lo_p (*reloc_type)) 7460 { 7461 struct mips_hi_fixup *hi_fixup; 7462 7463 /* Reuse the last entry if it already has a matching %lo. */ 7464 hi_fixup = mips_hi_fixup_list; 7465 if (hi_fixup == 0 7466 || !fixup_has_matching_lo_p (hi_fixup->fixp)) 7467 { 7468 hi_fixup = XNEW (struct mips_hi_fixup); 7469 hi_fixup->next = mips_hi_fixup_list; 7470 mips_hi_fixup_list = hi_fixup; 7471 } 7472 hi_fixup->fixp = ip->fixp[0]; 7473 hi_fixup->seg = now_seg; 7474 } 7475 7476 /* Add fixups for the second and third relocations, if given. 7477 Note that the ABI allows the second relocation to be 7478 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the 7479 moment we only use RSS_UNDEF, but we could add support 7480 for the others if it ever becomes necessary. */ 7481 for (i = 1; i < 3; i++) 7482 if (reloc_type[i] != BFD_RELOC_UNUSED) 7483 { 7484 ip->fixp[i] = fix_new (ip->frag, ip->where, 7485 ip->fixp[0]->fx_size, NULL, 0, 7486 FALSE, final_type[i]); 7487 7488 /* Use fx_tcbit to mark compound relocs. */ 7489 ip->fixp[0]->fx_tcbit = 1; 7490 ip->fixp[i]->fx_tcbit = 1; 7491 } 7492 } 7493 install_insn (ip); 7494 7495 /* Update the register mask information. */ 7496 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); 7497 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); 7498 7499 switch (method) 7500 { 7501 case APPEND_ADD: 7502 insert_into_history (0, 1, ip); 7503 break; 7504 7505 case APPEND_ADD_WITH_NOP: 7506 { 7507 struct mips_cl_insn *nop; 7508 7509 insert_into_history (0, 1, ip); 7510 nop = get_delay_slot_nop (ip); 7511 add_fixed_insn (nop); 7512 insert_into_history (0, 1, nop); 7513 if (mips_relax.sequence) 7514 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); 7515 } 7516 break; 7517 7518 case APPEND_ADD_COMPACT: 7519 /* Convert MIPS16 jr/jalr into a "compact" jump. */ 7520 gas_assert (mips_opts.mips16); 7521 ip->insn_opcode |= 0x0080; 7522 find_altered_mips16_opcode (ip); 7523 install_insn (ip); 7524 insert_into_history (0, 1, ip); 7525 break; 7526 7527 case APPEND_SWAP: 7528 { 7529 struct mips_cl_insn delay = history[0]; 7530 7531 if (relaxed_branch || delay.frag != ip->frag) 7532 { 7533 /* Add the delay slot instruction to the end of the 7534 current frag and shrink the fixed part of the 7535 original frag. If the branch occupies the tail of 7536 the latter, move it backwards to cover the gap. */ 7537 delay.frag->fr_fix -= branch_disp; 7538 if (delay.frag == ip->frag) 7539 move_insn (ip, ip->frag, ip->where - branch_disp); 7540 add_fixed_insn (&delay); 7541 } 7542 else 7543 { 7544 /* If this is not a relaxed branch and we are in the 7545 same frag, then just swap the instructions. */ 7546 move_insn (ip, delay.frag, delay.where); 7547 move_insn (&delay, ip->frag, ip->where + insn_length (ip)); 7548 } 7549 history[0] = *ip; 7550 delay.fixed_p = 1; 7551 insert_into_history (0, 1, &delay); 7552 } 7553 break; 7554 } 7555 7556 /* If we have just completed an unconditional branch, clear the history. */ 7557 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) 7558 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) 7559 { 7560 unsigned int i; 7561 7562 mips_no_prev_insn (); 7563 7564 for (i = 0; i < ARRAY_SIZE (history); i++) 7565 history[i].cleared_p = 1; 7566 } 7567 7568 /* We need to emit a label at the end of branch-likely macros. */ 7569 if (emit_branch_likely_macro) 7570 { 7571 emit_branch_likely_macro = FALSE; 7572 micromips_add_label (); 7573 } 7574 7575 /* We just output an insn, so the next one doesn't have a label. */ 7576 mips_clear_insn_labels (); 7577 } 7578 7579 /* Forget that there was any previous instruction or label. 7580 When BRANCH is true, the branch history is also flushed. */ 7581 7582 static void 7583 mips_no_prev_insn (void) 7584 { 7585 prev_nop_frag = NULL; 7586 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); 7587 mips_clear_insn_labels (); 7588 } 7589 7590 /* This function must be called before we emit something other than 7591 instructions. It is like mips_no_prev_insn except that it inserts 7592 any NOPS that might be needed by previous instructions. */ 7593 7594 void 7595 mips_emit_delays (void) 7596 { 7597 if (! mips_opts.noreorder) 7598 { 7599 int nops = nops_for_insn (0, history, NULL); 7600 if (nops > 0) 7601 { 7602 while (nops-- > 0) 7603 add_fixed_insn (NOP_INSN); 7604 mips_move_text_labels (); 7605 } 7606 } 7607 mips_no_prev_insn (); 7608 } 7609 7610 /* Start a (possibly nested) noreorder block. */ 7611 7612 static void 7613 start_noreorder (void) 7614 { 7615 if (mips_opts.noreorder == 0) 7616 { 7617 unsigned int i; 7618 int nops; 7619 7620 /* None of the instructions before the .set noreorder can be moved. */ 7621 for (i = 0; i < ARRAY_SIZE (history); i++) 7622 history[i].fixed_p = 1; 7623 7624 /* Insert any nops that might be needed between the .set noreorder 7625 block and the previous instructions. We will later remove any 7626 nops that turn out not to be needed. */ 7627 nops = nops_for_insn (0, history, NULL); 7628 if (nops > 0) 7629 { 7630 if (mips_optimize != 0) 7631 { 7632 /* Record the frag which holds the nop instructions, so 7633 that we can remove them if we don't need them. */ 7634 frag_grow (nops * NOP_INSN_SIZE); 7635 prev_nop_frag = frag_now; 7636 prev_nop_frag_holds = nops; 7637 prev_nop_frag_required = 0; 7638 prev_nop_frag_since = 0; 7639 } 7640 7641 for (; nops > 0; --nops) 7642 add_fixed_insn (NOP_INSN); 7643 7644 /* Move on to a new frag, so that it is safe to simply 7645 decrease the size of prev_nop_frag. */ 7646 frag_wane (frag_now); 7647 frag_new (0); 7648 mips_move_text_labels (); 7649 } 7650 mips_mark_labels (); 7651 mips_clear_insn_labels (); 7652 } 7653 mips_opts.noreorder++; 7654 mips_any_noreorder = 1; 7655 } 7656 7657 /* End a nested noreorder block. */ 7658 7659 static void 7660 end_noreorder (void) 7661 { 7662 mips_opts.noreorder--; 7663 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) 7664 { 7665 /* Commit to inserting prev_nop_frag_required nops and go back to 7666 handling nop insertion the .set reorder way. */ 7667 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) 7668 * NOP_INSN_SIZE); 7669 insert_into_history (prev_nop_frag_since, 7670 prev_nop_frag_required, NOP_INSN); 7671 prev_nop_frag = NULL; 7672 } 7673 } 7674 7675 /* Sign-extend 32-bit mode constants that have bit 31 set and all 7676 higher bits unset. */ 7677 7678 static void 7679 normalize_constant_expr (expressionS *ex) 7680 { 7681 if (ex->X_op == O_constant 7682 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 7683 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 7684 - 0x80000000); 7685 } 7686 7687 /* Sign-extend 32-bit mode address offsets that have bit 31 set and 7688 all higher bits unset. */ 7689 7690 static void 7691 normalize_address_expr (expressionS *ex) 7692 { 7693 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) 7694 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) 7695 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 7696 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 7697 - 0x80000000); 7698 } 7699 7700 /* Try to match TOKENS against OPCODE, storing the result in INSN. 7701 Return true if the match was successful. 7702 7703 OPCODE_EXTRA is a value that should be ORed into the opcode 7704 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if 7705 there are more alternatives after OPCODE and SOFT_MATCH is 7706 as for mips_arg_info. */ 7707 7708 static bfd_boolean 7709 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 7710 struct mips_operand_token *tokens, unsigned int opcode_extra, 7711 bfd_boolean lax_match, bfd_boolean complete_p) 7712 { 7713 const char *args; 7714 struct mips_arg_info arg; 7715 const struct mips_operand *operand; 7716 char c; 7717 7718 imm_expr.X_op = O_absent; 7719 offset_expr.X_op = O_absent; 7720 offset_reloc[0] = BFD_RELOC_UNUSED; 7721 offset_reloc[1] = BFD_RELOC_UNUSED; 7722 offset_reloc[2] = BFD_RELOC_UNUSED; 7723 7724 create_insn (insn, opcode); 7725 /* When no opcode suffix is specified, assume ".xyzw". */ 7726 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) 7727 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; 7728 else 7729 insn->insn_opcode |= opcode_extra; 7730 memset (&arg, 0, sizeof (arg)); 7731 arg.insn = insn; 7732 arg.token = tokens; 7733 arg.argnum = 1; 7734 arg.last_regno = ILLEGAL_REG; 7735 arg.dest_regno = ILLEGAL_REG; 7736 arg.lax_match = lax_match; 7737 for (args = opcode->args;; ++args) 7738 { 7739 if (arg.token->type == OT_END) 7740 { 7741 /* Handle unary instructions in which only one operand is given. 7742 The source is then the same as the destination. */ 7743 if (arg.opnum == 1 && *args == ',') 7744 { 7745 operand = (mips_opts.micromips 7746 ? decode_micromips_operand (args + 1) 7747 : decode_mips_operand (args + 1)); 7748 if (operand && mips_optional_operand_p (operand)) 7749 { 7750 arg.token = tokens; 7751 arg.argnum = 1; 7752 continue; 7753 } 7754 } 7755 7756 /* Treat elided base registers as $0. */ 7757 if (strcmp (args, "(b)") == 0) 7758 args += 3; 7759 7760 if (args[0] == '+') 7761 switch (args[1]) 7762 { 7763 case 'K': 7764 case 'N': 7765 /* The register suffix is optional. */ 7766 args += 2; 7767 break; 7768 } 7769 7770 /* Fail the match if there were too few operands. */ 7771 if (*args) 7772 return FALSE; 7773 7774 /* Successful match. */ 7775 if (!complete_p) 7776 return TRUE; 7777 clear_insn_error (); 7778 if (arg.dest_regno == arg.last_regno 7779 && strncmp (insn->insn_mo->name, "jalr", 4) == 0) 7780 { 7781 if (arg.opnum == 2) 7782 set_insn_error 7783 (0, _("source and destination must be different")); 7784 else if (arg.last_regno == 31) 7785 set_insn_error 7786 (0, _("a destination register must be supplied")); 7787 } 7788 else if (arg.last_regno == 31 7789 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 7790 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) 7791 set_insn_error (0, _("the source register must not be $31")); 7792 check_completed_insn (&arg); 7793 return TRUE; 7794 } 7795 7796 /* Fail the match if the line has too many operands. */ 7797 if (*args == 0) 7798 return FALSE; 7799 7800 /* Handle characters that need to match exactly. */ 7801 if (*args == '(' || *args == ')' || *args == ',') 7802 { 7803 if (match_char (&arg, *args)) 7804 continue; 7805 return FALSE; 7806 } 7807 if (*args == '#') 7808 { 7809 ++args; 7810 if (arg.token->type == OT_DOUBLE_CHAR 7811 && arg.token->u.ch == *args) 7812 { 7813 ++arg.token; 7814 continue; 7815 } 7816 return FALSE; 7817 } 7818 7819 /* Handle special macro operands. Work out the properties of 7820 other operands. */ 7821 arg.opnum += 1; 7822 switch (*args) 7823 { 7824 case '-': 7825 switch (args[1]) 7826 { 7827 case 'A': 7828 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; 7829 break; 7830 7831 case 'B': 7832 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; 7833 break; 7834 } 7835 break; 7836 7837 case '+': 7838 switch (args[1]) 7839 { 7840 case 'i': 7841 *offset_reloc = BFD_RELOC_MIPS_JMP; 7842 break; 7843 7844 case '\'': 7845 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; 7846 break; 7847 7848 case '\"': 7849 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; 7850 break; 7851 } 7852 break; 7853 7854 case 'I': 7855 if (!match_const_int (&arg, &imm_expr.X_add_number)) 7856 return FALSE; 7857 imm_expr.X_op = O_constant; 7858 if (GPR_SIZE == 32) 7859 normalize_constant_expr (&imm_expr); 7860 continue; 7861 7862 case 'A': 7863 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 7864 { 7865 /* Assume that the offset has been elided and that what 7866 we saw was a base register. The match will fail later 7867 if that assumption turns out to be wrong. */ 7868 offset_expr.X_op = O_constant; 7869 offset_expr.X_add_number = 0; 7870 } 7871 else 7872 { 7873 if (!match_expression (&arg, &offset_expr, offset_reloc)) 7874 return FALSE; 7875 normalize_address_expr (&offset_expr); 7876 } 7877 continue; 7878 7879 case 'F': 7880 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7881 8, TRUE)) 7882 return FALSE; 7883 continue; 7884 7885 case 'L': 7886 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7887 8, FALSE)) 7888 return FALSE; 7889 continue; 7890 7891 case 'f': 7892 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7893 4, TRUE)) 7894 return FALSE; 7895 continue; 7896 7897 case 'l': 7898 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7899 4, FALSE)) 7900 return FALSE; 7901 continue; 7902 7903 case 'p': 7904 *offset_reloc = BFD_RELOC_16_PCREL_S2; 7905 break; 7906 7907 case 'a': 7908 *offset_reloc = BFD_RELOC_MIPS_JMP; 7909 break; 7910 7911 case 'm': 7912 gas_assert (mips_opts.micromips); 7913 c = args[1]; 7914 switch (c) 7915 { 7916 case 'D': 7917 case 'E': 7918 if (!forced_insn_length) 7919 *offset_reloc = (int) BFD_RELOC_UNUSED + c; 7920 else if (c == 'D') 7921 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; 7922 else 7923 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; 7924 break; 7925 } 7926 break; 7927 } 7928 7929 operand = (mips_opts.micromips 7930 ? decode_micromips_operand (args) 7931 : decode_mips_operand (args)); 7932 if (!operand) 7933 abort (); 7934 7935 /* Skip prefixes. */ 7936 if (*args == '+' || *args == 'm' || *args == '-') 7937 args++; 7938 7939 if (mips_optional_operand_p (operand) 7940 && args[1] == ',' 7941 && (arg.token[0].type != OT_REG 7942 || arg.token[1].type == OT_END)) 7943 { 7944 /* Assume that the register has been elided and is the 7945 same as the first operand. */ 7946 arg.token = tokens; 7947 arg.argnum = 1; 7948 } 7949 7950 if (!match_operand (&arg, operand)) 7951 return FALSE; 7952 } 7953 } 7954 7955 /* Like match_insn, but for MIPS16. */ 7956 7957 static bfd_boolean 7958 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 7959 struct mips_operand_token *tokens) 7960 { 7961 const char *args; 7962 const struct mips_operand *operand; 7963 const struct mips_operand *ext_operand; 7964 struct mips_arg_info arg; 7965 int relax_char; 7966 7967 create_insn (insn, opcode); 7968 imm_expr.X_op = O_absent; 7969 offset_expr.X_op = O_absent; 7970 offset_reloc[0] = BFD_RELOC_UNUSED; 7971 offset_reloc[1] = BFD_RELOC_UNUSED; 7972 offset_reloc[2] = BFD_RELOC_UNUSED; 7973 relax_char = 0; 7974 7975 memset (&arg, 0, sizeof (arg)); 7976 arg.insn = insn; 7977 arg.token = tokens; 7978 arg.argnum = 1; 7979 arg.last_regno = ILLEGAL_REG; 7980 arg.dest_regno = ILLEGAL_REG; 7981 relax_char = 0; 7982 for (args = opcode->args;; ++args) 7983 { 7984 int c; 7985 7986 if (arg.token->type == OT_END) 7987 { 7988 offsetT value; 7989 7990 /* Handle unary instructions in which only one operand is given. 7991 The source is then the same as the destination. */ 7992 if (arg.opnum == 1 && *args == ',') 7993 { 7994 operand = decode_mips16_operand (args[1], FALSE); 7995 if (operand && mips_optional_operand_p (operand)) 7996 { 7997 arg.token = tokens; 7998 arg.argnum = 1; 7999 continue; 8000 } 8001 } 8002 8003 /* Fail the match if there were too few operands. */ 8004 if (*args) 8005 return FALSE; 8006 8007 /* Successful match. Stuff the immediate value in now, if 8008 we can. */ 8009 clear_insn_error (); 8010 if (opcode->pinfo == INSN_MACRO) 8011 { 8012 gas_assert (relax_char == 0 || relax_char == 'p'); 8013 gas_assert (*offset_reloc == BFD_RELOC_UNUSED); 8014 } 8015 else if (relax_char 8016 && offset_expr.X_op == O_constant 8017 && calculate_reloc (*offset_reloc, 8018 offset_expr.X_add_number, 8019 &value)) 8020 { 8021 mips16_immed (NULL, 0, relax_char, *offset_reloc, value, 8022 forced_insn_length, &insn->insn_opcode); 8023 offset_expr.X_op = O_absent; 8024 *offset_reloc = BFD_RELOC_UNUSED; 8025 } 8026 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) 8027 { 8028 if (forced_insn_length == 2) 8029 set_insn_error (0, _("invalid unextended operand value")); 8030 forced_insn_length = 4; 8031 insn->insn_opcode |= MIPS16_EXTEND; 8032 } 8033 else if (relax_char) 8034 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; 8035 8036 check_completed_insn (&arg); 8037 return TRUE; 8038 } 8039 8040 /* Fail the match if the line has too many operands. */ 8041 if (*args == 0) 8042 return FALSE; 8043 8044 /* Handle characters that need to match exactly. */ 8045 if (*args == '(' || *args == ')' || *args == ',') 8046 { 8047 if (match_char (&arg, *args)) 8048 continue; 8049 return FALSE; 8050 } 8051 8052 arg.opnum += 1; 8053 c = *args; 8054 switch (c) 8055 { 8056 case 'p': 8057 case 'q': 8058 case 'A': 8059 case 'B': 8060 case 'E': 8061 relax_char = c; 8062 break; 8063 8064 case 'I': 8065 if (!match_const_int (&arg, &imm_expr.X_add_number)) 8066 return FALSE; 8067 imm_expr.X_op = O_constant; 8068 if (GPR_SIZE == 32) 8069 normalize_constant_expr (&imm_expr); 8070 continue; 8071 8072 case 'a': 8073 case 'i': 8074 *offset_reloc = BFD_RELOC_MIPS16_JMP; 8075 insn->insn_opcode <<= 16; 8076 break; 8077 } 8078 8079 operand = decode_mips16_operand (c, FALSE); 8080 if (!operand) 8081 abort (); 8082 8083 /* '6' is a special case. It is used for BREAK and SDBBP, 8084 whose operands are only meaningful to the software that decodes 8085 them. This means that there is no architectural reason why 8086 they cannot be prefixed by EXTEND, but in practice, 8087 exception handlers will only look at the instruction 8088 itself. We therefore allow '6' to be extended when 8089 disassembling but not when assembling. */ 8090 if (operand->type != OP_PCREL && c != '6') 8091 { 8092 ext_operand = decode_mips16_operand (c, TRUE); 8093 if (operand != ext_operand) 8094 { 8095 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 8096 { 8097 offset_expr.X_op = O_constant; 8098 offset_expr.X_add_number = 0; 8099 relax_char = c; 8100 continue; 8101 } 8102 8103 /* We need the OT_INTEGER check because some MIPS16 8104 immediate variants are listed before the register ones. */ 8105 if (arg.token->type != OT_INTEGER 8106 || !match_expression (&arg, &offset_expr, offset_reloc)) 8107 return FALSE; 8108 8109 /* '8' is used for SLTI(U) and has traditionally not 8110 been allowed to take relocation operators. */ 8111 if (offset_reloc[0] != BFD_RELOC_UNUSED 8112 && (ext_operand->size != 16 || c == '8')) 8113 return FALSE; 8114 8115 relax_char = c; 8116 continue; 8117 } 8118 } 8119 8120 if (mips_optional_operand_p (operand) 8121 && args[1] == ',' 8122 && (arg.token[0].type != OT_REG 8123 || arg.token[1].type == OT_END)) 8124 { 8125 /* Assume that the register has been elided and is the 8126 same as the first operand. */ 8127 arg.token = tokens; 8128 arg.argnum = 1; 8129 } 8130 8131 if (!match_operand (&arg, operand)) 8132 return FALSE; 8133 } 8134 } 8135 8136 /* Record that the current instruction is invalid for the current ISA. */ 8137 8138 static void 8139 match_invalid_for_isa (void) 8140 { 8141 set_insn_error_ss 8142 (0, _("opcode not supported on this processor: %s (%s)"), 8143 mips_cpu_info_from_arch (mips_opts.arch)->name, 8144 mips_cpu_info_from_isa (mips_opts.isa)->name); 8145 } 8146 8147 /* Try to match TOKENS against a series of opcode entries, starting at FIRST. 8148 Return true if a definite match or failure was found, storing any match 8149 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode 8150 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already 8151 tried and failed to match under normal conditions and now want to try a 8152 more relaxed match. */ 8153 8154 static bfd_boolean 8155 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8156 const struct mips_opcode *past, struct mips_operand_token *tokens, 8157 int opcode_extra, bfd_boolean lax_match) 8158 { 8159 const struct mips_opcode *opcode; 8160 const struct mips_opcode *invalid_delay_slot; 8161 bfd_boolean seen_valid_for_isa, seen_valid_for_size; 8162 8163 /* Search for a match, ignoring alternatives that don't satisfy the 8164 current ISA or forced_length. */ 8165 invalid_delay_slot = 0; 8166 seen_valid_for_isa = FALSE; 8167 seen_valid_for_size = FALSE; 8168 opcode = first; 8169 do 8170 { 8171 gas_assert (strcmp (opcode->name, first->name) == 0); 8172 if (is_opcode_valid (opcode)) 8173 { 8174 seen_valid_for_isa = TRUE; 8175 if (is_size_valid (opcode)) 8176 { 8177 bfd_boolean delay_slot_ok; 8178 8179 seen_valid_for_size = TRUE; 8180 delay_slot_ok = is_delay_slot_valid (opcode); 8181 if (match_insn (insn, opcode, tokens, opcode_extra, 8182 lax_match, delay_slot_ok)) 8183 { 8184 if (!delay_slot_ok) 8185 { 8186 if (!invalid_delay_slot) 8187 invalid_delay_slot = opcode; 8188 } 8189 else 8190 return TRUE; 8191 } 8192 } 8193 } 8194 ++opcode; 8195 } 8196 while (opcode < past && strcmp (opcode->name, first->name) == 0); 8197 8198 /* If the only matches we found had the wrong length for the delay slot, 8199 pick the first such match. We'll issue an appropriate warning later. */ 8200 if (invalid_delay_slot) 8201 { 8202 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, 8203 lax_match, TRUE)) 8204 return TRUE; 8205 abort (); 8206 } 8207 8208 /* Handle the case where we didn't try to match an instruction because 8209 all the alternatives were incompatible with the current ISA. */ 8210 if (!seen_valid_for_isa) 8211 { 8212 match_invalid_for_isa (); 8213 return TRUE; 8214 } 8215 8216 /* Handle the case where we didn't try to match an instruction because 8217 all the alternatives were of the wrong size. */ 8218 if (!seen_valid_for_size) 8219 { 8220 if (mips_opts.insn32) 8221 set_insn_error (0, _("opcode not supported in the `insn32' mode")); 8222 else 8223 set_insn_error_i 8224 (0, _("unrecognized %d-bit version of microMIPS opcode"), 8225 8 * forced_insn_length); 8226 return TRUE; 8227 } 8228 8229 return FALSE; 8230 } 8231 8232 /* Like match_insns, but for MIPS16. */ 8233 8234 static bfd_boolean 8235 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8236 struct mips_operand_token *tokens) 8237 { 8238 const struct mips_opcode *opcode; 8239 bfd_boolean seen_valid_for_isa; 8240 8241 /* Search for a match, ignoring alternatives that don't satisfy the 8242 current ISA. There are no separate entries for extended forms so 8243 we deal with forced_length later. */ 8244 seen_valid_for_isa = FALSE; 8245 opcode = first; 8246 do 8247 { 8248 gas_assert (strcmp (opcode->name, first->name) == 0); 8249 if (is_opcode_valid_16 (opcode)) 8250 { 8251 seen_valid_for_isa = TRUE; 8252 if (match_mips16_insn (insn, opcode, tokens)) 8253 return TRUE; 8254 } 8255 ++opcode; 8256 } 8257 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] 8258 && strcmp (opcode->name, first->name) == 0); 8259 8260 /* Handle the case where we didn't try to match an instruction because 8261 all the alternatives were incompatible with the current ISA. */ 8262 if (!seen_valid_for_isa) 8263 { 8264 match_invalid_for_isa (); 8265 return TRUE; 8266 } 8267 8268 return FALSE; 8269 } 8270 8271 /* Set up global variables for the start of a new macro. */ 8272 8273 static void 8274 macro_start (void) 8275 { 8276 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); 8277 memset (&mips_macro_warning.first_insn_sizes, 0, 8278 sizeof (mips_macro_warning.first_insn_sizes)); 8279 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); 8280 mips_macro_warning.delay_slot_p = (mips_opts.noreorder 8281 && delayed_branch_p (&history[0])); 8282 switch (history[0].insn_mo->pinfo2 8283 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) 8284 { 8285 case INSN2_BRANCH_DELAY_32BIT: 8286 mips_macro_warning.delay_slot_length = 4; 8287 break; 8288 case INSN2_BRANCH_DELAY_16BIT: 8289 mips_macro_warning.delay_slot_length = 2; 8290 break; 8291 default: 8292 mips_macro_warning.delay_slot_length = 0; 8293 break; 8294 } 8295 mips_macro_warning.first_frag = NULL; 8296 } 8297 8298 /* Given that a macro is longer than one instruction or of the wrong size, 8299 return the appropriate warning for it. Return null if no warning is 8300 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, 8301 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, 8302 and RELAX_NOMACRO. */ 8303 8304 static const char * 8305 macro_warning (relax_substateT subtype) 8306 { 8307 if (subtype & RELAX_DELAY_SLOT) 8308 return _("macro instruction expanded into multiple instructions" 8309 " in a branch delay slot"); 8310 else if (subtype & RELAX_NOMACRO) 8311 return _("macro instruction expanded into multiple instructions"); 8312 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST 8313 | RELAX_DELAY_SLOT_SIZE_SECOND)) 8314 return ((subtype & RELAX_DELAY_SLOT_16BIT) 8315 ? _("macro instruction expanded into a wrong size instruction" 8316 " in a 16-bit branch delay slot") 8317 : _("macro instruction expanded into a wrong size instruction" 8318 " in a 32-bit branch delay slot")); 8319 else 8320 return 0; 8321 } 8322 8323 /* Finish up a macro. Emit warnings as appropriate. */ 8324 8325 static void 8326 macro_end (void) 8327 { 8328 /* Relaxation warning flags. */ 8329 relax_substateT subtype = 0; 8330 8331 /* Check delay slot size requirements. */ 8332 if (mips_macro_warning.delay_slot_length == 2) 8333 subtype |= RELAX_DELAY_SLOT_16BIT; 8334 if (mips_macro_warning.delay_slot_length != 0) 8335 { 8336 if (mips_macro_warning.delay_slot_length 8337 != mips_macro_warning.first_insn_sizes[0]) 8338 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; 8339 if (mips_macro_warning.delay_slot_length 8340 != mips_macro_warning.first_insn_sizes[1]) 8341 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; 8342 } 8343 8344 /* Check instruction count requirements. */ 8345 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) 8346 { 8347 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) 8348 subtype |= RELAX_SECOND_LONGER; 8349 if (mips_opts.warn_about_macros) 8350 subtype |= RELAX_NOMACRO; 8351 if (mips_macro_warning.delay_slot_p) 8352 subtype |= RELAX_DELAY_SLOT; 8353 } 8354 8355 /* If both alternatives fail to fill a delay slot correctly, 8356 emit the warning now. */ 8357 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 8358 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) 8359 { 8360 relax_substateT s; 8361 const char *msg; 8362 8363 s = subtype & (RELAX_DELAY_SLOT_16BIT 8364 | RELAX_DELAY_SLOT_SIZE_FIRST 8365 | RELAX_DELAY_SLOT_SIZE_SECOND); 8366 msg = macro_warning (s); 8367 if (msg != NULL) 8368 as_warn ("%s", msg); 8369 subtype &= ~s; 8370 } 8371 8372 /* If both implementations are longer than 1 instruction, then emit the 8373 warning now. */ 8374 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) 8375 { 8376 relax_substateT s; 8377 const char *msg; 8378 8379 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); 8380 msg = macro_warning (s); 8381 if (msg != NULL) 8382 as_warn ("%s", msg); 8383 subtype &= ~s; 8384 } 8385 8386 /* If any flags still set, then one implementation might need a warning 8387 and the other either will need one of a different kind or none at all. 8388 Pass any remaining flags over to relaxation. */ 8389 if (mips_macro_warning.first_frag != NULL) 8390 mips_macro_warning.first_frag->fr_subtype |= subtype; 8391 } 8392 8393 /* Instruction operand formats used in macros that vary between 8394 standard MIPS and microMIPS code. */ 8395 8396 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; 8397 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; 8398 static const char * const jalr_fmt[2] = { "d,s", "t,s" }; 8399 static const char * const lui_fmt[2] = { "t,u", "s,u" }; 8400 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; 8401 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; 8402 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; 8403 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; 8404 8405 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) 8406 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ 8407 : cop12_fmt[mips_opts.micromips]) 8408 #define JALR_FMT (jalr_fmt[mips_opts.micromips]) 8409 #define LUI_FMT (lui_fmt[mips_opts.micromips]) 8410 #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) 8411 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ 8412 : mem12_fmt[mips_opts.micromips]) 8413 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) 8414 #define SHFT_FMT (shft_fmt[mips_opts.micromips]) 8415 #define TRAP_FMT (trap_fmt[mips_opts.micromips]) 8416 8417 /* Read a macro's relocation codes from *ARGS and store them in *R. 8418 The first argument in *ARGS will be either the code for a single 8419 relocation or -1 followed by the three codes that make up a 8420 composite relocation. */ 8421 8422 static void 8423 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) 8424 { 8425 int i, next; 8426 8427 next = va_arg (*args, int); 8428 if (next >= 0) 8429 r[0] = (bfd_reloc_code_real_type) next; 8430 else 8431 { 8432 for (i = 0; i < 3; i++) 8433 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); 8434 /* This function is only used for 16-bit relocation fields. 8435 To make the macro code simpler, treat an unrelocated value 8436 in the same way as BFD_RELOC_LO16. */ 8437 if (r[0] == BFD_RELOC_UNUSED) 8438 r[0] = BFD_RELOC_LO16; 8439 } 8440 } 8441 8442 /* Build an instruction created by a macro expansion. This is passed 8443 a pointer to the count of instructions created so far, an 8444 expression, the name of the instruction to build, an operand format 8445 string, and corresponding arguments. */ 8446 8447 static void 8448 macro_build (expressionS *ep, const char *name, const char *fmt, ...) 8449 { 8450 const struct mips_opcode *mo = NULL; 8451 bfd_reloc_code_real_type r[3]; 8452 const struct mips_opcode *amo; 8453 const struct mips_operand *operand; 8454 struct hash_control *hash; 8455 struct mips_cl_insn insn; 8456 va_list args; 8457 unsigned int uval; 8458 8459 va_start (args, fmt); 8460 8461 if (mips_opts.mips16) 8462 { 8463 mips16_macro_build (ep, name, fmt, &args); 8464 va_end (args); 8465 return; 8466 } 8467 8468 r[0] = BFD_RELOC_UNUSED; 8469 r[1] = BFD_RELOC_UNUSED; 8470 r[2] = BFD_RELOC_UNUSED; 8471 hash = mips_opts.micromips ? micromips_op_hash : op_hash; 8472 amo = (struct mips_opcode *) hash_find (hash, name); 8473 gas_assert (amo); 8474 gas_assert (strcmp (name, amo->name) == 0); 8475 8476 do 8477 { 8478 /* Search until we get a match for NAME. It is assumed here that 8479 macros will never generate MDMX, MIPS-3D, or MT instructions. 8480 We try to match an instruction that fulfils the branch delay 8481 slot instruction length requirement (if any) of the previous 8482 instruction. While doing this we record the first instruction 8483 seen that matches all the other conditions and use it anyway 8484 if the requirement cannot be met; we will issue an appropriate 8485 warning later on. */ 8486 if (strcmp (fmt, amo->args) == 0 8487 && amo->pinfo != INSN_MACRO 8488 && is_opcode_valid (amo) 8489 && is_size_valid (amo)) 8490 { 8491 if (is_delay_slot_valid (amo)) 8492 { 8493 mo = amo; 8494 break; 8495 } 8496 else if (!mo) 8497 mo = amo; 8498 } 8499 8500 ++amo; 8501 gas_assert (amo->name); 8502 } 8503 while (strcmp (name, amo->name) == 0); 8504 8505 gas_assert (mo); 8506 create_insn (&insn, mo); 8507 for (; *fmt; ++fmt) 8508 { 8509 switch (*fmt) 8510 { 8511 case ',': 8512 case '(': 8513 case ')': 8514 case 'z': 8515 break; 8516 8517 case 'i': 8518 case 'j': 8519 macro_read_relocs (&args, r); 8520 gas_assert (*r == BFD_RELOC_GPREL16 8521 || *r == BFD_RELOC_MIPS_HIGHER 8522 || *r == BFD_RELOC_HI16_S 8523 || *r == BFD_RELOC_LO16 8524 || *r == BFD_RELOC_MIPS_GOT_OFST); 8525 break; 8526 8527 case 'o': 8528 macro_read_relocs (&args, r); 8529 break; 8530 8531 case 'u': 8532 macro_read_relocs (&args, r); 8533 gas_assert (ep != NULL 8534 && (ep->X_op == O_constant 8535 || (ep->X_op == O_symbol 8536 && (*r == BFD_RELOC_MIPS_HIGHEST 8537 || *r == BFD_RELOC_HI16_S 8538 || *r == BFD_RELOC_HI16 8539 || *r == BFD_RELOC_GPREL16 8540 || *r == BFD_RELOC_MIPS_GOT_HI16 8541 || *r == BFD_RELOC_MIPS_CALL_HI16)))); 8542 break; 8543 8544 case 'p': 8545 gas_assert (ep != NULL); 8546 8547 /* 8548 * This allows macro() to pass an immediate expression for 8549 * creating short branches without creating a symbol. 8550 * 8551 * We don't allow branch relaxation for these branches, as 8552 * they should only appear in ".set nomacro" anyway. 8553 */ 8554 if (ep->X_op == O_constant) 8555 { 8556 /* For microMIPS we always use relocations for branches. 8557 So we should not resolve immediate values. */ 8558 gas_assert (!mips_opts.micromips); 8559 8560 if ((ep->X_add_number & 3) != 0) 8561 as_bad (_("branch to misaligned address (0x%lx)"), 8562 (unsigned long) ep->X_add_number); 8563 if ((ep->X_add_number + 0x20000) & ~0x3ffff) 8564 as_bad (_("branch address range overflow (0x%lx)"), 8565 (unsigned long) ep->X_add_number); 8566 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; 8567 ep = NULL; 8568 } 8569 else 8570 *r = BFD_RELOC_16_PCREL_S2; 8571 break; 8572 8573 case 'a': 8574 gas_assert (ep != NULL); 8575 *r = BFD_RELOC_MIPS_JMP; 8576 break; 8577 8578 default: 8579 operand = (mips_opts.micromips 8580 ? decode_micromips_operand (fmt) 8581 : decode_mips_operand (fmt)); 8582 if (!operand) 8583 abort (); 8584 8585 uval = va_arg (args, int); 8586 if (operand->type == OP_CLO_CLZ_DEST) 8587 uval |= (uval << 5); 8588 insn_insert_operand (&insn, operand, uval); 8589 8590 if (*fmt == '+' || *fmt == 'm' || *fmt == '-') 8591 ++fmt; 8592 break; 8593 } 8594 } 8595 va_end (args); 8596 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 8597 8598 append_insn (&insn, ep, r, TRUE); 8599 } 8600 8601 static void 8602 mips16_macro_build (expressionS *ep, const char *name, const char *fmt, 8603 va_list *args) 8604 { 8605 struct mips_opcode *mo; 8606 struct mips_cl_insn insn; 8607 const struct mips_operand *operand; 8608 bfd_reloc_code_real_type r[3] 8609 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 8610 8611 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); 8612 gas_assert (mo); 8613 gas_assert (strcmp (name, mo->name) == 0); 8614 8615 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) 8616 { 8617 ++mo; 8618 gas_assert (mo->name); 8619 gas_assert (strcmp (name, mo->name) == 0); 8620 } 8621 8622 create_insn (&insn, mo); 8623 for (; *fmt; ++fmt) 8624 { 8625 int c; 8626 8627 c = *fmt; 8628 switch (c) 8629 { 8630 case ',': 8631 case '(': 8632 case ')': 8633 break; 8634 8635 case '0': 8636 case 'S': 8637 case 'P': 8638 case 'R': 8639 break; 8640 8641 case '<': 8642 case '>': 8643 case '4': 8644 case '5': 8645 case 'H': 8646 case 'W': 8647 case 'D': 8648 case 'j': 8649 case '8': 8650 case 'V': 8651 case 'C': 8652 case 'U': 8653 case 'k': 8654 case 'K': 8655 case 'p': 8656 case 'q': 8657 { 8658 offsetT value; 8659 8660 gas_assert (ep != NULL); 8661 8662 if (ep->X_op != O_constant) 8663 *r = (int) BFD_RELOC_UNUSED + c; 8664 else if (calculate_reloc (*r, ep->X_add_number, &value)) 8665 { 8666 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); 8667 ep = NULL; 8668 *r = BFD_RELOC_UNUSED; 8669 } 8670 } 8671 break; 8672 8673 default: 8674 operand = decode_mips16_operand (c, FALSE); 8675 if (!operand) 8676 abort (); 8677 8678 insn_insert_operand (&insn, operand, va_arg (*args, int)); 8679 break; 8680 } 8681 } 8682 8683 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 8684 8685 append_insn (&insn, ep, r, TRUE); 8686 } 8687 8688 /* 8689 * Generate a "jalr" instruction with a relocation hint to the called 8690 * function. This occurs in NewABI PIC code. 8691 */ 8692 static void 8693 macro_build_jalr (expressionS *ep, int cprestore) 8694 { 8695 static const bfd_reloc_code_real_type jalr_relocs[2] 8696 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; 8697 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; 8698 const char *jalr; 8699 char *f = NULL; 8700 8701 if (MIPS_JALR_HINT_P (ep)) 8702 { 8703 frag_grow (8); 8704 f = frag_more (0); 8705 } 8706 if (mips_opts.micromips) 8707 { 8708 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 8709 ? "jalr" : "jalrs"); 8710 if (MIPS_JALR_HINT_P (ep) 8711 || mips_opts.insn32 8712 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 8713 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); 8714 else 8715 macro_build (NULL, jalr, "mj", PIC_CALL_REG); 8716 } 8717 else 8718 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); 8719 if (MIPS_JALR_HINT_P (ep)) 8720 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); 8721 } 8722 8723 /* 8724 * Generate a "lui" instruction. 8725 */ 8726 static void 8727 macro_build_lui (expressionS *ep, int regnum) 8728 { 8729 gas_assert (! mips_opts.mips16); 8730 8731 if (ep->X_op != O_constant) 8732 { 8733 gas_assert (ep->X_op == O_symbol); 8734 /* _gp_disp is a special case, used from s_cpload. 8735 __gnu_local_gp is used if mips_no_shared. */ 8736 gas_assert (mips_pic == NO_PIC 8737 || (! HAVE_NEWABI 8738 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) 8739 || (! mips_in_shared 8740 && strcmp (S_GET_NAME (ep->X_add_symbol), 8741 "__gnu_local_gp") == 0)); 8742 } 8743 8744 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); 8745 } 8746 8747 /* Generate a sequence of instructions to do a load or store from a constant 8748 offset off of a base register (breg) into/from a target register (treg), 8749 using AT if necessary. */ 8750 static void 8751 macro_build_ldst_constoffset (expressionS *ep, const char *op, 8752 int treg, int breg, int dbl) 8753 { 8754 gas_assert (ep->X_op == O_constant); 8755 8756 /* Sign-extending 32-bit constants makes their handling easier. */ 8757 if (!dbl) 8758 normalize_constant_expr (ep); 8759 8760 /* Right now, this routine can only handle signed 32-bit constants. */ 8761 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) 8762 as_warn (_("operand overflow")); 8763 8764 if (IS_SEXT_16BIT_NUM(ep->X_add_number)) 8765 { 8766 /* Signed 16-bit offset will fit in the op. Easy! */ 8767 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); 8768 } 8769 else 8770 { 8771 /* 32-bit offset, need multiple instructions and AT, like: 8772 lui $tempreg,const_hi (BFD_RELOC_HI16_S) 8773 addu $tempreg,$tempreg,$breg 8774 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) 8775 to handle the complete offset. */ 8776 macro_build_lui (ep, AT); 8777 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 8778 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); 8779 8780 if (!mips_opts.at) 8781 as_bad (_("macro used $at after \".set noat\"")); 8782 } 8783 } 8784 8785 /* set_at() 8786 * Generates code to set the $at register to true (one) 8787 * if reg is less than the immediate expression. 8788 */ 8789 static void 8790 set_at (int reg, int unsignedp) 8791 { 8792 if (imm_expr.X_add_number >= -0x8000 8793 && imm_expr.X_add_number < 0x8000) 8794 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", 8795 AT, reg, BFD_RELOC_LO16); 8796 else 8797 { 8798 load_register (AT, &imm_expr, GPR_SIZE == 64); 8799 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); 8800 } 8801 } 8802 8803 /* Count the leading zeroes by performing a binary chop. This is a 8804 bulky bit of source, but performance is a LOT better for the 8805 majority of values than a simple loop to count the bits: 8806 for (lcnt = 0; (lcnt < 32); lcnt++) 8807 if ((v) & (1 << (31 - lcnt))) 8808 break; 8809 However it is not code size friendly, and the gain will drop a bit 8810 on certain cached systems. 8811 */ 8812 #define COUNT_TOP_ZEROES(v) \ 8813 (((v) & ~0xffff) == 0 \ 8814 ? ((v) & ~0xff) == 0 \ 8815 ? ((v) & ~0xf) == 0 \ 8816 ? ((v) & ~0x3) == 0 \ 8817 ? ((v) & ~0x1) == 0 \ 8818 ? !(v) \ 8819 ? 32 \ 8820 : 31 \ 8821 : 30 \ 8822 : ((v) & ~0x7) == 0 \ 8823 ? 29 \ 8824 : 28 \ 8825 : ((v) & ~0x3f) == 0 \ 8826 ? ((v) & ~0x1f) == 0 \ 8827 ? 27 \ 8828 : 26 \ 8829 : ((v) & ~0x7f) == 0 \ 8830 ? 25 \ 8831 : 24 \ 8832 : ((v) & ~0xfff) == 0 \ 8833 ? ((v) & ~0x3ff) == 0 \ 8834 ? ((v) & ~0x1ff) == 0 \ 8835 ? 23 \ 8836 : 22 \ 8837 : ((v) & ~0x7ff) == 0 \ 8838 ? 21 \ 8839 : 20 \ 8840 : ((v) & ~0x3fff) == 0 \ 8841 ? ((v) & ~0x1fff) == 0 \ 8842 ? 19 \ 8843 : 18 \ 8844 : ((v) & ~0x7fff) == 0 \ 8845 ? 17 \ 8846 : 16 \ 8847 : ((v) & ~0xffffff) == 0 \ 8848 ? ((v) & ~0xfffff) == 0 \ 8849 ? ((v) & ~0x3ffff) == 0 \ 8850 ? ((v) & ~0x1ffff) == 0 \ 8851 ? 15 \ 8852 : 14 \ 8853 : ((v) & ~0x7ffff) == 0 \ 8854 ? 13 \ 8855 : 12 \ 8856 : ((v) & ~0x3fffff) == 0 \ 8857 ? ((v) & ~0x1fffff) == 0 \ 8858 ? 11 \ 8859 : 10 \ 8860 : ((v) & ~0x7fffff) == 0 \ 8861 ? 9 \ 8862 : 8 \ 8863 : ((v) & ~0xfffffff) == 0 \ 8864 ? ((v) & ~0x3ffffff) == 0 \ 8865 ? ((v) & ~0x1ffffff) == 0 \ 8866 ? 7 \ 8867 : 6 \ 8868 : ((v) & ~0x7ffffff) == 0 \ 8869 ? 5 \ 8870 : 4 \ 8871 : ((v) & ~0x3fffffff) == 0 \ 8872 ? ((v) & ~0x1fffffff) == 0 \ 8873 ? 3 \ 8874 : 2 \ 8875 : ((v) & ~0x7fffffff) == 0 \ 8876 ? 1 \ 8877 : 0) 8878 8879 /* load_register() 8880 * This routine generates the least number of instructions necessary to load 8881 * an absolute expression value into a register. 8882 */ 8883 static void 8884 load_register (int reg, expressionS *ep, int dbl) 8885 { 8886 int freg; 8887 expressionS hi32, lo32; 8888 8889 if (ep->X_op != O_big) 8890 { 8891 gas_assert (ep->X_op == O_constant); 8892 8893 /* Sign-extending 32-bit constants makes their handling easier. */ 8894 if (!dbl) 8895 normalize_constant_expr (ep); 8896 8897 if (IS_SEXT_16BIT_NUM (ep->X_add_number)) 8898 { 8899 /* We can handle 16 bit signed values with an addiu to 8900 $zero. No need to ever use daddiu here, since $zero and 8901 the result are always correct in 32 bit mode. */ 8902 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 8903 return; 8904 } 8905 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) 8906 { 8907 /* We can handle 16 bit unsigned values with an ori to 8908 $zero. */ 8909 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 8910 return; 8911 } 8912 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) 8913 { 8914 /* 32 bit values require an lui. */ 8915 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 8916 if ((ep->X_add_number & 0xffff) != 0) 8917 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 8918 return; 8919 } 8920 } 8921 8922 /* The value is larger than 32 bits. */ 8923 8924 if (!dbl || GPR_SIZE == 32) 8925 { 8926 char value[32]; 8927 8928 sprintf_vma (value, ep->X_add_number); 8929 as_bad (_("number (0x%s) larger than 32 bits"), value); 8930 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 8931 return; 8932 } 8933 8934 if (ep->X_op != O_big) 8935 { 8936 hi32 = *ep; 8937 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 8938 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 8939 hi32.X_add_number &= 0xffffffff; 8940 lo32 = *ep; 8941 lo32.X_add_number &= 0xffffffff; 8942 } 8943 else 8944 { 8945 gas_assert (ep->X_add_number > 2); 8946 if (ep->X_add_number == 3) 8947 generic_bignum[3] = 0; 8948 else if (ep->X_add_number > 4) 8949 as_bad (_("number larger than 64 bits")); 8950 lo32.X_op = O_constant; 8951 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); 8952 hi32.X_op = O_constant; 8953 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); 8954 } 8955 8956 if (hi32.X_add_number == 0) 8957 freg = 0; 8958 else 8959 { 8960 int shift, bit; 8961 unsigned long hi, lo; 8962 8963 if (hi32.X_add_number == (offsetT) 0xffffffff) 8964 { 8965 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) 8966 { 8967 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 8968 return; 8969 } 8970 if (lo32.X_add_number & 0x80000000) 8971 { 8972 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 8973 if (lo32.X_add_number & 0xffff) 8974 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 8975 return; 8976 } 8977 } 8978 8979 /* Check for 16bit shifted constant. We know that hi32 is 8980 non-zero, so start the mask on the first bit of the hi32 8981 value. */ 8982 shift = 17; 8983 do 8984 { 8985 unsigned long himask, lomask; 8986 8987 if (shift < 32) 8988 { 8989 himask = 0xffff >> (32 - shift); 8990 lomask = (0xffff << shift) & 0xffffffff; 8991 } 8992 else 8993 { 8994 himask = 0xffff << (shift - 32); 8995 lomask = 0; 8996 } 8997 if ((hi32.X_add_number & ~(offsetT) himask) == 0 8998 && (lo32.X_add_number & ~(offsetT) lomask) == 0) 8999 { 9000 expressionS tmp; 9001 9002 tmp.X_op = O_constant; 9003 if (shift < 32) 9004 tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) 9005 | (lo32.X_add_number >> shift)); 9006 else 9007 tmp.X_add_number = hi32.X_add_number >> (shift - 32); 9008 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 9009 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9010 reg, reg, (shift >= 32) ? shift - 32 : shift); 9011 return; 9012 } 9013 ++shift; 9014 } 9015 while (shift <= (64 - 16)); 9016 9017 /* Find the bit number of the lowest one bit, and store the 9018 shifted value in hi/lo. */ 9019 hi = (unsigned long) (hi32.X_add_number & 0xffffffff); 9020 lo = (unsigned long) (lo32.X_add_number & 0xffffffff); 9021 if (lo != 0) 9022 { 9023 bit = 0; 9024 while ((lo & 1) == 0) 9025 { 9026 lo >>= 1; 9027 ++bit; 9028 } 9029 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); 9030 hi >>= bit; 9031 } 9032 else 9033 { 9034 bit = 32; 9035 while ((hi & 1) == 0) 9036 { 9037 hi >>= 1; 9038 ++bit; 9039 } 9040 lo = hi; 9041 hi = 0; 9042 } 9043 9044 /* Optimize if the shifted value is a (power of 2) - 1. */ 9045 if ((hi == 0 && ((lo + 1) & lo) == 0) 9046 || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) 9047 { 9048 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); 9049 if (shift != 0) 9050 { 9051 expressionS tmp; 9052 9053 /* This instruction will set the register to be all 9054 ones. */ 9055 tmp.X_op = O_constant; 9056 tmp.X_add_number = (offsetT) -1; 9057 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9058 if (bit != 0) 9059 { 9060 bit += shift; 9061 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9062 reg, reg, (bit >= 32) ? bit - 32 : bit); 9063 } 9064 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, 9065 reg, reg, (shift >= 32) ? shift - 32 : shift); 9066 return; 9067 } 9068 } 9069 9070 /* Sign extend hi32 before calling load_register, because we can 9071 generally get better code when we load a sign extended value. */ 9072 if ((hi32.X_add_number & 0x80000000) != 0) 9073 hi32.X_add_number |= ~(offsetT) 0xffffffff; 9074 load_register (reg, &hi32, 0); 9075 freg = reg; 9076 } 9077 if ((lo32.X_add_number & 0xffff0000) == 0) 9078 { 9079 if (freg != 0) 9080 { 9081 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); 9082 freg = reg; 9083 } 9084 } 9085 else 9086 { 9087 expressionS mid16; 9088 9089 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) 9090 { 9091 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9092 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); 9093 return; 9094 } 9095 9096 if (freg != 0) 9097 { 9098 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); 9099 freg = reg; 9100 } 9101 mid16 = lo32; 9102 mid16.X_add_number >>= 16; 9103 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9104 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9105 freg = reg; 9106 } 9107 if ((lo32.X_add_number & 0xffff) != 0) 9108 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9109 } 9110 9111 static inline void 9112 load_delay_nop (void) 9113 { 9114 if (!gpr_interlocks) 9115 macro_build (NULL, "nop", ""); 9116 } 9117 9118 /* Load an address into a register. */ 9119 9120 static void 9121 load_address (int reg, expressionS *ep, int *used_at) 9122 { 9123 if (ep->X_op != O_constant 9124 && ep->X_op != O_symbol) 9125 { 9126 as_bad (_("expression too complex")); 9127 ep->X_op = O_constant; 9128 } 9129 9130 if (ep->X_op == O_constant) 9131 { 9132 load_register (reg, ep, HAVE_64BIT_ADDRESSES); 9133 return; 9134 } 9135 9136 if (mips_pic == NO_PIC) 9137 { 9138 /* If this is a reference to a GP relative symbol, we want 9139 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 9140 Otherwise we want 9141 lui $reg,<sym> (BFD_RELOC_HI16_S) 9142 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9143 If we have an addend, we always use the latter form. 9144 9145 With 64bit address space and a usable $at we want 9146 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9147 lui $at,<sym> (BFD_RELOC_HI16_S) 9148 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9149 daddiu $at,<sym> (BFD_RELOC_LO16) 9150 dsll32 $reg,0 9151 daddu $reg,$reg,$at 9152 9153 If $at is already in use, we use a path which is suboptimal 9154 on superscalar processors. 9155 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9156 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9157 dsll $reg,16 9158 daddiu $reg,<sym> (BFD_RELOC_HI16_S) 9159 dsll $reg,16 9160 daddiu $reg,<sym> (BFD_RELOC_LO16) 9161 9162 For GP relative symbols in 64bit address space we can use 9163 the same sequence as in 32bit address space. */ 9164 if (HAVE_64BIT_SYMBOLS) 9165 { 9166 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9167 && !nopic_need_relax (ep->X_add_symbol, 1)) 9168 { 9169 relax_start (ep->X_add_symbol); 9170 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9171 mips_gp_register, BFD_RELOC_GPREL16); 9172 relax_switch (); 9173 } 9174 9175 if (*used_at == 0 && mips_opts.at) 9176 { 9177 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9178 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); 9179 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9180 BFD_RELOC_MIPS_HIGHER); 9181 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); 9182 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); 9183 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); 9184 *used_at = 1; 9185 } 9186 else 9187 { 9188 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9189 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9190 BFD_RELOC_MIPS_HIGHER); 9191 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9192 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); 9193 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9194 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); 9195 } 9196 9197 if (mips_relax.sequence) 9198 relax_end (); 9199 } 9200 else 9201 { 9202 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9203 && !nopic_need_relax (ep->X_add_symbol, 1)) 9204 { 9205 relax_start (ep->X_add_symbol); 9206 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9207 mips_gp_register, BFD_RELOC_GPREL16); 9208 relax_switch (); 9209 } 9210 macro_build_lui (ep, reg); 9211 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 9212 reg, reg, BFD_RELOC_LO16); 9213 if (mips_relax.sequence) 9214 relax_end (); 9215 } 9216 } 9217 else if (!mips_big_got) 9218 { 9219 expressionS ex; 9220 9221 /* If this is a reference to an external symbol, we want 9222 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9223 Otherwise we want 9224 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9225 nop 9226 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9227 If there is a constant, it must be added in after. 9228 9229 If we have NewABI, we want 9230 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) 9231 unless we're referencing a global symbol with a non-zero 9232 offset, in which case cst must be added separately. */ 9233 if (HAVE_NEWABI) 9234 { 9235 if (ep->X_add_number) 9236 { 9237 ex.X_add_number = ep->X_add_number; 9238 ep->X_add_number = 0; 9239 relax_start (ep->X_add_symbol); 9240 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9241 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9242 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9243 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9244 ex.X_op = O_constant; 9245 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9246 reg, reg, BFD_RELOC_LO16); 9247 ep->X_add_number = ex.X_add_number; 9248 relax_switch (); 9249 } 9250 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9251 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9252 if (mips_relax.sequence) 9253 relax_end (); 9254 } 9255 else 9256 { 9257 ex.X_add_number = ep->X_add_number; 9258 ep->X_add_number = 0; 9259 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9260 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9261 load_delay_nop (); 9262 relax_start (ep->X_add_symbol); 9263 relax_switch (); 9264 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9265 BFD_RELOC_LO16); 9266 relax_end (); 9267 9268 if (ex.X_add_number != 0) 9269 { 9270 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9271 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9272 ex.X_op = O_constant; 9273 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9274 reg, reg, BFD_RELOC_LO16); 9275 } 9276 } 9277 } 9278 else if (mips_big_got) 9279 { 9280 expressionS ex; 9281 9282 /* This is the large GOT case. If this is a reference to an 9283 external symbol, we want 9284 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 9285 addu $reg,$reg,$gp 9286 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) 9287 9288 Otherwise, for a reference to a local symbol in old ABI, we want 9289 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9290 nop 9291 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9292 If there is a constant, it must be added in after. 9293 9294 In the NewABI, for local symbols, with or without offsets, we want: 9295 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 9296 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 9297 */ 9298 if (HAVE_NEWABI) 9299 { 9300 ex.X_add_number = ep->X_add_number; 9301 ep->X_add_number = 0; 9302 relax_start (ep->X_add_symbol); 9303 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9304 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9305 reg, reg, mips_gp_register); 9306 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9307 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9308 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9309 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9310 else if (ex.X_add_number) 9311 { 9312 ex.X_op = O_constant; 9313 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9314 BFD_RELOC_LO16); 9315 } 9316 9317 ep->X_add_number = ex.X_add_number; 9318 relax_switch (); 9319 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9320 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 9321 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9322 BFD_RELOC_MIPS_GOT_OFST); 9323 relax_end (); 9324 } 9325 else 9326 { 9327 ex.X_add_number = ep->X_add_number; 9328 ep->X_add_number = 0; 9329 relax_start (ep->X_add_symbol); 9330 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9331 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9332 reg, reg, mips_gp_register); 9333 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9334 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9335 relax_switch (); 9336 if (reg_needs_delay (mips_gp_register)) 9337 { 9338 /* We need a nop before loading from $gp. This special 9339 check is required because the lui which starts the main 9340 instruction stream does not refer to $gp, and so will not 9341 insert the nop which may be required. */ 9342 macro_build (NULL, "nop", ""); 9343 } 9344 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9345 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9346 load_delay_nop (); 9347 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9348 BFD_RELOC_LO16); 9349 relax_end (); 9350 9351 if (ex.X_add_number != 0) 9352 { 9353 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9354 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9355 ex.X_op = O_constant; 9356 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9357 BFD_RELOC_LO16); 9358 } 9359 } 9360 } 9361 else 9362 abort (); 9363 9364 if (!mips_opts.at && *used_at == 1) 9365 as_bad (_("macro used $at after \".set noat\"")); 9366 } 9367 9368 /* Move the contents of register SOURCE into register DEST. */ 9369 9370 static void 9371 move_register (int dest, int source) 9372 { 9373 /* Prefer to use a 16-bit microMIPS instruction unless the previous 9374 instruction specifically requires a 32-bit one. */ 9375 if (mips_opts.micromips 9376 && !mips_opts.insn32 9377 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 9378 macro_build (NULL, "move", "mp,mj", dest, source); 9379 else 9380 macro_build (NULL, "or", "d,v,t", dest, source, 0); 9381 } 9382 9383 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where 9384 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. 9385 The two alternatives are: 9386 9387 Global symbol Local sybmol 9388 ------------- ------------ 9389 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) 9390 ... ... 9391 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) 9392 9393 load_got_offset emits the first instruction and add_got_offset 9394 emits the second for a 16-bit offset or add_got_offset_hilo emits 9395 a sequence to add a 32-bit offset using a scratch register. */ 9396 9397 static void 9398 load_got_offset (int dest, expressionS *local) 9399 { 9400 expressionS global; 9401 9402 global = *local; 9403 global.X_add_number = 0; 9404 9405 relax_start (local->X_add_symbol); 9406 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, 9407 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9408 relax_switch (); 9409 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, 9410 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9411 relax_end (); 9412 } 9413 9414 static void 9415 add_got_offset (int dest, expressionS *local) 9416 { 9417 expressionS global; 9418 9419 global.X_op = O_constant; 9420 global.X_op_symbol = NULL; 9421 global.X_add_symbol = NULL; 9422 global.X_add_number = local->X_add_number; 9423 9424 relax_start (local->X_add_symbol); 9425 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", 9426 dest, dest, BFD_RELOC_LO16); 9427 relax_switch (); 9428 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); 9429 relax_end (); 9430 } 9431 9432 static void 9433 add_got_offset_hilo (int dest, expressionS *local, int tmp) 9434 { 9435 expressionS global; 9436 int hold_mips_optimize; 9437 9438 global.X_op = O_constant; 9439 global.X_op_symbol = NULL; 9440 global.X_add_symbol = NULL; 9441 global.X_add_number = local->X_add_number; 9442 9443 relax_start (local->X_add_symbol); 9444 load_register (tmp, &global, HAVE_64BIT_ADDRESSES); 9445 relax_switch (); 9446 /* Set mips_optimize around the lui instruction to avoid 9447 inserting an unnecessary nop after the lw. */ 9448 hold_mips_optimize = mips_optimize; 9449 mips_optimize = 2; 9450 macro_build_lui (&global, tmp); 9451 mips_optimize = hold_mips_optimize; 9452 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); 9453 relax_end (); 9454 9455 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); 9456 } 9457 9458 /* Emit a sequence of instructions to emulate a branch likely operation. 9459 BR is an ordinary branch corresponding to one to be emulated. BRNEG 9460 is its complementing branch with the original condition negated. 9461 CALL is set if the original branch specified the link operation. 9462 EP, FMT, SREG and TREG specify the usual macro_build() parameters. 9463 9464 Code like this is produced in the noreorder mode: 9465 9466 BRNEG <args>, 1f 9467 nop 9468 b <sym> 9469 delay slot (executed only if branch taken) 9470 1: 9471 9472 or, if CALL is set: 9473 9474 BRNEG <args>, 1f 9475 nop 9476 bal <sym> 9477 delay slot (executed only if branch taken) 9478 1: 9479 9480 In the reorder mode the delay slot would be filled with a nop anyway, 9481 so code produced is simply: 9482 9483 BR <args>, <sym> 9484 nop 9485 9486 This function is used when producing code for the microMIPS ASE that 9487 does not implement branch likely instructions in hardware. */ 9488 9489 static void 9490 macro_build_branch_likely (const char *br, const char *brneg, 9491 int call, expressionS *ep, const char *fmt, 9492 unsigned int sreg, unsigned int treg) 9493 { 9494 int noreorder = mips_opts.noreorder; 9495 expressionS expr1; 9496 9497 gas_assert (mips_opts.micromips); 9498 start_noreorder (); 9499 if (noreorder) 9500 { 9501 micromips_label_expr (&expr1); 9502 macro_build (&expr1, brneg, fmt, sreg, treg); 9503 macro_build (NULL, "nop", ""); 9504 macro_build (ep, call ? "bal" : "b", "p"); 9505 9506 /* Set to true so that append_insn adds a label. */ 9507 emit_branch_likely_macro = TRUE; 9508 } 9509 else 9510 { 9511 macro_build (ep, br, fmt, sreg, treg); 9512 macro_build (NULL, "nop", ""); 9513 } 9514 end_noreorder (); 9515 } 9516 9517 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as 9518 the condition code tested. EP specifies the branch target. */ 9519 9520 static void 9521 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) 9522 { 9523 const int call = 0; 9524 const char *brneg; 9525 const char *br; 9526 9527 switch (type) 9528 { 9529 case M_BC1FL: 9530 br = "bc1f"; 9531 brneg = "bc1t"; 9532 break; 9533 case M_BC1TL: 9534 br = "bc1t"; 9535 brneg = "bc1f"; 9536 break; 9537 case M_BC2FL: 9538 br = "bc2f"; 9539 brneg = "bc2t"; 9540 break; 9541 case M_BC2TL: 9542 br = "bc2t"; 9543 brneg = "bc2f"; 9544 break; 9545 default: 9546 abort (); 9547 } 9548 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); 9549 } 9550 9551 /* Emit a two-argument branch macro specified by TYPE, using SREG as 9552 the register tested. EP specifies the branch target. */ 9553 9554 static void 9555 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) 9556 { 9557 const char *brneg = NULL; 9558 const char *br; 9559 int call = 0; 9560 9561 switch (type) 9562 { 9563 case M_BGEZ: 9564 br = "bgez"; 9565 break; 9566 case M_BGEZL: 9567 br = mips_opts.micromips ? "bgez" : "bgezl"; 9568 brneg = "bltz"; 9569 break; 9570 case M_BGEZALL: 9571 gas_assert (mips_opts.micromips); 9572 br = mips_opts.insn32 ? "bgezal" : "bgezals"; 9573 brneg = "bltz"; 9574 call = 1; 9575 break; 9576 case M_BGTZ: 9577 br = "bgtz"; 9578 break; 9579 case M_BGTZL: 9580 br = mips_opts.micromips ? "bgtz" : "bgtzl"; 9581 brneg = "blez"; 9582 break; 9583 case M_BLEZ: 9584 br = "blez"; 9585 break; 9586 case M_BLEZL: 9587 br = mips_opts.micromips ? "blez" : "blezl"; 9588 brneg = "bgtz"; 9589 break; 9590 case M_BLTZ: 9591 br = "bltz"; 9592 break; 9593 case M_BLTZL: 9594 br = mips_opts.micromips ? "bltz" : "bltzl"; 9595 brneg = "bgez"; 9596 break; 9597 case M_BLTZALL: 9598 gas_assert (mips_opts.micromips); 9599 br = mips_opts.insn32 ? "bltzal" : "bltzals"; 9600 brneg = "bgez"; 9601 call = 1; 9602 break; 9603 default: 9604 abort (); 9605 } 9606 if (mips_opts.micromips && brneg) 9607 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); 9608 else 9609 macro_build (ep, br, "s,p", sreg); 9610 } 9611 9612 /* Emit a three-argument branch macro specified by TYPE, using SREG and 9613 TREG as the registers tested. EP specifies the branch target. */ 9614 9615 static void 9616 macro_build_branch_rsrt (int type, expressionS *ep, 9617 unsigned int sreg, unsigned int treg) 9618 { 9619 const char *brneg = NULL; 9620 const int call = 0; 9621 const char *br; 9622 9623 switch (type) 9624 { 9625 case M_BEQ: 9626 case M_BEQ_I: 9627 br = "beq"; 9628 break; 9629 case M_BEQL: 9630 case M_BEQL_I: 9631 br = mips_opts.micromips ? "beq" : "beql"; 9632 brneg = "bne"; 9633 break; 9634 case M_BNE: 9635 case M_BNE_I: 9636 br = "bne"; 9637 break; 9638 case M_BNEL: 9639 case M_BNEL_I: 9640 br = mips_opts.micromips ? "bne" : "bnel"; 9641 brneg = "beq"; 9642 break; 9643 default: 9644 abort (); 9645 } 9646 if (mips_opts.micromips && brneg) 9647 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); 9648 else 9649 macro_build (ep, br, "s,t,p", sreg, treg); 9650 } 9651 9652 /* Return the high part that should be loaded in order to make the low 9653 part of VALUE accessible using an offset of OFFBITS bits. */ 9654 9655 static offsetT 9656 offset_high_part (offsetT value, unsigned int offbits) 9657 { 9658 offsetT bias; 9659 addressT low_mask; 9660 9661 if (offbits == 0) 9662 return value; 9663 bias = 1 << (offbits - 1); 9664 low_mask = bias * 2 - 1; 9665 return (value + bias) & ~low_mask; 9666 } 9667 9668 /* Return true if the value stored in offset_expr and offset_reloc 9669 fits into a signed offset of OFFBITS bits. RANGE is the maximum 9670 amount that the caller wants to add without inducing overflow 9671 and ALIGN is the known alignment of the value in bytes. */ 9672 9673 static bfd_boolean 9674 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) 9675 { 9676 if (offbits == 16) 9677 { 9678 /* Accept any relocation operator if overflow isn't a concern. */ 9679 if (range < align && *offset_reloc != BFD_RELOC_UNUSED) 9680 return TRUE; 9681 9682 /* These relocations are guaranteed not to overflow in correct links. */ 9683 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL 9684 || gprel16_reloc_p (*offset_reloc)) 9685 return TRUE; 9686 } 9687 if (offset_expr.X_op == O_constant 9688 && offset_high_part (offset_expr.X_add_number, offbits) == 0 9689 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) 9690 return TRUE; 9691 return FALSE; 9692 } 9693 9694 /* 9695 * Build macros 9696 * This routine implements the seemingly endless macro or synthesized 9697 * instructions and addressing modes in the mips assembly language. Many 9698 * of these macros are simple and are similar to each other. These could 9699 * probably be handled by some kind of table or grammar approach instead of 9700 * this verbose method. Others are not simple macros but are more like 9701 * optimizing code generation. 9702 * One interesting optimization is when several store macros appear 9703 * consecutively that would load AT with the upper half of the same address. 9704 * The ensuing load upper instructions are ommited. This implies some kind 9705 * of global optimization. We currently only optimize within a single macro. 9706 * For many of the load and store macros if the address is specified as a 9707 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we 9708 * first load register 'at' with zero and use it as the base register. The 9709 * mips assembler simply uses register $zero. Just one tiny optimization 9710 * we're missing. 9711 */ 9712 static void 9713 macro (struct mips_cl_insn *ip, char *str) 9714 { 9715 const struct mips_operand_array *operands; 9716 unsigned int breg, i; 9717 unsigned int tempreg; 9718 int mask; 9719 int used_at = 0; 9720 expressionS label_expr; 9721 expressionS expr1; 9722 expressionS *ep; 9723 const char *s; 9724 const char *s2; 9725 const char *fmt; 9726 int likely = 0; 9727 int coproc = 0; 9728 int offbits = 16; 9729 int call = 0; 9730 int jals = 0; 9731 int dbl = 0; 9732 int imm = 0; 9733 int ust = 0; 9734 int lp = 0; 9735 bfd_boolean large_offset; 9736 int off; 9737 int hold_mips_optimize; 9738 unsigned int align; 9739 unsigned int op[MAX_OPERANDS]; 9740 9741 gas_assert (! mips_opts.mips16); 9742 9743 operands = insn_operands (ip); 9744 for (i = 0; i < MAX_OPERANDS; i++) 9745 if (operands->operand[i]) 9746 op[i] = insn_extract_operand (ip, operands->operand[i]); 9747 else 9748 op[i] = -1; 9749 9750 mask = ip->insn_mo->mask; 9751 9752 label_expr.X_op = O_constant; 9753 label_expr.X_op_symbol = NULL; 9754 label_expr.X_add_symbol = NULL; 9755 label_expr.X_add_number = 0; 9756 9757 expr1.X_op = O_constant; 9758 expr1.X_op_symbol = NULL; 9759 expr1.X_add_symbol = NULL; 9760 expr1.X_add_number = 1; 9761 align = 1; 9762 9763 switch (mask) 9764 { 9765 case M_DABS: 9766 dbl = 1; 9767 case M_ABS: 9768 /* bgez $a0,1f 9769 move v0,$a0 9770 sub v0,$zero,$a0 9771 1: 9772 */ 9773 9774 start_noreorder (); 9775 9776 if (mips_opts.micromips) 9777 micromips_label_expr (&label_expr); 9778 else 9779 label_expr.X_add_number = 8; 9780 macro_build (&label_expr, "bgez", "s,p", op[1]); 9781 if (op[0] == op[1]) 9782 macro_build (NULL, "nop", ""); 9783 else 9784 move_register (op[0], op[1]); 9785 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); 9786 if (mips_opts.micromips) 9787 micromips_add_label (); 9788 9789 end_noreorder (); 9790 break; 9791 9792 case M_ADD_I: 9793 s = "addi"; 9794 s2 = "add"; 9795 goto do_addi; 9796 case M_ADDU_I: 9797 s = "addiu"; 9798 s2 = "addu"; 9799 goto do_addi; 9800 case M_DADD_I: 9801 dbl = 1; 9802 s = "daddi"; 9803 s2 = "dadd"; 9804 if (!mips_opts.micromips) 9805 goto do_addi; 9806 if (imm_expr.X_add_number >= -0x200 9807 && imm_expr.X_add_number < 0x200) 9808 { 9809 macro_build (NULL, s, "t,r,.", op[0], op[1], 9810 (int) imm_expr.X_add_number); 9811 break; 9812 } 9813 goto do_addi_i; 9814 case M_DADDU_I: 9815 dbl = 1; 9816 s = "daddiu"; 9817 s2 = "daddu"; 9818 do_addi: 9819 if (imm_expr.X_add_number >= -0x8000 9820 && imm_expr.X_add_number < 0x8000) 9821 { 9822 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 9823 break; 9824 } 9825 do_addi_i: 9826 used_at = 1; 9827 load_register (AT, &imm_expr, dbl); 9828 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 9829 break; 9830 9831 case M_AND_I: 9832 s = "andi"; 9833 s2 = "and"; 9834 goto do_bit; 9835 case M_OR_I: 9836 s = "ori"; 9837 s2 = "or"; 9838 goto do_bit; 9839 case M_NOR_I: 9840 s = ""; 9841 s2 = "nor"; 9842 goto do_bit; 9843 case M_XOR_I: 9844 s = "xori"; 9845 s2 = "xor"; 9846 do_bit: 9847 if (imm_expr.X_add_number >= 0 9848 && imm_expr.X_add_number < 0x10000) 9849 { 9850 if (mask != M_NOR_I) 9851 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); 9852 else 9853 { 9854 macro_build (&imm_expr, "ori", "t,r,i", 9855 op[0], op[1], BFD_RELOC_LO16); 9856 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); 9857 } 9858 break; 9859 } 9860 9861 used_at = 1; 9862 load_register (AT, &imm_expr, GPR_SIZE == 64); 9863 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 9864 break; 9865 9866 case M_BALIGN: 9867 switch (imm_expr.X_add_number) 9868 { 9869 case 0: 9870 macro_build (NULL, "nop", ""); 9871 break; 9872 case 2: 9873 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); 9874 break; 9875 case 1: 9876 case 3: 9877 macro_build (NULL, "balign", "t,s,2", op[0], op[1], 9878 (int) imm_expr.X_add_number); 9879 break; 9880 default: 9881 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), 9882 (unsigned long) imm_expr.X_add_number); 9883 break; 9884 } 9885 break; 9886 9887 case M_BC1FL: 9888 case M_BC1TL: 9889 case M_BC2FL: 9890 case M_BC2TL: 9891 gas_assert (mips_opts.micromips); 9892 macro_build_branch_ccl (mask, &offset_expr, 9893 EXTRACT_OPERAND (1, BCC, *ip)); 9894 break; 9895 9896 case M_BEQ_I: 9897 case M_BEQL_I: 9898 case M_BNE_I: 9899 case M_BNEL_I: 9900 if (imm_expr.X_add_number == 0) 9901 op[1] = 0; 9902 else 9903 { 9904 op[1] = AT; 9905 used_at = 1; 9906 load_register (op[1], &imm_expr, GPR_SIZE == 64); 9907 } 9908 /* Fall through. */ 9909 case M_BEQL: 9910 case M_BNEL: 9911 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); 9912 break; 9913 9914 case M_BGEL: 9915 likely = 1; 9916 case M_BGE: 9917 if (op[1] == 0) 9918 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); 9919 else if (op[0] == 0) 9920 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); 9921 else 9922 { 9923 used_at = 1; 9924 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 9925 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 9926 &offset_expr, AT, ZERO); 9927 } 9928 break; 9929 9930 case M_BGEZL: 9931 case M_BGEZALL: 9932 case M_BGTZL: 9933 case M_BLEZL: 9934 case M_BLTZL: 9935 case M_BLTZALL: 9936 macro_build_branch_rs (mask, &offset_expr, op[0]); 9937 break; 9938 9939 case M_BGTL_I: 9940 likely = 1; 9941 case M_BGT_I: 9942 /* Check for > max integer. */ 9943 if (imm_expr.X_add_number >= GPR_SMAX) 9944 { 9945 do_false: 9946 /* Result is always false. */ 9947 if (! likely) 9948 macro_build (NULL, "nop", ""); 9949 else 9950 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); 9951 break; 9952 } 9953 ++imm_expr.X_add_number; 9954 /* FALLTHROUGH */ 9955 case M_BGE_I: 9956 case M_BGEL_I: 9957 if (mask == M_BGEL_I) 9958 likely = 1; 9959 if (imm_expr.X_add_number == 0) 9960 { 9961 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, 9962 &offset_expr, op[0]); 9963 break; 9964 } 9965 if (imm_expr.X_add_number == 1) 9966 { 9967 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, 9968 &offset_expr, op[0]); 9969 break; 9970 } 9971 if (imm_expr.X_add_number <= GPR_SMIN) 9972 { 9973 do_true: 9974 /* result is always true */ 9975 as_warn (_("branch %s is always true"), ip->insn_mo->name); 9976 macro_build (&offset_expr, "b", "p"); 9977 break; 9978 } 9979 used_at = 1; 9980 set_at (op[0], 0); 9981 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 9982 &offset_expr, AT, ZERO); 9983 break; 9984 9985 case M_BGEUL: 9986 likely = 1; 9987 case M_BGEU: 9988 if (op[1] == 0) 9989 goto do_true; 9990 else if (op[0] == 0) 9991 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 9992 &offset_expr, ZERO, op[1]); 9993 else 9994 { 9995 used_at = 1; 9996 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 9997 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 9998 &offset_expr, AT, ZERO); 9999 } 10000 break; 10001 10002 case M_BGTUL_I: 10003 likely = 1; 10004 case M_BGTU_I: 10005 if (op[0] == 0 10006 || (GPR_SIZE == 32 10007 && imm_expr.X_add_number == -1)) 10008 goto do_false; 10009 ++imm_expr.X_add_number; 10010 /* FALLTHROUGH */ 10011 case M_BGEU_I: 10012 case M_BGEUL_I: 10013 if (mask == M_BGEUL_I) 10014 likely = 1; 10015 if (imm_expr.X_add_number == 0) 10016 goto do_true; 10017 else if (imm_expr.X_add_number == 1) 10018 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10019 &offset_expr, op[0], ZERO); 10020 else 10021 { 10022 used_at = 1; 10023 set_at (op[0], 1); 10024 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10025 &offset_expr, AT, ZERO); 10026 } 10027 break; 10028 10029 case M_BGTL: 10030 likely = 1; 10031 case M_BGT: 10032 if (op[1] == 0) 10033 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); 10034 else if (op[0] == 0) 10035 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); 10036 else 10037 { 10038 used_at = 1; 10039 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10040 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10041 &offset_expr, AT, ZERO); 10042 } 10043 break; 10044 10045 case M_BGTUL: 10046 likely = 1; 10047 case M_BGTU: 10048 if (op[1] == 0) 10049 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10050 &offset_expr, op[0], ZERO); 10051 else if (op[0] == 0) 10052 goto do_false; 10053 else 10054 { 10055 used_at = 1; 10056 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10057 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10058 &offset_expr, AT, ZERO); 10059 } 10060 break; 10061 10062 case M_BLEL: 10063 likely = 1; 10064 case M_BLE: 10065 if (op[1] == 0) 10066 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10067 else if (op[0] == 0) 10068 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); 10069 else 10070 { 10071 used_at = 1; 10072 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10073 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10074 &offset_expr, AT, ZERO); 10075 } 10076 break; 10077 10078 case M_BLEL_I: 10079 likely = 1; 10080 case M_BLE_I: 10081 if (imm_expr.X_add_number >= GPR_SMAX) 10082 goto do_true; 10083 ++imm_expr.X_add_number; 10084 /* FALLTHROUGH */ 10085 case M_BLT_I: 10086 case M_BLTL_I: 10087 if (mask == M_BLTL_I) 10088 likely = 1; 10089 if (imm_expr.X_add_number == 0) 10090 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10091 else if (imm_expr.X_add_number == 1) 10092 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10093 else 10094 { 10095 used_at = 1; 10096 set_at (op[0], 0); 10097 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10098 &offset_expr, AT, ZERO); 10099 } 10100 break; 10101 10102 case M_BLEUL: 10103 likely = 1; 10104 case M_BLEU: 10105 if (op[1] == 0) 10106 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10107 &offset_expr, op[0], ZERO); 10108 else if (op[0] == 0) 10109 goto do_true; 10110 else 10111 { 10112 used_at = 1; 10113 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10114 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10115 &offset_expr, AT, ZERO); 10116 } 10117 break; 10118 10119 case M_BLEUL_I: 10120 likely = 1; 10121 case M_BLEU_I: 10122 if (op[0] == 0 10123 || (GPR_SIZE == 32 10124 && imm_expr.X_add_number == -1)) 10125 goto do_true; 10126 ++imm_expr.X_add_number; 10127 /* FALLTHROUGH */ 10128 case M_BLTU_I: 10129 case M_BLTUL_I: 10130 if (mask == M_BLTUL_I) 10131 likely = 1; 10132 if (imm_expr.X_add_number == 0) 10133 goto do_false; 10134 else if (imm_expr.X_add_number == 1) 10135 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10136 &offset_expr, op[0], ZERO); 10137 else 10138 { 10139 used_at = 1; 10140 set_at (op[0], 1); 10141 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10142 &offset_expr, AT, ZERO); 10143 } 10144 break; 10145 10146 case M_BLTL: 10147 likely = 1; 10148 case M_BLT: 10149 if (op[1] == 0) 10150 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10151 else if (op[0] == 0) 10152 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); 10153 else 10154 { 10155 used_at = 1; 10156 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 10157 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10158 &offset_expr, AT, ZERO); 10159 } 10160 break; 10161 10162 case M_BLTUL: 10163 likely = 1; 10164 case M_BLTU: 10165 if (op[1] == 0) 10166 goto do_false; 10167 else if (op[0] == 0) 10168 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10169 &offset_expr, ZERO, op[1]); 10170 else 10171 { 10172 used_at = 1; 10173 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 10174 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10175 &offset_expr, AT, ZERO); 10176 } 10177 break; 10178 10179 case M_DDIV_3: 10180 dbl = 1; 10181 case M_DIV_3: 10182 s = "mflo"; 10183 goto do_div3; 10184 case M_DREM_3: 10185 dbl = 1; 10186 case M_REM_3: 10187 s = "mfhi"; 10188 do_div3: 10189 if (op[2] == 0) 10190 { 10191 as_warn (_("divide by zero")); 10192 if (mips_trap) 10193 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10194 else 10195 macro_build (NULL, "break", BRK_FMT, 7); 10196 break; 10197 } 10198 10199 start_noreorder (); 10200 if (mips_trap) 10201 { 10202 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 10203 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10204 } 10205 else 10206 { 10207 if (mips_opts.micromips) 10208 micromips_label_expr (&label_expr); 10209 else 10210 label_expr.X_add_number = 8; 10211 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 10212 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10213 macro_build (NULL, "break", BRK_FMT, 7); 10214 if (mips_opts.micromips) 10215 micromips_add_label (); 10216 } 10217 expr1.X_add_number = -1; 10218 used_at = 1; 10219 load_register (AT, &expr1, dbl); 10220 if (mips_opts.micromips) 10221 micromips_label_expr (&label_expr); 10222 else 10223 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); 10224 macro_build (&label_expr, "bne", "s,t,p", op[2], AT); 10225 if (dbl) 10226 { 10227 expr1.X_add_number = 1; 10228 load_register (AT, &expr1, dbl); 10229 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); 10230 } 10231 else 10232 { 10233 expr1.X_add_number = 0x80000000; 10234 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); 10235 } 10236 if (mips_trap) 10237 { 10238 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); 10239 /* We want to close the noreorder block as soon as possible, so 10240 that later insns are available for delay slot filling. */ 10241 end_noreorder (); 10242 } 10243 else 10244 { 10245 if (mips_opts.micromips) 10246 micromips_label_expr (&label_expr); 10247 else 10248 label_expr.X_add_number = 8; 10249 macro_build (&label_expr, "bne", "s,t,p", op[1], AT); 10250 macro_build (NULL, "nop", ""); 10251 10252 /* We want to close the noreorder block as soon as possible, so 10253 that later insns are available for delay slot filling. */ 10254 end_noreorder (); 10255 10256 macro_build (NULL, "break", BRK_FMT, 6); 10257 } 10258 if (mips_opts.micromips) 10259 micromips_add_label (); 10260 macro_build (NULL, s, MFHL_FMT, op[0]); 10261 break; 10262 10263 case M_DIV_3I: 10264 s = "div"; 10265 s2 = "mflo"; 10266 goto do_divi; 10267 case M_DIVU_3I: 10268 s = "divu"; 10269 s2 = "mflo"; 10270 goto do_divi; 10271 case M_REM_3I: 10272 s = "div"; 10273 s2 = "mfhi"; 10274 goto do_divi; 10275 case M_REMU_3I: 10276 s = "divu"; 10277 s2 = "mfhi"; 10278 goto do_divi; 10279 case M_DDIV_3I: 10280 dbl = 1; 10281 s = "ddiv"; 10282 s2 = "mflo"; 10283 goto do_divi; 10284 case M_DDIVU_3I: 10285 dbl = 1; 10286 s = "ddivu"; 10287 s2 = "mflo"; 10288 goto do_divi; 10289 case M_DREM_3I: 10290 dbl = 1; 10291 s = "ddiv"; 10292 s2 = "mfhi"; 10293 goto do_divi; 10294 case M_DREMU_3I: 10295 dbl = 1; 10296 s = "ddivu"; 10297 s2 = "mfhi"; 10298 do_divi: 10299 if (imm_expr.X_add_number == 0) 10300 { 10301 as_warn (_("divide by zero")); 10302 if (mips_trap) 10303 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10304 else 10305 macro_build (NULL, "break", BRK_FMT, 7); 10306 break; 10307 } 10308 if (imm_expr.X_add_number == 1) 10309 { 10310 if (strcmp (s2, "mflo") == 0) 10311 move_register (op[0], op[1]); 10312 else 10313 move_register (op[0], ZERO); 10314 break; 10315 } 10316 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') 10317 { 10318 if (strcmp (s2, "mflo") == 0) 10319 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); 10320 else 10321 move_register (op[0], ZERO); 10322 break; 10323 } 10324 10325 used_at = 1; 10326 load_register (AT, &imm_expr, dbl); 10327 macro_build (NULL, s, "z,s,t", op[1], AT); 10328 macro_build (NULL, s2, MFHL_FMT, op[0]); 10329 break; 10330 10331 case M_DIVU_3: 10332 s = "divu"; 10333 s2 = "mflo"; 10334 goto do_divu3; 10335 case M_REMU_3: 10336 s = "divu"; 10337 s2 = "mfhi"; 10338 goto do_divu3; 10339 case M_DDIVU_3: 10340 s = "ddivu"; 10341 s2 = "mflo"; 10342 goto do_divu3; 10343 case M_DREMU_3: 10344 s = "ddivu"; 10345 s2 = "mfhi"; 10346 do_divu3: 10347 start_noreorder (); 10348 if (mips_trap) 10349 { 10350 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 10351 macro_build (NULL, s, "z,s,t", op[1], op[2]); 10352 /* We want to close the noreorder block as soon as possible, so 10353 that later insns are available for delay slot filling. */ 10354 end_noreorder (); 10355 } 10356 else 10357 { 10358 if (mips_opts.micromips) 10359 micromips_label_expr (&label_expr); 10360 else 10361 label_expr.X_add_number = 8; 10362 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 10363 macro_build (NULL, s, "z,s,t", op[1], op[2]); 10364 10365 /* We want to close the noreorder block as soon as possible, so 10366 that later insns are available for delay slot filling. */ 10367 end_noreorder (); 10368 macro_build (NULL, "break", BRK_FMT, 7); 10369 if (mips_opts.micromips) 10370 micromips_add_label (); 10371 } 10372 macro_build (NULL, s2, MFHL_FMT, op[0]); 10373 break; 10374 10375 case M_DLCA_AB: 10376 dbl = 1; 10377 case M_LCA_AB: 10378 call = 1; 10379 goto do_la; 10380 case M_DLA_AB: 10381 dbl = 1; 10382 case M_LA_AB: 10383 do_la: 10384 /* Load the address of a symbol into a register. If breg is not 10385 zero, we then add a base register to it. */ 10386 10387 breg = op[2]; 10388 if (dbl && GPR_SIZE == 32) 10389 as_warn (_("dla used to load 32-bit register; recommend using la " 10390 "instead")); 10391 10392 if (!dbl && HAVE_64BIT_OBJECTS) 10393 as_warn (_("la used to load 64-bit address; recommend using dla " 10394 "instead")); 10395 10396 if (small_offset_p (0, align, 16)) 10397 { 10398 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, 10399 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); 10400 break; 10401 } 10402 10403 if (mips_opts.at && (op[0] == breg)) 10404 { 10405 tempreg = AT; 10406 used_at = 1; 10407 } 10408 else 10409 tempreg = op[0]; 10410 10411 if (offset_expr.X_op != O_symbol 10412 && offset_expr.X_op != O_constant) 10413 { 10414 as_bad (_("expression too complex")); 10415 offset_expr.X_op = O_constant; 10416 } 10417 10418 if (offset_expr.X_op == O_constant) 10419 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); 10420 else if (mips_pic == NO_PIC) 10421 { 10422 /* If this is a reference to a GP relative symbol, we want 10423 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 10424 Otherwise we want 10425 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 10426 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10427 If we have a constant, we need two instructions anyhow, 10428 so we may as well always use the latter form. 10429 10430 With 64bit address space and a usable $at we want 10431 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 10432 lui $at,<sym> (BFD_RELOC_HI16_S) 10433 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 10434 daddiu $at,<sym> (BFD_RELOC_LO16) 10435 dsll32 $tempreg,0 10436 daddu $tempreg,$tempreg,$at 10437 10438 If $at is already in use, we use a path which is suboptimal 10439 on superscalar processors. 10440 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 10441 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 10442 dsll $tempreg,16 10443 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 10444 dsll $tempreg,16 10445 daddiu $tempreg,<sym> (BFD_RELOC_LO16) 10446 10447 For GP relative symbols in 64bit address space we can use 10448 the same sequence as in 32bit address space. */ 10449 if (HAVE_64BIT_SYMBOLS) 10450 { 10451 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 10452 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 10453 { 10454 relax_start (offset_expr.X_add_symbol); 10455 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10456 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 10457 relax_switch (); 10458 } 10459 10460 if (used_at == 0 && mips_opts.at) 10461 { 10462 macro_build (&offset_expr, "lui", LUI_FMT, 10463 tempreg, BFD_RELOC_MIPS_HIGHEST); 10464 macro_build (&offset_expr, "lui", LUI_FMT, 10465 AT, BFD_RELOC_HI16_S); 10466 macro_build (&offset_expr, "daddiu", "t,r,j", 10467 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 10468 macro_build (&offset_expr, "daddiu", "t,r,j", 10469 AT, AT, BFD_RELOC_LO16); 10470 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 10471 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 10472 used_at = 1; 10473 } 10474 else 10475 { 10476 macro_build (&offset_expr, "lui", LUI_FMT, 10477 tempreg, BFD_RELOC_MIPS_HIGHEST); 10478 macro_build (&offset_expr, "daddiu", "t,r,j", 10479 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 10480 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 10481 macro_build (&offset_expr, "daddiu", "t,r,j", 10482 tempreg, tempreg, BFD_RELOC_HI16_S); 10483 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 10484 macro_build (&offset_expr, "daddiu", "t,r,j", 10485 tempreg, tempreg, BFD_RELOC_LO16); 10486 } 10487 10488 if (mips_relax.sequence) 10489 relax_end (); 10490 } 10491 else 10492 { 10493 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 10494 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 10495 { 10496 relax_start (offset_expr.X_add_symbol); 10497 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10498 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 10499 relax_switch (); 10500 } 10501 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 10502 as_bad (_("offset too large")); 10503 macro_build_lui (&offset_expr, tempreg); 10504 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10505 tempreg, tempreg, BFD_RELOC_LO16); 10506 if (mips_relax.sequence) 10507 relax_end (); 10508 } 10509 } 10510 else if (!mips_big_got && !HAVE_NEWABI) 10511 { 10512 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 10513 10514 /* If this is a reference to an external symbol, and there 10515 is no constant, we want 10516 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10517 or for lca or if tempreg is PIC_CALL_REG 10518 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 10519 For a local symbol, we want 10520 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10521 nop 10522 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10523 10524 If we have a small constant, and this is a reference to 10525 an external symbol, we want 10526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10527 nop 10528 addiu $tempreg,$tempreg,<constant> 10529 For a local symbol, we want the same instruction 10530 sequence, but we output a BFD_RELOC_LO16 reloc on the 10531 addiu instruction. 10532 10533 If we have a large constant, and this is a reference to 10534 an external symbol, we want 10535 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10536 lui $at,<hiconstant> 10537 addiu $at,$at,<loconstant> 10538 addu $tempreg,$tempreg,$at 10539 For a local symbol, we want the same instruction 10540 sequence, but we output a BFD_RELOC_LO16 reloc on the 10541 addiu instruction. 10542 */ 10543 10544 if (offset_expr.X_add_number == 0) 10545 { 10546 if (mips_pic == SVR4_PIC 10547 && breg == 0 10548 && (call || tempreg == PIC_CALL_REG)) 10549 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; 10550 10551 relax_start (offset_expr.X_add_symbol); 10552 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10553 lw_reloc_type, mips_gp_register); 10554 if (breg != 0) 10555 { 10556 /* We're going to put in an addu instruction using 10557 tempreg, so we may as well insert the nop right 10558 now. */ 10559 load_delay_nop (); 10560 } 10561 relax_switch (); 10562 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 10563 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); 10564 load_delay_nop (); 10565 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10566 tempreg, tempreg, BFD_RELOC_LO16); 10567 relax_end (); 10568 /* FIXME: If breg == 0, and the next instruction uses 10569 $tempreg, then if this variant case is used an extra 10570 nop will be generated. */ 10571 } 10572 else if (offset_expr.X_add_number >= -0x8000 10573 && offset_expr.X_add_number < 0x8000) 10574 { 10575 load_got_offset (tempreg, &offset_expr); 10576 load_delay_nop (); 10577 add_got_offset (tempreg, &offset_expr); 10578 } 10579 else 10580 { 10581 expr1.X_add_number = offset_expr.X_add_number; 10582 offset_expr.X_add_number = 10583 SEXT_16BIT (offset_expr.X_add_number); 10584 load_got_offset (tempreg, &offset_expr); 10585 offset_expr.X_add_number = expr1.X_add_number; 10586 /* If we are going to add in a base register, and the 10587 target register and the base register are the same, 10588 then we are using AT as a temporary register. Since 10589 we want to load the constant into AT, we add our 10590 current AT (from the global offset table) and the 10591 register into the register now, and pretend we were 10592 not using a base register. */ 10593 if (breg == op[0]) 10594 { 10595 load_delay_nop (); 10596 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10597 op[0], AT, breg); 10598 breg = 0; 10599 tempreg = op[0]; 10600 } 10601 add_got_offset_hilo (tempreg, &offset_expr, AT); 10602 used_at = 1; 10603 } 10604 } 10605 else if (!mips_big_got && HAVE_NEWABI) 10606 { 10607 int add_breg_early = 0; 10608 10609 /* If this is a reference to an external, and there is no 10610 constant, or local symbol (*), with or without a 10611 constant, we want 10612 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10613 or for lca or if tempreg is PIC_CALL_REG 10614 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 10615 10616 If we have a small constant, and this is a reference to 10617 an external symbol, we want 10618 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10619 addiu $tempreg,$tempreg,<constant> 10620 10621 If we have a large constant, and this is a reference to 10622 an external symbol, we want 10623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10624 lui $at,<hiconstant> 10625 addiu $at,$at,<loconstant> 10626 addu $tempreg,$tempreg,$at 10627 10628 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for 10629 local symbols, even though it introduces an additional 10630 instruction. */ 10631 10632 if (offset_expr.X_add_number) 10633 { 10634 expr1.X_add_number = offset_expr.X_add_number; 10635 offset_expr.X_add_number = 0; 10636 10637 relax_start (offset_expr.X_add_symbol); 10638 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10639 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10640 10641 if (expr1.X_add_number >= -0x8000 10642 && expr1.X_add_number < 0x8000) 10643 { 10644 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 10645 tempreg, tempreg, BFD_RELOC_LO16); 10646 } 10647 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 10648 { 10649 unsigned int dreg; 10650 10651 /* If we are going to add in a base register, and the 10652 target register and the base register are the same, 10653 then we are using AT as a temporary register. Since 10654 we want to load the constant into AT, we add our 10655 current AT (from the global offset table) and the 10656 register into the register now, and pretend we were 10657 not using a base register. */ 10658 if (breg != op[0]) 10659 dreg = tempreg; 10660 else 10661 { 10662 gas_assert (tempreg == AT); 10663 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10664 op[0], AT, breg); 10665 dreg = op[0]; 10666 add_breg_early = 1; 10667 } 10668 10669 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 10670 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10671 dreg, dreg, AT); 10672 10673 used_at = 1; 10674 } 10675 else 10676 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 10677 10678 relax_switch (); 10679 offset_expr.X_add_number = expr1.X_add_number; 10680 10681 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10682 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10683 if (add_breg_early) 10684 { 10685 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10686 op[0], tempreg, breg); 10687 breg = 0; 10688 tempreg = op[0]; 10689 } 10690 relax_end (); 10691 } 10692 else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 10693 { 10694 relax_start (offset_expr.X_add_symbol); 10695 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10696 BFD_RELOC_MIPS_CALL16, mips_gp_register); 10697 relax_switch (); 10698 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10699 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10700 relax_end (); 10701 } 10702 else 10703 { 10704 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10705 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10706 } 10707 } 10708 else if (mips_big_got && !HAVE_NEWABI) 10709 { 10710 int gpdelay; 10711 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 10712 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 10713 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 10714 10715 /* This is the large GOT case. If this is a reference to an 10716 external symbol, and there is no constant, we want 10717 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10718 addu $tempreg,$tempreg,$gp 10719 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10720 or for lca or if tempreg is PIC_CALL_REG 10721 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 10722 addu $tempreg,$tempreg,$gp 10723 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 10724 For a local symbol, we want 10725 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10726 nop 10727 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10728 10729 If we have a small constant, and this is a reference to 10730 an external symbol, we want 10731 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10732 addu $tempreg,$tempreg,$gp 10733 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10734 nop 10735 addiu $tempreg,$tempreg,<constant> 10736 For a local symbol, we want 10737 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10738 nop 10739 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) 10740 10741 If we have a large constant, and this is a reference to 10742 an external symbol, we want 10743 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10744 addu $tempreg,$tempreg,$gp 10745 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10746 lui $at,<hiconstant> 10747 addiu $at,$at,<loconstant> 10748 addu $tempreg,$tempreg,$at 10749 For a local symbol, we want 10750 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10751 lui $at,<hiconstant> 10752 addiu $at,$at,<loconstant> (BFD_RELOC_LO16) 10753 addu $tempreg,$tempreg,$at 10754 */ 10755 10756 expr1.X_add_number = offset_expr.X_add_number; 10757 offset_expr.X_add_number = 0; 10758 relax_start (offset_expr.X_add_symbol); 10759 gpdelay = reg_needs_delay (mips_gp_register); 10760 if (expr1.X_add_number == 0 && breg == 0 10761 && (call || tempreg == PIC_CALL_REG)) 10762 { 10763 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 10764 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 10765 } 10766 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 10767 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10768 tempreg, tempreg, mips_gp_register); 10769 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 10770 tempreg, lw_reloc_type, tempreg); 10771 if (expr1.X_add_number == 0) 10772 { 10773 if (breg != 0) 10774 { 10775 /* We're going to put in an addu instruction using 10776 tempreg, so we may as well insert the nop right 10777 now. */ 10778 load_delay_nop (); 10779 } 10780 } 10781 else if (expr1.X_add_number >= -0x8000 10782 && expr1.X_add_number < 0x8000) 10783 { 10784 load_delay_nop (); 10785 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 10786 tempreg, tempreg, BFD_RELOC_LO16); 10787 } 10788 else 10789 { 10790 unsigned int dreg; 10791 10792 /* If we are going to add in a base register, and the 10793 target register and the base register are the same, 10794 then we are using AT as a temporary register. Since 10795 we want to load the constant into AT, we add our 10796 current AT (from the global offset table) and the 10797 register into the register now, and pretend we were 10798 not using a base register. */ 10799 if (breg != op[0]) 10800 dreg = tempreg; 10801 else 10802 { 10803 gas_assert (tempreg == AT); 10804 load_delay_nop (); 10805 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10806 op[0], AT, breg); 10807 dreg = op[0]; 10808 } 10809 10810 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 10811 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 10812 10813 used_at = 1; 10814 } 10815 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); 10816 relax_switch (); 10817 10818 if (gpdelay) 10819 { 10820 /* This is needed because this instruction uses $gp, but 10821 the first instruction on the main stream does not. */ 10822 macro_build (NULL, "nop", ""); 10823 } 10824 10825 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10826 local_reloc_type, mips_gp_register); 10827 if (expr1.X_add_number >= -0x8000 10828 && expr1.X_add_number < 0x8000) 10829 { 10830 load_delay_nop (); 10831 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10832 tempreg, tempreg, BFD_RELOC_LO16); 10833 /* FIXME: If add_number is 0, and there was no base 10834 register, the external symbol case ended with a load, 10835 so if the symbol turns out to not be external, and 10836 the next instruction uses tempreg, an unnecessary nop 10837 will be inserted. */ 10838 } 10839 else 10840 { 10841 if (breg == op[0]) 10842 { 10843 /* We must add in the base register now, as in the 10844 external symbol case. */ 10845 gas_assert (tempreg == AT); 10846 load_delay_nop (); 10847 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10848 op[0], AT, breg); 10849 tempreg = op[0]; 10850 /* We set breg to 0 because we have arranged to add 10851 it in in both cases. */ 10852 breg = 0; 10853 } 10854 10855 macro_build_lui (&expr1, AT); 10856 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10857 AT, AT, BFD_RELOC_LO16); 10858 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10859 tempreg, tempreg, AT); 10860 used_at = 1; 10861 } 10862 relax_end (); 10863 } 10864 else if (mips_big_got && HAVE_NEWABI) 10865 { 10866 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 10867 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 10868 int add_breg_early = 0; 10869 10870 /* This is the large GOT case. If this is a reference to an 10871 external symbol, and there is no constant, we want 10872 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10873 add $tempreg,$tempreg,$gp 10874 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10875 or for lca or if tempreg is PIC_CALL_REG 10876 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 10877 add $tempreg,$tempreg,$gp 10878 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 10879 10880 If we have a small constant, and this is a reference to 10881 an external symbol, we want 10882 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10883 add $tempreg,$tempreg,$gp 10884 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10885 addi $tempreg,$tempreg,<constant> 10886 10887 If we have a large constant, and this is a reference to 10888 an external symbol, we want 10889 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10890 addu $tempreg,$tempreg,$gp 10891 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10892 lui $at,<hiconstant> 10893 addi $at,$at,<loconstant> 10894 add $tempreg,$tempreg,$at 10895 10896 If we have NewABI, and we know it's a local symbol, we want 10897 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 10898 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 10899 otherwise we have to resort to GOT_HI16/GOT_LO16. */ 10900 10901 relax_start (offset_expr.X_add_symbol); 10902 10903 expr1.X_add_number = offset_expr.X_add_number; 10904 offset_expr.X_add_number = 0; 10905 10906 if (expr1.X_add_number == 0 && breg == 0 10907 && (call || tempreg == PIC_CALL_REG)) 10908 { 10909 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 10910 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 10911 } 10912 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 10913 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10914 tempreg, tempreg, mips_gp_register); 10915 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 10916 tempreg, lw_reloc_type, tempreg); 10917 10918 if (expr1.X_add_number == 0) 10919 ; 10920 else if (expr1.X_add_number >= -0x8000 10921 && expr1.X_add_number < 0x8000) 10922 { 10923 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 10924 tempreg, tempreg, BFD_RELOC_LO16); 10925 } 10926 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 10927 { 10928 unsigned int dreg; 10929 10930 /* If we are going to add in a base register, and the 10931 target register and the base register are the same, 10932 then we are using AT as a temporary register. Since 10933 we want to load the constant into AT, we add our 10934 current AT (from the global offset table) and the 10935 register into the register now, and pretend we were 10936 not using a base register. */ 10937 if (breg != op[0]) 10938 dreg = tempreg; 10939 else 10940 { 10941 gas_assert (tempreg == AT); 10942 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10943 op[0], AT, breg); 10944 dreg = op[0]; 10945 add_breg_early = 1; 10946 } 10947 10948 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 10949 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 10950 10951 used_at = 1; 10952 } 10953 else 10954 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 10955 10956 relax_switch (); 10957 offset_expr.X_add_number = expr1.X_add_number; 10958 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10959 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 10960 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 10961 tempreg, BFD_RELOC_MIPS_GOT_OFST); 10962 if (add_breg_early) 10963 { 10964 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10965 op[0], tempreg, breg); 10966 breg = 0; 10967 tempreg = op[0]; 10968 } 10969 relax_end (); 10970 } 10971 else 10972 abort (); 10973 10974 if (breg != 0) 10975 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); 10976 break; 10977 10978 case M_MSGSND: 10979 gas_assert (!mips_opts.micromips); 10980 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); 10981 break; 10982 10983 case M_MSGLD: 10984 gas_assert (!mips_opts.micromips); 10985 macro_build (NULL, "c2", "C", 0x02); 10986 break; 10987 10988 case M_MSGLD_T: 10989 gas_assert (!mips_opts.micromips); 10990 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); 10991 break; 10992 10993 case M_MSGWAIT: 10994 gas_assert (!mips_opts.micromips); 10995 macro_build (NULL, "c2", "C", 3); 10996 break; 10997 10998 case M_MSGWAIT_T: 10999 gas_assert (!mips_opts.micromips); 11000 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); 11001 break; 11002 11003 case M_J_A: 11004 /* The j instruction may not be used in PIC code, since it 11005 requires an absolute address. We convert it to a b 11006 instruction. */ 11007 if (mips_pic == NO_PIC) 11008 macro_build (&offset_expr, "j", "a"); 11009 else 11010 macro_build (&offset_expr, "b", "p"); 11011 break; 11012 11013 /* The jal instructions must be handled as macros because when 11014 generating PIC code they expand to multi-instruction 11015 sequences. Normally they are simple instructions. */ 11016 case M_JALS_1: 11017 op[1] = op[0]; 11018 op[0] = RA; 11019 /* Fall through. */ 11020 case M_JALS_2: 11021 gas_assert (mips_opts.micromips); 11022 if (mips_opts.insn32) 11023 { 11024 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11025 break; 11026 } 11027 jals = 1; 11028 goto jal; 11029 case M_JAL_1: 11030 op[1] = op[0]; 11031 op[0] = RA; 11032 /* Fall through. */ 11033 case M_JAL_2: 11034 jal: 11035 if (mips_pic == NO_PIC) 11036 { 11037 s = jals ? "jalrs" : "jalr"; 11038 if (mips_opts.micromips 11039 && !mips_opts.insn32 11040 && op[0] == RA 11041 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11042 macro_build (NULL, s, "mj", op[1]); 11043 else 11044 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11045 } 11046 else 11047 { 11048 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI 11049 && mips_cprestore_offset >= 0); 11050 11051 if (op[1] != PIC_CALL_REG) 11052 as_warn (_("MIPS PIC call to register other than $25")); 11053 11054 s = ((mips_opts.micromips 11055 && !mips_opts.insn32 11056 && (!mips_opts.noreorder || cprestore)) 11057 ? "jalrs" : "jalr"); 11058 if (mips_opts.micromips 11059 && !mips_opts.insn32 11060 && op[0] == RA 11061 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11062 macro_build (NULL, s, "mj", op[1]); 11063 else 11064 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11065 if (mips_pic == SVR4_PIC && !HAVE_NEWABI) 11066 { 11067 if (mips_cprestore_offset < 0) 11068 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11069 else 11070 { 11071 if (!mips_frame_reg_valid) 11072 { 11073 as_warn (_("no .frame pseudo-op used in PIC code")); 11074 /* Quiet this warning. */ 11075 mips_frame_reg_valid = 1; 11076 } 11077 if (!mips_cprestore_valid) 11078 { 11079 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11080 /* Quiet this warning. */ 11081 mips_cprestore_valid = 1; 11082 } 11083 if (mips_opts.noreorder) 11084 macro_build (NULL, "nop", ""); 11085 expr1.X_add_number = mips_cprestore_offset; 11086 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11087 mips_gp_register, 11088 mips_frame_reg, 11089 HAVE_64BIT_ADDRESSES); 11090 } 11091 } 11092 } 11093 11094 break; 11095 11096 case M_JALS_A: 11097 gas_assert (mips_opts.micromips); 11098 if (mips_opts.insn32) 11099 { 11100 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11101 break; 11102 } 11103 jals = 1; 11104 /* Fall through. */ 11105 case M_JAL_A: 11106 if (mips_pic == NO_PIC) 11107 macro_build (&offset_expr, jals ? "jals" : "jal", "a"); 11108 else if (mips_pic == SVR4_PIC) 11109 { 11110 /* If this is a reference to an external symbol, and we are 11111 using a small GOT, we want 11112 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 11113 nop 11114 jalr $ra,$25 11115 nop 11116 lw $gp,cprestore($sp) 11117 The cprestore value is set using the .cprestore 11118 pseudo-op. If we are using a big GOT, we want 11119 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) 11120 addu $25,$25,$gp 11121 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) 11122 nop 11123 jalr $ra,$25 11124 nop 11125 lw $gp,cprestore($sp) 11126 If the symbol is not external, we want 11127 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11128 nop 11129 addiu $25,$25,<sym> (BFD_RELOC_LO16) 11130 jalr $ra,$25 11131 nop 11132 lw $gp,cprestore($sp) 11133 11134 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 11135 sequences above, minus nops, unless the symbol is local, 11136 which enables us to use GOT_PAGE/GOT_OFST (big got) or 11137 GOT_DISP. */ 11138 if (HAVE_NEWABI) 11139 { 11140 if (!mips_big_got) 11141 { 11142 relax_start (offset_expr.X_add_symbol); 11143 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11144 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11145 mips_gp_register); 11146 relax_switch (); 11147 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11148 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, 11149 mips_gp_register); 11150 relax_end (); 11151 } 11152 else 11153 { 11154 relax_start (offset_expr.X_add_symbol); 11155 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11156 BFD_RELOC_MIPS_CALL_HI16); 11157 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11158 PIC_CALL_REG, mips_gp_register); 11159 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11160 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11161 PIC_CALL_REG); 11162 relax_switch (); 11163 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11164 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, 11165 mips_gp_register); 11166 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11167 PIC_CALL_REG, PIC_CALL_REG, 11168 BFD_RELOC_MIPS_GOT_OFST); 11169 relax_end (); 11170 } 11171 11172 macro_build_jalr (&offset_expr, 0); 11173 } 11174 else 11175 { 11176 relax_start (offset_expr.X_add_symbol); 11177 if (!mips_big_got) 11178 { 11179 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11180 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11181 mips_gp_register); 11182 load_delay_nop (); 11183 relax_switch (); 11184 } 11185 else 11186 { 11187 int gpdelay; 11188 11189 gpdelay = reg_needs_delay (mips_gp_register); 11190 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11191 BFD_RELOC_MIPS_CALL_HI16); 11192 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11193 PIC_CALL_REG, mips_gp_register); 11194 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11195 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11196 PIC_CALL_REG); 11197 load_delay_nop (); 11198 relax_switch (); 11199 if (gpdelay) 11200 macro_build (NULL, "nop", ""); 11201 } 11202 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11203 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, 11204 mips_gp_register); 11205 load_delay_nop (); 11206 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11207 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); 11208 relax_end (); 11209 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); 11210 11211 if (mips_cprestore_offset < 0) 11212 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11213 else 11214 { 11215 if (!mips_frame_reg_valid) 11216 { 11217 as_warn (_("no .frame pseudo-op used in PIC code")); 11218 /* Quiet this warning. */ 11219 mips_frame_reg_valid = 1; 11220 } 11221 if (!mips_cprestore_valid) 11222 { 11223 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11224 /* Quiet this warning. */ 11225 mips_cprestore_valid = 1; 11226 } 11227 if (mips_opts.noreorder) 11228 macro_build (NULL, "nop", ""); 11229 expr1.X_add_number = mips_cprestore_offset; 11230 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11231 mips_gp_register, 11232 mips_frame_reg, 11233 HAVE_64BIT_ADDRESSES); 11234 } 11235 } 11236 } 11237 else if (mips_pic == VXWORKS_PIC) 11238 as_bad (_("non-PIC jump used in PIC library")); 11239 else 11240 abort (); 11241 11242 break; 11243 11244 case M_LBUE_AB: 11245 s = "lbue"; 11246 fmt = "t,+j(b)"; 11247 offbits = 9; 11248 goto ld_st; 11249 case M_LHUE_AB: 11250 s = "lhue"; 11251 fmt = "t,+j(b)"; 11252 offbits = 9; 11253 goto ld_st; 11254 case M_LBE_AB: 11255 s = "lbe"; 11256 fmt = "t,+j(b)"; 11257 offbits = 9; 11258 goto ld_st; 11259 case M_LHE_AB: 11260 s = "lhe"; 11261 fmt = "t,+j(b)"; 11262 offbits = 9; 11263 goto ld_st; 11264 case M_LLE_AB: 11265 s = "lle"; 11266 fmt = "t,+j(b)"; 11267 offbits = 9; 11268 goto ld_st; 11269 case M_LWE_AB: 11270 s = "lwe"; 11271 fmt = "t,+j(b)"; 11272 offbits = 9; 11273 goto ld_st; 11274 case M_LWLE_AB: 11275 s = "lwle"; 11276 fmt = "t,+j(b)"; 11277 offbits = 9; 11278 goto ld_st; 11279 case M_LWRE_AB: 11280 s = "lwre"; 11281 fmt = "t,+j(b)"; 11282 offbits = 9; 11283 goto ld_st; 11284 case M_SBE_AB: 11285 s = "sbe"; 11286 fmt = "t,+j(b)"; 11287 offbits = 9; 11288 goto ld_st; 11289 case M_SCE_AB: 11290 s = "sce"; 11291 fmt = "t,+j(b)"; 11292 offbits = 9; 11293 goto ld_st; 11294 case M_SHE_AB: 11295 s = "she"; 11296 fmt = "t,+j(b)"; 11297 offbits = 9; 11298 goto ld_st; 11299 case M_SWE_AB: 11300 s = "swe"; 11301 fmt = "t,+j(b)"; 11302 offbits = 9; 11303 goto ld_st; 11304 case M_SWLE_AB: 11305 s = "swle"; 11306 fmt = "t,+j(b)"; 11307 offbits = 9; 11308 goto ld_st; 11309 case M_SWRE_AB: 11310 s = "swre"; 11311 fmt = "t,+j(b)"; 11312 offbits = 9; 11313 goto ld_st; 11314 case M_ACLR_AB: 11315 s = "aclr"; 11316 fmt = "\\,~(b)"; 11317 offbits = 12; 11318 goto ld_st; 11319 case M_ASET_AB: 11320 s = "aset"; 11321 fmt = "\\,~(b)"; 11322 offbits = 12; 11323 goto ld_st; 11324 case M_LB_AB: 11325 s = "lb"; 11326 fmt = "t,o(b)"; 11327 goto ld; 11328 case M_LBU_AB: 11329 s = "lbu"; 11330 fmt = "t,o(b)"; 11331 goto ld; 11332 case M_LH_AB: 11333 s = "lh"; 11334 fmt = "t,o(b)"; 11335 goto ld; 11336 case M_LHU_AB: 11337 s = "lhu"; 11338 fmt = "t,o(b)"; 11339 goto ld; 11340 case M_LW_AB: 11341 s = "lw"; 11342 fmt = "t,o(b)"; 11343 goto ld; 11344 case M_LWC0_AB: 11345 gas_assert (!mips_opts.micromips); 11346 s = "lwc0"; 11347 fmt = "E,o(b)"; 11348 /* Itbl support may require additional care here. */ 11349 coproc = 1; 11350 goto ld_st; 11351 case M_LWC1_AB: 11352 s = "lwc1"; 11353 fmt = "T,o(b)"; 11354 /* Itbl support may require additional care here. */ 11355 coproc = 1; 11356 goto ld_st; 11357 case M_LWC2_AB: 11358 s = "lwc2"; 11359 fmt = COP12_FMT; 11360 offbits = (mips_opts.micromips ? 12 11361 : ISA_IS_R6 (mips_opts.isa) ? 11 11362 : 16); 11363 /* Itbl support may require additional care here. */ 11364 coproc = 1; 11365 goto ld_st; 11366 case M_LWC3_AB: 11367 gas_assert (!mips_opts.micromips); 11368 s = "lwc3"; 11369 fmt = "E,o(b)"; 11370 /* Itbl support may require additional care here. */ 11371 coproc = 1; 11372 goto ld_st; 11373 case M_LWL_AB: 11374 s = "lwl"; 11375 fmt = MEM12_FMT; 11376 offbits = (mips_opts.micromips ? 12 : 16); 11377 goto ld_st; 11378 case M_LWR_AB: 11379 s = "lwr"; 11380 fmt = MEM12_FMT; 11381 offbits = (mips_opts.micromips ? 12 : 16); 11382 goto ld_st; 11383 case M_LDC1_AB: 11384 s = "ldc1"; 11385 fmt = "T,o(b)"; 11386 /* Itbl support may require additional care here. */ 11387 coproc = 1; 11388 goto ld_st; 11389 case M_LDC2_AB: 11390 s = "ldc2"; 11391 fmt = COP12_FMT; 11392 offbits = (mips_opts.micromips ? 12 11393 : ISA_IS_R6 (mips_opts.isa) ? 11 11394 : 16); 11395 /* Itbl support may require additional care here. */ 11396 coproc = 1; 11397 goto ld_st; 11398 case M_LQC2_AB: 11399 s = "lqc2"; 11400 fmt = "+7,o(b)"; 11401 /* Itbl support may require additional care here. */ 11402 coproc = 1; 11403 goto ld_st; 11404 case M_LDC3_AB: 11405 s = "ldc3"; 11406 fmt = "E,o(b)"; 11407 /* Itbl support may require additional care here. */ 11408 coproc = 1; 11409 goto ld_st; 11410 case M_LDL_AB: 11411 s = "ldl"; 11412 fmt = MEM12_FMT; 11413 offbits = (mips_opts.micromips ? 12 : 16); 11414 goto ld_st; 11415 case M_LDR_AB: 11416 s = "ldr"; 11417 fmt = MEM12_FMT; 11418 offbits = (mips_opts.micromips ? 12 : 16); 11419 goto ld_st; 11420 case M_LL_AB: 11421 s = "ll"; 11422 fmt = LL_SC_FMT; 11423 offbits = (mips_opts.micromips ? 12 11424 : ISA_IS_R6 (mips_opts.isa) ? 9 11425 : 16); 11426 goto ld; 11427 case M_LLD_AB: 11428 s = "lld"; 11429 fmt = LL_SC_FMT; 11430 offbits = (mips_opts.micromips ? 12 11431 : ISA_IS_R6 (mips_opts.isa) ? 9 11432 : 16); 11433 goto ld; 11434 case M_LWU_AB: 11435 s = "lwu"; 11436 fmt = MEM12_FMT; 11437 offbits = (mips_opts.micromips ? 12 : 16); 11438 goto ld; 11439 case M_LWP_AB: 11440 gas_assert (mips_opts.micromips); 11441 s = "lwp"; 11442 fmt = "t,~(b)"; 11443 offbits = 12; 11444 lp = 1; 11445 goto ld; 11446 case M_LDP_AB: 11447 gas_assert (mips_opts.micromips); 11448 s = "ldp"; 11449 fmt = "t,~(b)"; 11450 offbits = 12; 11451 lp = 1; 11452 goto ld; 11453 case M_LWM_AB: 11454 gas_assert (mips_opts.micromips); 11455 s = "lwm"; 11456 fmt = "n,~(b)"; 11457 offbits = 12; 11458 goto ld_st; 11459 case M_LDM_AB: 11460 gas_assert (mips_opts.micromips); 11461 s = "ldm"; 11462 fmt = "n,~(b)"; 11463 offbits = 12; 11464 goto ld_st; 11465 11466 ld: 11467 /* We don't want to use $0 as tempreg. */ 11468 if (op[2] == op[0] + lp || op[0] + lp == ZERO) 11469 goto ld_st; 11470 else 11471 tempreg = op[0] + lp; 11472 goto ld_noat; 11473 11474 case M_SB_AB: 11475 s = "sb"; 11476 fmt = "t,o(b)"; 11477 goto ld_st; 11478 case M_SH_AB: 11479 s = "sh"; 11480 fmt = "t,o(b)"; 11481 goto ld_st; 11482 case M_SW_AB: 11483 s = "sw"; 11484 fmt = "t,o(b)"; 11485 goto ld_st; 11486 case M_SWC0_AB: 11487 gas_assert (!mips_opts.micromips); 11488 s = "swc0"; 11489 fmt = "E,o(b)"; 11490 /* Itbl support may require additional care here. */ 11491 coproc = 1; 11492 goto ld_st; 11493 case M_SWC1_AB: 11494 s = "swc1"; 11495 fmt = "T,o(b)"; 11496 /* Itbl support may require additional care here. */ 11497 coproc = 1; 11498 goto ld_st; 11499 case M_SWC2_AB: 11500 s = "swc2"; 11501 fmt = COP12_FMT; 11502 offbits = (mips_opts.micromips ? 12 11503 : ISA_IS_R6 (mips_opts.isa) ? 11 11504 : 16); 11505 /* Itbl support may require additional care here. */ 11506 coproc = 1; 11507 goto ld_st; 11508 case M_SWC3_AB: 11509 gas_assert (!mips_opts.micromips); 11510 s = "swc3"; 11511 fmt = "E,o(b)"; 11512 /* Itbl support may require additional care here. */ 11513 coproc = 1; 11514 goto ld_st; 11515 case M_SWL_AB: 11516 s = "swl"; 11517 fmt = MEM12_FMT; 11518 offbits = (mips_opts.micromips ? 12 : 16); 11519 goto ld_st; 11520 case M_SWR_AB: 11521 s = "swr"; 11522 fmt = MEM12_FMT; 11523 offbits = (mips_opts.micromips ? 12 : 16); 11524 goto ld_st; 11525 case M_SC_AB: 11526 s = "sc"; 11527 fmt = LL_SC_FMT; 11528 offbits = (mips_opts.micromips ? 12 11529 : ISA_IS_R6 (mips_opts.isa) ? 9 11530 : 16); 11531 goto ld_st; 11532 case M_SCD_AB: 11533 s = "scd"; 11534 fmt = LL_SC_FMT; 11535 offbits = (mips_opts.micromips ? 12 11536 : ISA_IS_R6 (mips_opts.isa) ? 9 11537 : 16); 11538 goto ld_st; 11539 case M_CACHE_AB: 11540 s = "cache"; 11541 fmt = (mips_opts.micromips ? "k,~(b)" 11542 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 11543 : "k,o(b)"); 11544 offbits = (mips_opts.micromips ? 12 11545 : ISA_IS_R6 (mips_opts.isa) ? 9 11546 : 16); 11547 goto ld_st; 11548 case M_CACHEE_AB: 11549 s = "cachee"; 11550 fmt = "k,+j(b)"; 11551 offbits = 9; 11552 goto ld_st; 11553 case M_PREF_AB: 11554 s = "pref"; 11555 fmt = (mips_opts.micromips ? "k,~(b)" 11556 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 11557 : "k,o(b)"); 11558 offbits = (mips_opts.micromips ? 12 11559 : ISA_IS_R6 (mips_opts.isa) ? 9 11560 : 16); 11561 goto ld_st; 11562 case M_PREFE_AB: 11563 s = "prefe"; 11564 fmt = "k,+j(b)"; 11565 offbits = 9; 11566 goto ld_st; 11567 case M_SDC1_AB: 11568 s = "sdc1"; 11569 fmt = "T,o(b)"; 11570 coproc = 1; 11571 /* Itbl support may require additional care here. */ 11572 goto ld_st; 11573 case M_SDC2_AB: 11574 s = "sdc2"; 11575 fmt = COP12_FMT; 11576 offbits = (mips_opts.micromips ? 12 11577 : ISA_IS_R6 (mips_opts.isa) ? 11 11578 : 16); 11579 /* Itbl support may require additional care here. */ 11580 coproc = 1; 11581 goto ld_st; 11582 case M_SQC2_AB: 11583 s = "sqc2"; 11584 fmt = "+7,o(b)"; 11585 /* Itbl support may require additional care here. */ 11586 coproc = 1; 11587 goto ld_st; 11588 case M_SDC3_AB: 11589 gas_assert (!mips_opts.micromips); 11590 s = "sdc3"; 11591 fmt = "E,o(b)"; 11592 /* Itbl support may require additional care here. */ 11593 coproc = 1; 11594 goto ld_st; 11595 case M_SDL_AB: 11596 s = "sdl"; 11597 fmt = MEM12_FMT; 11598 offbits = (mips_opts.micromips ? 12 : 16); 11599 goto ld_st; 11600 case M_SDR_AB: 11601 s = "sdr"; 11602 fmt = MEM12_FMT; 11603 offbits = (mips_opts.micromips ? 12 : 16); 11604 goto ld_st; 11605 case M_SWP_AB: 11606 gas_assert (mips_opts.micromips); 11607 s = "swp"; 11608 fmt = "t,~(b)"; 11609 offbits = 12; 11610 goto ld_st; 11611 case M_SDP_AB: 11612 gas_assert (mips_opts.micromips); 11613 s = "sdp"; 11614 fmt = "t,~(b)"; 11615 offbits = 12; 11616 goto ld_st; 11617 case M_SWM_AB: 11618 gas_assert (mips_opts.micromips); 11619 s = "swm"; 11620 fmt = "n,~(b)"; 11621 offbits = 12; 11622 goto ld_st; 11623 case M_SDM_AB: 11624 gas_assert (mips_opts.micromips); 11625 s = "sdm"; 11626 fmt = "n,~(b)"; 11627 offbits = 12; 11628 11629 ld_st: 11630 tempreg = AT; 11631 ld_noat: 11632 breg = op[2]; 11633 if (small_offset_p (0, align, 16)) 11634 { 11635 /* The first case exists for M_LD_AB and M_SD_AB, which are 11636 macros for o32 but which should act like normal instructions 11637 otherwise. */ 11638 if (offbits == 16) 11639 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], 11640 offset_reloc[1], offset_reloc[2], breg); 11641 else if (small_offset_p (0, align, offbits)) 11642 { 11643 if (offbits == 0) 11644 macro_build (NULL, s, fmt, op[0], breg); 11645 else 11646 macro_build (NULL, s, fmt, op[0], 11647 (int) offset_expr.X_add_number, breg); 11648 } 11649 else 11650 { 11651 if (tempreg == AT) 11652 used_at = 1; 11653 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11654 tempreg, breg, -1, offset_reloc[0], 11655 offset_reloc[1], offset_reloc[2]); 11656 if (offbits == 0) 11657 macro_build (NULL, s, fmt, op[0], tempreg); 11658 else 11659 macro_build (NULL, s, fmt, op[0], 0, tempreg); 11660 } 11661 break; 11662 } 11663 11664 if (tempreg == AT) 11665 used_at = 1; 11666 11667 if (offset_expr.X_op != O_constant 11668 && offset_expr.X_op != O_symbol) 11669 { 11670 as_bad (_("expression too complex")); 11671 offset_expr.X_op = O_constant; 11672 } 11673 11674 if (HAVE_32BIT_ADDRESSES 11675 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 11676 { 11677 char value [32]; 11678 11679 sprintf_vma (value, offset_expr.X_add_number); 11680 as_bad (_("number (0x%s) larger than 32 bits"), value); 11681 } 11682 11683 /* A constant expression in PIC code can be handled just as it 11684 is in non PIC code. */ 11685 if (offset_expr.X_op == O_constant) 11686 { 11687 expr1.X_add_number = offset_high_part (offset_expr.X_add_number, 11688 offbits == 0 ? 16 : offbits); 11689 offset_expr.X_add_number -= expr1.X_add_number; 11690 11691 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); 11692 if (breg != 0) 11693 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11694 tempreg, tempreg, breg); 11695 if (offbits == 0) 11696 { 11697 if (offset_expr.X_add_number != 0) 11698 macro_build (&offset_expr, ADDRESS_ADDI_INSN, 11699 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); 11700 macro_build (NULL, s, fmt, op[0], tempreg); 11701 } 11702 else if (offbits == 16) 11703 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 11704 else 11705 macro_build (NULL, s, fmt, op[0], 11706 (int) offset_expr.X_add_number, tempreg); 11707 } 11708 else if (offbits != 16) 11709 { 11710 /* The offset field is too narrow to be used for a low-part 11711 relocation, so load the whole address into the auxillary 11712 register. */ 11713 load_address (tempreg, &offset_expr, &used_at); 11714 if (breg != 0) 11715 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11716 tempreg, tempreg, breg); 11717 if (offbits == 0) 11718 macro_build (NULL, s, fmt, op[0], tempreg); 11719 else 11720 macro_build (NULL, s, fmt, op[0], 0, tempreg); 11721 } 11722 else if (mips_pic == NO_PIC) 11723 { 11724 /* If this is a reference to a GP relative symbol, and there 11725 is no base register, we want 11726 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 11727 Otherwise, if there is no base register, we want 11728 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 11729 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11730 If we have a constant, we need two instructions anyhow, 11731 so we always use the latter form. 11732 11733 If we have a base register, and this is a reference to a 11734 GP relative symbol, we want 11735 addu $tempreg,$breg,$gp 11736 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) 11737 Otherwise we want 11738 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 11739 addu $tempreg,$tempreg,$breg 11740 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11741 With a constant we always use the latter case. 11742 11743 With 64bit address space and no base register and $at usable, 11744 we want 11745 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11746 lui $at,<sym> (BFD_RELOC_HI16_S) 11747 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11748 dsll32 $tempreg,0 11749 daddu $tempreg,$at 11750 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11751 If we have a base register, we want 11752 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11753 lui $at,<sym> (BFD_RELOC_HI16_S) 11754 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11755 daddu $at,$breg 11756 dsll32 $tempreg,0 11757 daddu $tempreg,$at 11758 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11759 11760 Without $at we can't generate the optimal path for superscalar 11761 processors here since this would require two temporary registers. 11762 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11763 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11764 dsll $tempreg,16 11765 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 11766 dsll $tempreg,16 11767 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11768 If we have a base register, we want 11769 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11770 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11771 dsll $tempreg,16 11772 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 11773 dsll $tempreg,16 11774 daddu $tempreg,$tempreg,$breg 11775 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11776 11777 For GP relative symbols in 64bit address space we can use 11778 the same sequence as in 32bit address space. */ 11779 if (HAVE_64BIT_SYMBOLS) 11780 { 11781 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11782 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11783 { 11784 relax_start (offset_expr.X_add_symbol); 11785 if (breg == 0) 11786 { 11787 macro_build (&offset_expr, s, fmt, op[0], 11788 BFD_RELOC_GPREL16, mips_gp_register); 11789 } 11790 else 11791 { 11792 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11793 tempreg, breg, mips_gp_register); 11794 macro_build (&offset_expr, s, fmt, op[0], 11795 BFD_RELOC_GPREL16, tempreg); 11796 } 11797 relax_switch (); 11798 } 11799 11800 if (used_at == 0 && mips_opts.at) 11801 { 11802 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11803 BFD_RELOC_MIPS_HIGHEST); 11804 macro_build (&offset_expr, "lui", LUI_FMT, AT, 11805 BFD_RELOC_HI16_S); 11806 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11807 tempreg, BFD_RELOC_MIPS_HIGHER); 11808 if (breg != 0) 11809 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); 11810 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 11811 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 11812 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, 11813 tempreg); 11814 used_at = 1; 11815 } 11816 else 11817 { 11818 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11819 BFD_RELOC_MIPS_HIGHEST); 11820 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11821 tempreg, BFD_RELOC_MIPS_HIGHER); 11822 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11823 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11824 tempreg, BFD_RELOC_HI16_S); 11825 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11826 if (breg != 0) 11827 macro_build (NULL, "daddu", "d,v,t", 11828 tempreg, tempreg, breg); 11829 macro_build (&offset_expr, s, fmt, op[0], 11830 BFD_RELOC_LO16, tempreg); 11831 } 11832 11833 if (mips_relax.sequence) 11834 relax_end (); 11835 break; 11836 } 11837 11838 if (breg == 0) 11839 { 11840 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11841 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11842 { 11843 relax_start (offset_expr.X_add_symbol); 11844 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, 11845 mips_gp_register); 11846 relax_switch (); 11847 } 11848 macro_build_lui (&offset_expr, tempreg); 11849 macro_build (&offset_expr, s, fmt, op[0], 11850 BFD_RELOC_LO16, tempreg); 11851 if (mips_relax.sequence) 11852 relax_end (); 11853 } 11854 else 11855 { 11856 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11857 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11858 { 11859 relax_start (offset_expr.X_add_symbol); 11860 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11861 tempreg, breg, mips_gp_register); 11862 macro_build (&offset_expr, s, fmt, op[0], 11863 BFD_RELOC_GPREL16, tempreg); 11864 relax_switch (); 11865 } 11866 macro_build_lui (&offset_expr, tempreg); 11867 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11868 tempreg, tempreg, breg); 11869 macro_build (&offset_expr, s, fmt, op[0], 11870 BFD_RELOC_LO16, tempreg); 11871 if (mips_relax.sequence) 11872 relax_end (); 11873 } 11874 } 11875 else if (!mips_big_got) 11876 { 11877 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 11878 11879 /* If this is a reference to an external symbol, we want 11880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11881 nop 11882 <op> op[0],0($tempreg) 11883 Otherwise we want 11884 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11885 nop 11886 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 11887 <op> op[0],0($tempreg) 11888 11889 For NewABI, we want 11890 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 11891 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) 11892 11893 If there is a base register, we add it to $tempreg before 11894 the <op>. If there is a constant, we stick it in the 11895 <op> instruction. We don't handle constants larger than 11896 16 bits, because we have no way to load the upper 16 bits 11897 (actually, we could handle them for the subset of cases 11898 in which we are not using $at). */ 11899 gas_assert (offset_expr.X_op == O_symbol); 11900 if (HAVE_NEWABI) 11901 { 11902 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11903 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 11904 if (breg != 0) 11905 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11906 tempreg, tempreg, breg); 11907 macro_build (&offset_expr, s, fmt, op[0], 11908 BFD_RELOC_MIPS_GOT_OFST, tempreg); 11909 break; 11910 } 11911 expr1.X_add_number = offset_expr.X_add_number; 11912 offset_expr.X_add_number = 0; 11913 if (expr1.X_add_number < -0x8000 11914 || expr1.X_add_number >= 0x8000) 11915 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 11916 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11917 lw_reloc_type, mips_gp_register); 11918 load_delay_nop (); 11919 relax_start (offset_expr.X_add_symbol); 11920 relax_switch (); 11921 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 11922 tempreg, BFD_RELOC_LO16); 11923 relax_end (); 11924 if (breg != 0) 11925 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11926 tempreg, tempreg, breg); 11927 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 11928 } 11929 else if (mips_big_got && !HAVE_NEWABI) 11930 { 11931 int gpdelay; 11932 11933 /* If this is a reference to an external symbol, we want 11934 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11935 addu $tempreg,$tempreg,$gp 11936 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11937 <op> op[0],0($tempreg) 11938 Otherwise we want 11939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11940 nop 11941 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 11942 <op> op[0],0($tempreg) 11943 If there is a base register, we add it to $tempreg before 11944 the <op>. If there is a constant, we stick it in the 11945 <op> instruction. We don't handle constants larger than 11946 16 bits, because we have no way to load the upper 16 bits 11947 (actually, we could handle them for the subset of cases 11948 in which we are not using $at). */ 11949 gas_assert (offset_expr.X_op == O_symbol); 11950 expr1.X_add_number = offset_expr.X_add_number; 11951 offset_expr.X_add_number = 0; 11952 if (expr1.X_add_number < -0x8000 11953 || expr1.X_add_number >= 0x8000) 11954 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 11955 gpdelay = reg_needs_delay (mips_gp_register); 11956 relax_start (offset_expr.X_add_symbol); 11957 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11958 BFD_RELOC_MIPS_GOT_HI16); 11959 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 11960 mips_gp_register); 11961 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11962 BFD_RELOC_MIPS_GOT_LO16, tempreg); 11963 relax_switch (); 11964 if (gpdelay) 11965 macro_build (NULL, "nop", ""); 11966 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11967 BFD_RELOC_MIPS_GOT16, mips_gp_register); 11968 load_delay_nop (); 11969 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 11970 tempreg, BFD_RELOC_LO16); 11971 relax_end (); 11972 11973 if (breg != 0) 11974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11975 tempreg, tempreg, breg); 11976 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 11977 } 11978 else if (mips_big_got && HAVE_NEWABI) 11979 { 11980 /* If this is a reference to an external symbol, we want 11981 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11982 add $tempreg,$tempreg,$gp 11983 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11984 <op> op[0],<ofst>($tempreg) 11985 Otherwise, for local symbols, we want: 11986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 11987 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ 11988 gas_assert (offset_expr.X_op == O_symbol); 11989 expr1.X_add_number = offset_expr.X_add_number; 11990 offset_expr.X_add_number = 0; 11991 if (expr1.X_add_number < -0x8000 11992 || expr1.X_add_number >= 0x8000) 11993 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 11994 relax_start (offset_expr.X_add_symbol); 11995 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11996 BFD_RELOC_MIPS_GOT_HI16); 11997 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 11998 mips_gp_register); 11999 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12000 BFD_RELOC_MIPS_GOT_LO16, tempreg); 12001 if (breg != 0) 12002 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12003 tempreg, tempreg, breg); 12004 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12005 12006 relax_switch (); 12007 offset_expr.X_add_number = expr1.X_add_number; 12008 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12009 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 12010 if (breg != 0) 12011 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12012 tempreg, tempreg, breg); 12013 macro_build (&offset_expr, s, fmt, op[0], 12014 BFD_RELOC_MIPS_GOT_OFST, tempreg); 12015 relax_end (); 12016 } 12017 else 12018 abort (); 12019 12020 break; 12021 12022 case M_JRADDIUSP: 12023 gas_assert (mips_opts.micromips); 12024 gas_assert (mips_opts.insn32); 12025 start_noreorder (); 12026 macro_build (NULL, "jr", "s", RA); 12027 expr1.X_add_number = op[0] << 2; 12028 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); 12029 end_noreorder (); 12030 break; 12031 12032 case M_JRC: 12033 gas_assert (mips_opts.micromips); 12034 gas_assert (mips_opts.insn32); 12035 macro_build (NULL, "jr", "s", op[0]); 12036 if (mips_opts.noreorder) 12037 macro_build (NULL, "nop", ""); 12038 break; 12039 12040 case M_LI: 12041 case M_LI_S: 12042 load_register (op[0], &imm_expr, 0); 12043 break; 12044 12045 case M_DLI: 12046 load_register (op[0], &imm_expr, 1); 12047 break; 12048 12049 case M_LI_SS: 12050 if (imm_expr.X_op == O_constant) 12051 { 12052 used_at = 1; 12053 load_register (AT, &imm_expr, 0); 12054 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12055 break; 12056 } 12057 else 12058 { 12059 gas_assert (imm_expr.X_op == O_absent 12060 && offset_expr.X_op == O_symbol 12061 && strcmp (segment_name (S_GET_SEGMENT 12062 (offset_expr.X_add_symbol)), 12063 ".lit4") == 0 12064 && offset_expr.X_add_number == 0); 12065 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], 12066 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 12067 break; 12068 } 12069 12070 case M_LI_D: 12071 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits 12072 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high 12073 order 32 bits of the value and the low order 32 bits are either 12074 zero or in OFFSET_EXPR. */ 12075 if (imm_expr.X_op == O_constant) 12076 { 12077 if (GPR_SIZE == 64) 12078 load_register (op[0], &imm_expr, 1); 12079 else 12080 { 12081 int hreg, lreg; 12082 12083 if (target_big_endian) 12084 { 12085 hreg = op[0]; 12086 lreg = op[0] + 1; 12087 } 12088 else 12089 { 12090 hreg = op[0] + 1; 12091 lreg = op[0]; 12092 } 12093 12094 if (hreg <= 31) 12095 load_register (hreg, &imm_expr, 0); 12096 if (lreg <= 31) 12097 { 12098 if (offset_expr.X_op == O_absent) 12099 move_register (lreg, 0); 12100 else 12101 { 12102 gas_assert (offset_expr.X_op == O_constant); 12103 load_register (lreg, &offset_expr, 0); 12104 } 12105 } 12106 } 12107 break; 12108 } 12109 gas_assert (imm_expr.X_op == O_absent); 12110 12111 /* We know that sym is in the .rdata section. First we get the 12112 upper 16 bits of the address. */ 12113 if (mips_pic == NO_PIC) 12114 { 12115 macro_build_lui (&offset_expr, AT); 12116 used_at = 1; 12117 } 12118 else 12119 { 12120 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12121 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12122 used_at = 1; 12123 } 12124 12125 /* Now we load the register(s). */ 12126 if (GPR_SIZE == 64) 12127 { 12128 used_at = 1; 12129 macro_build (&offset_expr, "ld", "t,o(b)", op[0], 12130 BFD_RELOC_LO16, AT); 12131 } 12132 else 12133 { 12134 used_at = 1; 12135 macro_build (&offset_expr, "lw", "t,o(b)", op[0], 12136 BFD_RELOC_LO16, AT); 12137 if (op[0] != RA) 12138 { 12139 /* FIXME: How in the world do we deal with the possible 12140 overflow here? */ 12141 offset_expr.X_add_number += 4; 12142 macro_build (&offset_expr, "lw", "t,o(b)", 12143 op[0] + 1, BFD_RELOC_LO16, AT); 12144 } 12145 } 12146 break; 12147 12148 case M_LI_DD: 12149 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits 12150 wide, IMM_EXPR is the entire value and the GPRs are known to be 64 12151 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of 12152 the value and the low order 32 bits are either zero or in 12153 OFFSET_EXPR. */ 12154 if (imm_expr.X_op == O_constant) 12155 { 12156 used_at = 1; 12157 load_register (AT, &imm_expr, FPR_SIZE == 64); 12158 if (FPR_SIZE == 64 && GPR_SIZE == 64) 12159 macro_build (NULL, "dmtc1", "t,S", AT, op[0]); 12160 else 12161 { 12162 if (ISA_HAS_MXHC1 (mips_opts.isa)) 12163 macro_build (NULL, "mthc1", "t,G", AT, op[0]); 12164 else if (FPR_SIZE != 32) 12165 as_bad (_("Unable to generate `%s' compliant code " 12166 "without mthc1"), 12167 (FPR_SIZE == 64) ? "fp64" : "fpxx"); 12168 else 12169 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); 12170 if (offset_expr.X_op == O_absent) 12171 macro_build (NULL, "mtc1", "t,G", 0, op[0]); 12172 else 12173 { 12174 gas_assert (offset_expr.X_op == O_constant); 12175 load_register (AT, &offset_expr, 0); 12176 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12177 } 12178 } 12179 break; 12180 } 12181 12182 gas_assert (imm_expr.X_op == O_absent 12183 && offset_expr.X_op == O_symbol 12184 && offset_expr.X_add_number == 0); 12185 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); 12186 if (strcmp (s, ".lit8") == 0) 12187 { 12188 op[2] = mips_gp_register; 12189 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; 12190 offset_reloc[1] = BFD_RELOC_UNUSED; 12191 offset_reloc[2] = BFD_RELOC_UNUSED; 12192 } 12193 else 12194 { 12195 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); 12196 used_at = 1; 12197 if (mips_pic != NO_PIC) 12198 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12199 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12200 else 12201 { 12202 /* FIXME: This won't work for a 64 bit address. */ 12203 macro_build_lui (&offset_expr, AT); 12204 } 12205 12206 op[2] = AT; 12207 offset_reloc[0] = BFD_RELOC_LO16; 12208 offset_reloc[1] = BFD_RELOC_UNUSED; 12209 offset_reloc[2] = BFD_RELOC_UNUSED; 12210 } 12211 align = 8; 12212 /* Fall through */ 12213 12214 case M_L_DAB: 12215 /* 12216 * The MIPS assembler seems to check for X_add_number not 12217 * being double aligned and generating: 12218 * lui at,%hi(foo+1) 12219 * addu at,at,v1 12220 * addiu at,at,%lo(foo+1) 12221 * lwc1 f2,0(at) 12222 * lwc1 f3,4(at) 12223 * But, the resulting address is the same after relocation so why 12224 * generate the extra instruction? 12225 */ 12226 /* Itbl support may require additional care here. */ 12227 coproc = 1; 12228 fmt = "T,o(b)"; 12229 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12230 { 12231 s = "ldc1"; 12232 goto ld_st; 12233 } 12234 s = "lwc1"; 12235 goto ldd_std; 12236 12237 case M_S_DAB: 12238 gas_assert (!mips_opts.micromips); 12239 /* Itbl support may require additional care here. */ 12240 coproc = 1; 12241 fmt = "T,o(b)"; 12242 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12243 { 12244 s = "sdc1"; 12245 goto ld_st; 12246 } 12247 s = "swc1"; 12248 goto ldd_std; 12249 12250 case M_LQ_AB: 12251 fmt = "t,o(b)"; 12252 s = "lq"; 12253 goto ld; 12254 12255 case M_SQ_AB: 12256 fmt = "t,o(b)"; 12257 s = "sq"; 12258 goto ld_st; 12259 12260 case M_LD_AB: 12261 fmt = "t,o(b)"; 12262 if (GPR_SIZE == 64) 12263 { 12264 s = "ld"; 12265 goto ld; 12266 } 12267 s = "lw"; 12268 goto ldd_std; 12269 12270 case M_SD_AB: 12271 fmt = "t,o(b)"; 12272 if (GPR_SIZE == 64) 12273 { 12274 s = "sd"; 12275 goto ld_st; 12276 } 12277 s = "sw"; 12278 12279 ldd_std: 12280 /* Even on a big endian machine $fn comes before $fn+1. We have 12281 to adjust when loading from memory. We set coproc if we must 12282 load $fn+1 first. */ 12283 /* Itbl support may require additional care here. */ 12284 if (!target_big_endian) 12285 coproc = 0; 12286 12287 breg = op[2]; 12288 if (small_offset_p (0, align, 16)) 12289 { 12290 ep = &offset_expr; 12291 if (!small_offset_p (4, align, 16)) 12292 { 12293 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, 12294 -1, offset_reloc[0], offset_reloc[1], 12295 offset_reloc[2]); 12296 expr1.X_add_number = 0; 12297 ep = &expr1; 12298 breg = AT; 12299 used_at = 1; 12300 offset_reloc[0] = BFD_RELOC_LO16; 12301 offset_reloc[1] = BFD_RELOC_UNUSED; 12302 offset_reloc[2] = BFD_RELOC_UNUSED; 12303 } 12304 if (strcmp (s, "lw") == 0 && op[0] == breg) 12305 { 12306 ep->X_add_number += 4; 12307 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], 12308 offset_reloc[1], offset_reloc[2], breg); 12309 ep->X_add_number -= 4; 12310 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], 12311 offset_reloc[1], offset_reloc[2], breg); 12312 } 12313 else 12314 { 12315 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, 12316 offset_reloc[0], offset_reloc[1], offset_reloc[2], 12317 breg); 12318 ep->X_add_number += 4; 12319 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, 12320 offset_reloc[0], offset_reloc[1], offset_reloc[2], 12321 breg); 12322 } 12323 break; 12324 } 12325 12326 if (offset_expr.X_op != O_symbol 12327 && offset_expr.X_op != O_constant) 12328 { 12329 as_bad (_("expression too complex")); 12330 offset_expr.X_op = O_constant; 12331 } 12332 12333 if (HAVE_32BIT_ADDRESSES 12334 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 12335 { 12336 char value [32]; 12337 12338 sprintf_vma (value, offset_expr.X_add_number); 12339 as_bad (_("number (0x%s) larger than 32 bits"), value); 12340 } 12341 12342 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) 12343 { 12344 /* If this is a reference to a GP relative symbol, we want 12345 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 12346 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 12347 If we have a base register, we use this 12348 addu $at,$breg,$gp 12349 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) 12350 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) 12351 If this is not a GP relative symbol, we want 12352 lui $at,<sym> (BFD_RELOC_HI16_S) 12353 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12354 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12355 If there is a base register, we add it to $at after the 12356 lui instruction. If there is a constant, we always use 12357 the last case. */ 12358 if (offset_expr.X_op == O_symbol 12359 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 12360 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 12361 { 12362 relax_start (offset_expr.X_add_symbol); 12363 if (breg == 0) 12364 { 12365 tempreg = mips_gp_register; 12366 } 12367 else 12368 { 12369 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12370 AT, breg, mips_gp_register); 12371 tempreg = AT; 12372 used_at = 1; 12373 } 12374 12375 /* Itbl support may require additional care here. */ 12376 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12377 BFD_RELOC_GPREL16, tempreg); 12378 offset_expr.X_add_number += 4; 12379 12380 /* Set mips_optimize to 2 to avoid inserting an 12381 undesired nop. */ 12382 hold_mips_optimize = mips_optimize; 12383 mips_optimize = 2; 12384 /* Itbl support may require additional care here. */ 12385 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12386 BFD_RELOC_GPREL16, tempreg); 12387 mips_optimize = hold_mips_optimize; 12388 12389 relax_switch (); 12390 12391 offset_expr.X_add_number -= 4; 12392 } 12393 used_at = 1; 12394 if (offset_high_part (offset_expr.X_add_number, 16) 12395 != offset_high_part (offset_expr.X_add_number + 4, 16)) 12396 { 12397 load_address (AT, &offset_expr, &used_at); 12398 offset_expr.X_op = O_constant; 12399 offset_expr.X_add_number = 0; 12400 } 12401 else 12402 macro_build_lui (&offset_expr, AT); 12403 if (breg != 0) 12404 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12405 /* Itbl support may require additional care here. */ 12406 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12407 BFD_RELOC_LO16, AT); 12408 /* FIXME: How do we handle overflow here? */ 12409 offset_expr.X_add_number += 4; 12410 /* Itbl support may require additional care here. */ 12411 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12412 BFD_RELOC_LO16, AT); 12413 if (mips_relax.sequence) 12414 relax_end (); 12415 } 12416 else if (!mips_big_got) 12417 { 12418 /* If this is a reference to an external symbol, we want 12419 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12420 nop 12421 <op> op[0],0($at) 12422 <op> op[0]+1,4($at) 12423 Otherwise we want 12424 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12425 nop 12426 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12427 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12428 If there is a base register we add it to $at before the 12429 lwc1 instructions. If there is a constant we include it 12430 in the lwc1 instructions. */ 12431 used_at = 1; 12432 expr1.X_add_number = offset_expr.X_add_number; 12433 if (expr1.X_add_number < -0x8000 12434 || expr1.X_add_number >= 0x8000 - 4) 12435 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12436 load_got_offset (AT, &offset_expr); 12437 load_delay_nop (); 12438 if (breg != 0) 12439 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12440 12441 /* Set mips_optimize to 2 to avoid inserting an undesired 12442 nop. */ 12443 hold_mips_optimize = mips_optimize; 12444 mips_optimize = 2; 12445 12446 /* Itbl support may require additional care here. */ 12447 relax_start (offset_expr.X_add_symbol); 12448 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 12449 BFD_RELOC_LO16, AT); 12450 expr1.X_add_number += 4; 12451 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 12452 BFD_RELOC_LO16, AT); 12453 relax_switch (); 12454 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12455 BFD_RELOC_LO16, AT); 12456 offset_expr.X_add_number += 4; 12457 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12458 BFD_RELOC_LO16, AT); 12459 relax_end (); 12460 12461 mips_optimize = hold_mips_optimize; 12462 } 12463 else if (mips_big_got) 12464 { 12465 int gpdelay; 12466 12467 /* If this is a reference to an external symbol, we want 12468 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12469 addu $at,$at,$gp 12470 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) 12471 nop 12472 <op> op[0],0($at) 12473 <op> op[0]+1,4($at) 12474 Otherwise we want 12475 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12476 nop 12477 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12478 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12479 If there is a base register we add it to $at before the 12480 lwc1 instructions. If there is a constant we include it 12481 in the lwc1 instructions. */ 12482 used_at = 1; 12483 expr1.X_add_number = offset_expr.X_add_number; 12484 offset_expr.X_add_number = 0; 12485 if (expr1.X_add_number < -0x8000 12486 || expr1.X_add_number >= 0x8000 - 4) 12487 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12488 gpdelay = reg_needs_delay (mips_gp_register); 12489 relax_start (offset_expr.X_add_symbol); 12490 macro_build (&offset_expr, "lui", LUI_FMT, 12491 AT, BFD_RELOC_MIPS_GOT_HI16); 12492 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12493 AT, AT, mips_gp_register); 12494 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 12495 AT, BFD_RELOC_MIPS_GOT_LO16, AT); 12496 load_delay_nop (); 12497 if (breg != 0) 12498 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12499 /* Itbl support may require additional care here. */ 12500 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 12501 BFD_RELOC_LO16, AT); 12502 expr1.X_add_number += 4; 12503 12504 /* Set mips_optimize to 2 to avoid inserting an undesired 12505 nop. */ 12506 hold_mips_optimize = mips_optimize; 12507 mips_optimize = 2; 12508 /* Itbl support may require additional care here. */ 12509 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 12510 BFD_RELOC_LO16, AT); 12511 mips_optimize = hold_mips_optimize; 12512 expr1.X_add_number -= 4; 12513 12514 relax_switch (); 12515 offset_expr.X_add_number = expr1.X_add_number; 12516 if (gpdelay) 12517 macro_build (NULL, "nop", ""); 12518 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12519 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12520 load_delay_nop (); 12521 if (breg != 0) 12522 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12523 /* Itbl support may require additional care here. */ 12524 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12525 BFD_RELOC_LO16, AT); 12526 offset_expr.X_add_number += 4; 12527 12528 /* Set mips_optimize to 2 to avoid inserting an undesired 12529 nop. */ 12530 hold_mips_optimize = mips_optimize; 12531 mips_optimize = 2; 12532 /* Itbl support may require additional care here. */ 12533 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12534 BFD_RELOC_LO16, AT); 12535 mips_optimize = hold_mips_optimize; 12536 relax_end (); 12537 } 12538 else 12539 abort (); 12540 12541 break; 12542 12543 case M_SAA_AB: 12544 s = "saa"; 12545 goto saa_saad; 12546 case M_SAAD_AB: 12547 s = "saad"; 12548 saa_saad: 12549 gas_assert (!mips_opts.micromips); 12550 offbits = 0; 12551 fmt = "t,(b)"; 12552 goto ld_st; 12553 12554 /* New code added to support COPZ instructions. 12555 This code builds table entries out of the macros in mip_opcodes. 12556 R4000 uses interlocks to handle coproc delays. 12557 Other chips (like the R3000) require nops to be inserted for delays. 12558 12559 FIXME: Currently, we require that the user handle delays. 12560 In order to fill delay slots for non-interlocked chips, 12561 we must have a way to specify delays based on the coprocessor. 12562 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. 12563 What are the side-effects of the cop instruction? 12564 What cache support might we have and what are its effects? 12565 Both coprocessor & memory require delays. how long??? 12566 What registers are read/set/modified? 12567 12568 If an itbl is provided to interpret cop instructions, 12569 this knowledge can be encoded in the itbl spec. */ 12570 12571 case M_COP0: 12572 s = "c0"; 12573 goto copz; 12574 case M_COP1: 12575 s = "c1"; 12576 goto copz; 12577 case M_COP2: 12578 s = "c2"; 12579 goto copz; 12580 case M_COP3: 12581 s = "c3"; 12582 copz: 12583 gas_assert (!mips_opts.micromips); 12584 /* For now we just do C (same as Cz). The parameter will be 12585 stored in insn_opcode by mips_ip. */ 12586 macro_build (NULL, s, "C", (int) ip->insn_opcode); 12587 break; 12588 12589 case M_MOVE: 12590 move_register (op[0], op[1]); 12591 break; 12592 12593 case M_MOVEP: 12594 gas_assert (mips_opts.micromips); 12595 gas_assert (mips_opts.insn32); 12596 move_register (micromips_to_32_reg_h_map1[op[0]], 12597 micromips_to_32_reg_m_map[op[1]]); 12598 move_register (micromips_to_32_reg_h_map2[op[0]], 12599 micromips_to_32_reg_n_map[op[2]]); 12600 break; 12601 12602 case M_DMUL: 12603 dbl = 1; 12604 case M_MUL: 12605 if (mips_opts.arch == CPU_R5900) 12606 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], 12607 op[2]); 12608 else 12609 { 12610 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); 12611 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12612 } 12613 break; 12614 12615 case M_DMUL_I: 12616 dbl = 1; 12617 case M_MUL_I: 12618 /* The MIPS assembler some times generates shifts and adds. I'm 12619 not trying to be that fancy. GCC should do this for us 12620 anyway. */ 12621 used_at = 1; 12622 load_register (AT, &imm_expr, dbl); 12623 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); 12624 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12625 break; 12626 12627 case M_DMULO_I: 12628 dbl = 1; 12629 case M_MULO_I: 12630 imm = 1; 12631 goto do_mulo; 12632 12633 case M_DMULO: 12634 dbl = 1; 12635 case M_MULO: 12636 do_mulo: 12637 start_noreorder (); 12638 used_at = 1; 12639 if (imm) 12640 load_register (AT, &imm_expr, dbl); 12641 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", 12642 op[1], imm ? AT : op[2]); 12643 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12644 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); 12645 macro_build (NULL, "mfhi", MFHL_FMT, AT); 12646 if (mips_trap) 12647 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); 12648 else 12649 { 12650 if (mips_opts.micromips) 12651 micromips_label_expr (&label_expr); 12652 else 12653 label_expr.X_add_number = 8; 12654 macro_build (&label_expr, "beq", "s,t,p", op[0], AT); 12655 macro_build (NULL, "nop", ""); 12656 macro_build (NULL, "break", BRK_FMT, 6); 12657 if (mips_opts.micromips) 12658 micromips_add_label (); 12659 } 12660 end_noreorder (); 12661 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12662 break; 12663 12664 case M_DMULOU_I: 12665 dbl = 1; 12666 case M_MULOU_I: 12667 imm = 1; 12668 goto do_mulou; 12669 12670 case M_DMULOU: 12671 dbl = 1; 12672 case M_MULOU: 12673 do_mulou: 12674 start_noreorder (); 12675 used_at = 1; 12676 if (imm) 12677 load_register (AT, &imm_expr, dbl); 12678 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", 12679 op[1], imm ? AT : op[2]); 12680 macro_build (NULL, "mfhi", MFHL_FMT, AT); 12681 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12682 if (mips_trap) 12683 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); 12684 else 12685 { 12686 if (mips_opts.micromips) 12687 micromips_label_expr (&label_expr); 12688 else 12689 label_expr.X_add_number = 8; 12690 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); 12691 macro_build (NULL, "nop", ""); 12692 macro_build (NULL, "break", BRK_FMT, 6); 12693 if (mips_opts.micromips) 12694 micromips_add_label (); 12695 } 12696 end_noreorder (); 12697 break; 12698 12699 case M_DROL: 12700 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12701 { 12702 if (op[0] == op[1]) 12703 { 12704 tempreg = AT; 12705 used_at = 1; 12706 } 12707 else 12708 tempreg = op[0]; 12709 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); 12710 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); 12711 break; 12712 } 12713 used_at = 1; 12714 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 12715 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); 12716 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); 12717 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12718 break; 12719 12720 case M_ROL: 12721 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12722 { 12723 if (op[0] == op[1]) 12724 { 12725 tempreg = AT; 12726 used_at = 1; 12727 } 12728 else 12729 tempreg = op[0]; 12730 macro_build (NULL, "negu", "d,w", tempreg, op[2]); 12731 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); 12732 break; 12733 } 12734 used_at = 1; 12735 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 12736 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); 12737 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); 12738 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12739 break; 12740 12741 case M_DROL_I: 12742 { 12743 unsigned int rot; 12744 const char *l; 12745 const char *rr; 12746 12747 rot = imm_expr.X_add_number & 0x3f; 12748 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12749 { 12750 rot = (64 - rot) & 0x3f; 12751 if (rot >= 32) 12752 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 12753 else 12754 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 12755 break; 12756 } 12757 if (rot == 0) 12758 { 12759 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 12760 break; 12761 } 12762 l = (rot < 0x20) ? "dsll" : "dsll32"; 12763 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; 12764 rot &= 0x1f; 12765 used_at = 1; 12766 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); 12767 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12768 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12769 } 12770 break; 12771 12772 case M_ROL_I: 12773 { 12774 unsigned int rot; 12775 12776 rot = imm_expr.X_add_number & 0x1f; 12777 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12778 { 12779 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], 12780 (32 - rot) & 0x1f); 12781 break; 12782 } 12783 if (rot == 0) 12784 { 12785 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 12786 break; 12787 } 12788 used_at = 1; 12789 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); 12790 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12791 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12792 } 12793 break; 12794 12795 case M_DROR: 12796 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12797 { 12798 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); 12799 break; 12800 } 12801 used_at = 1; 12802 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 12803 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); 12804 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); 12805 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12806 break; 12807 12808 case M_ROR: 12809 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12810 { 12811 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); 12812 break; 12813 } 12814 used_at = 1; 12815 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 12816 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); 12817 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); 12818 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12819 break; 12820 12821 case M_DROR_I: 12822 { 12823 unsigned int rot; 12824 const char *l; 12825 const char *rr; 12826 12827 rot = imm_expr.X_add_number & 0x3f; 12828 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12829 { 12830 if (rot >= 32) 12831 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 12832 else 12833 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 12834 break; 12835 } 12836 if (rot == 0) 12837 { 12838 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 12839 break; 12840 } 12841 rr = (rot < 0x20) ? "dsrl" : "dsrl32"; 12842 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; 12843 rot &= 0x1f; 12844 used_at = 1; 12845 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); 12846 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12847 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12848 } 12849 break; 12850 12851 case M_ROR_I: 12852 { 12853 unsigned int rot; 12854 12855 rot = imm_expr.X_add_number & 0x1f; 12856 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12857 { 12858 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); 12859 break; 12860 } 12861 if (rot == 0) 12862 { 12863 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 12864 break; 12865 } 12866 used_at = 1; 12867 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); 12868 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12869 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12870 } 12871 break; 12872 12873 case M_SEQ: 12874 if (op[1] == 0) 12875 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); 12876 else if (op[2] == 0) 12877 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 12878 else 12879 { 12880 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 12881 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 12882 } 12883 break; 12884 12885 case M_SEQ_I: 12886 if (imm_expr.X_add_number == 0) 12887 { 12888 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 12889 break; 12890 } 12891 if (op[1] == 0) 12892 { 12893 as_warn (_("instruction %s: result is always false"), 12894 ip->insn_mo->name); 12895 move_register (op[0], 0); 12896 break; 12897 } 12898 if (CPU_HAS_SEQ (mips_opts.arch) 12899 && -512 <= imm_expr.X_add_number 12900 && imm_expr.X_add_number < 512) 12901 { 12902 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], 12903 (int) imm_expr.X_add_number); 12904 break; 12905 } 12906 if (imm_expr.X_add_number >= 0 12907 && imm_expr.X_add_number < 0x10000) 12908 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); 12909 else if (imm_expr.X_add_number > -0x8000 12910 && imm_expr.X_add_number < 0) 12911 { 12912 imm_expr.X_add_number = -imm_expr.X_add_number; 12913 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 12914 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 12915 } 12916 else if (CPU_HAS_SEQ (mips_opts.arch)) 12917 { 12918 used_at = 1; 12919 load_register (AT, &imm_expr, GPR_SIZE == 64); 12920 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); 12921 break; 12922 } 12923 else 12924 { 12925 load_register (AT, &imm_expr, GPR_SIZE == 64); 12926 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 12927 used_at = 1; 12928 } 12929 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 12930 break; 12931 12932 case M_SGE: /* X >= Y <==> not (X < Y) */ 12933 s = "slt"; 12934 goto sge; 12935 case M_SGEU: 12936 s = "sltu"; 12937 sge: 12938 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); 12939 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 12940 break; 12941 12942 case M_SGE_I: /* X >= I <==> not (X < I) */ 12943 case M_SGEU_I: 12944 if (imm_expr.X_add_number >= -0x8000 12945 && imm_expr.X_add_number < 0x8000) 12946 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", 12947 op[0], op[1], BFD_RELOC_LO16); 12948 else 12949 { 12950 load_register (AT, &imm_expr, GPR_SIZE == 64); 12951 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", 12952 op[0], op[1], AT); 12953 used_at = 1; 12954 } 12955 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 12956 break; 12957 12958 case M_SGT: /* X > Y <==> Y < X */ 12959 s = "slt"; 12960 goto sgt; 12961 case M_SGTU: 12962 s = "sltu"; 12963 sgt: 12964 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 12965 break; 12966 12967 case M_SGT_I: /* X > I <==> I < X */ 12968 s = "slt"; 12969 goto sgti; 12970 case M_SGTU_I: 12971 s = "sltu"; 12972 sgti: 12973 used_at = 1; 12974 load_register (AT, &imm_expr, GPR_SIZE == 64); 12975 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 12976 break; 12977 12978 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ 12979 s = "slt"; 12980 goto sle; 12981 case M_SLEU: 12982 s = "sltu"; 12983 sle: 12984 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 12985 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 12986 break; 12987 12988 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ 12989 s = "slt"; 12990 goto slei; 12991 case M_SLEU_I: 12992 s = "sltu"; 12993 slei: 12994 used_at = 1; 12995 load_register (AT, &imm_expr, GPR_SIZE == 64); 12996 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 12997 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 12998 break; 12999 13000 case M_SLT_I: 13001 if (imm_expr.X_add_number >= -0x8000 13002 && imm_expr.X_add_number < 0x8000) 13003 { 13004 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], 13005 BFD_RELOC_LO16); 13006 break; 13007 } 13008 used_at = 1; 13009 load_register (AT, &imm_expr, GPR_SIZE == 64); 13010 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); 13011 break; 13012 13013 case M_SLTU_I: 13014 if (imm_expr.X_add_number >= -0x8000 13015 && imm_expr.X_add_number < 0x8000) 13016 { 13017 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], 13018 BFD_RELOC_LO16); 13019 break; 13020 } 13021 used_at = 1; 13022 load_register (AT, &imm_expr, GPR_SIZE == 64); 13023 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); 13024 break; 13025 13026 case M_SNE: 13027 if (op[1] == 0) 13028 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); 13029 else if (op[2] == 0) 13030 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13031 else 13032 { 13033 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 13034 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13035 } 13036 break; 13037 13038 case M_SNE_I: 13039 if (imm_expr.X_add_number == 0) 13040 { 13041 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13042 break; 13043 } 13044 if (op[1] == 0) 13045 { 13046 as_warn (_("instruction %s: result is always true"), 13047 ip->insn_mo->name); 13048 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", 13049 op[0], 0, BFD_RELOC_LO16); 13050 break; 13051 } 13052 if (CPU_HAS_SEQ (mips_opts.arch) 13053 && -512 <= imm_expr.X_add_number 13054 && imm_expr.X_add_number < 512) 13055 { 13056 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], 13057 (int) imm_expr.X_add_number); 13058 break; 13059 } 13060 if (imm_expr.X_add_number >= 0 13061 && imm_expr.X_add_number < 0x10000) 13062 { 13063 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], 13064 BFD_RELOC_LO16); 13065 } 13066 else if (imm_expr.X_add_number > -0x8000 13067 && imm_expr.X_add_number < 0) 13068 { 13069 imm_expr.X_add_number = -imm_expr.X_add_number; 13070 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 13071 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13072 } 13073 else if (CPU_HAS_SEQ (mips_opts.arch)) 13074 { 13075 used_at = 1; 13076 load_register (AT, &imm_expr, GPR_SIZE == 64); 13077 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); 13078 break; 13079 } 13080 else 13081 { 13082 load_register (AT, &imm_expr, GPR_SIZE == 64); 13083 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 13084 used_at = 1; 13085 } 13086 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13087 break; 13088 13089 case M_SUB_I: 13090 s = "addi"; 13091 s2 = "sub"; 13092 goto do_subi; 13093 case M_SUBU_I: 13094 s = "addiu"; 13095 s2 = "subu"; 13096 goto do_subi; 13097 case M_DSUB_I: 13098 dbl = 1; 13099 s = "daddi"; 13100 s2 = "dsub"; 13101 if (!mips_opts.micromips) 13102 goto do_subi; 13103 if (imm_expr.X_add_number > -0x200 13104 && imm_expr.X_add_number <= 0x200) 13105 { 13106 macro_build (NULL, s, "t,r,.", op[0], op[1], 13107 (int) -imm_expr.X_add_number); 13108 break; 13109 } 13110 goto do_subi_i; 13111 case M_DSUBU_I: 13112 dbl = 1; 13113 s = "daddiu"; 13114 s2 = "dsubu"; 13115 do_subi: 13116 if (imm_expr.X_add_number > -0x8000 13117 && imm_expr.X_add_number <= 0x8000) 13118 { 13119 imm_expr.X_add_number = -imm_expr.X_add_number; 13120 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13121 break; 13122 } 13123 do_subi_i: 13124 used_at = 1; 13125 load_register (AT, &imm_expr, dbl); 13126 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 13127 break; 13128 13129 case M_TEQ_I: 13130 s = "teq"; 13131 goto trap; 13132 case M_TGE_I: 13133 s = "tge"; 13134 goto trap; 13135 case M_TGEU_I: 13136 s = "tgeu"; 13137 goto trap; 13138 case M_TLT_I: 13139 s = "tlt"; 13140 goto trap; 13141 case M_TLTU_I: 13142 s = "tltu"; 13143 goto trap; 13144 case M_TNE_I: 13145 s = "tne"; 13146 trap: 13147 used_at = 1; 13148 load_register (AT, &imm_expr, GPR_SIZE == 64); 13149 macro_build (NULL, s, "s,t", op[0], AT); 13150 break; 13151 13152 case M_TRUNCWS: 13153 case M_TRUNCWD: 13154 gas_assert (!mips_opts.micromips); 13155 gas_assert (mips_opts.isa == ISA_MIPS1); 13156 used_at = 1; 13157 13158 /* 13159 * Is the double cfc1 instruction a bug in the mips assembler; 13160 * or is there a reason for it? 13161 */ 13162 start_noreorder (); 13163 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13164 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13165 macro_build (NULL, "nop", ""); 13166 expr1.X_add_number = 3; 13167 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); 13168 expr1.X_add_number = 2; 13169 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); 13170 macro_build (NULL, "ctc1", "t,G", AT, RA); 13171 macro_build (NULL, "nop", ""); 13172 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", 13173 op[0], op[1]); 13174 macro_build (NULL, "ctc1", "t,G", op[2], RA); 13175 macro_build (NULL, "nop", ""); 13176 end_noreorder (); 13177 break; 13178 13179 case M_ULH_AB: 13180 s = "lb"; 13181 s2 = "lbu"; 13182 off = 1; 13183 goto uld_st; 13184 case M_ULHU_AB: 13185 s = "lbu"; 13186 s2 = "lbu"; 13187 off = 1; 13188 goto uld_st; 13189 case M_ULW_AB: 13190 s = "lwl"; 13191 s2 = "lwr"; 13192 offbits = (mips_opts.micromips ? 12 : 16); 13193 off = 3; 13194 goto uld_st; 13195 case M_ULD_AB: 13196 s = "ldl"; 13197 s2 = "ldr"; 13198 offbits = (mips_opts.micromips ? 12 : 16); 13199 off = 7; 13200 goto uld_st; 13201 case M_USH_AB: 13202 s = "sb"; 13203 s2 = "sb"; 13204 off = 1; 13205 ust = 1; 13206 goto uld_st; 13207 case M_USW_AB: 13208 s = "swl"; 13209 s2 = "swr"; 13210 offbits = (mips_opts.micromips ? 12 : 16); 13211 off = 3; 13212 ust = 1; 13213 goto uld_st; 13214 case M_USD_AB: 13215 s = "sdl"; 13216 s2 = "sdr"; 13217 offbits = (mips_opts.micromips ? 12 : 16); 13218 off = 7; 13219 ust = 1; 13220 13221 uld_st: 13222 breg = op[2]; 13223 large_offset = !small_offset_p (off, align, offbits); 13224 ep = &offset_expr; 13225 expr1.X_add_number = 0; 13226 if (large_offset) 13227 { 13228 used_at = 1; 13229 tempreg = AT; 13230 if (small_offset_p (0, align, 16)) 13231 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, 13232 offset_reloc[0], offset_reloc[1], offset_reloc[2]); 13233 else 13234 { 13235 load_address (tempreg, ep, &used_at); 13236 if (breg != 0) 13237 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 13238 tempreg, tempreg, breg); 13239 } 13240 offset_reloc[0] = BFD_RELOC_LO16; 13241 offset_reloc[1] = BFD_RELOC_UNUSED; 13242 offset_reloc[2] = BFD_RELOC_UNUSED; 13243 breg = tempreg; 13244 tempreg = op[0]; 13245 ep = &expr1; 13246 } 13247 else if (!ust && op[0] == breg) 13248 { 13249 used_at = 1; 13250 tempreg = AT; 13251 } 13252 else 13253 tempreg = op[0]; 13254 13255 if (off == 1) 13256 goto ulh_sh; 13257 13258 if (!target_big_endian) 13259 ep->X_add_number += off; 13260 if (offbits == 12) 13261 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); 13262 else 13263 macro_build (ep, s, "t,o(b)", tempreg, -1, 13264 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13265 13266 if (!target_big_endian) 13267 ep->X_add_number -= off; 13268 else 13269 ep->X_add_number += off; 13270 if (offbits == 12) 13271 macro_build (NULL, s2, "t,~(b)", 13272 tempreg, (int) ep->X_add_number, breg); 13273 else 13274 macro_build (ep, s2, "t,o(b)", tempreg, -1, 13275 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13276 13277 /* If necessary, move the result in tempreg to the final destination. */ 13278 if (!ust && op[0] != tempreg) 13279 { 13280 /* Protect second load's delay slot. */ 13281 load_delay_nop (); 13282 move_register (op[0], tempreg); 13283 } 13284 break; 13285 13286 ulh_sh: 13287 used_at = 1; 13288 if (target_big_endian == ust) 13289 ep->X_add_number += off; 13290 tempreg = ust || large_offset ? op[0] : AT; 13291 macro_build (ep, s, "t,o(b)", tempreg, -1, 13292 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13293 13294 /* For halfword transfers we need a temporary register to shuffle 13295 bytes. Unfortunately for M_USH_A we have none available before 13296 the next store as AT holds the base address. We deal with this 13297 case by clobbering TREG and then restoring it as with ULH. */ 13298 tempreg = ust == large_offset ? op[0] : AT; 13299 if (ust) 13300 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); 13301 13302 if (target_big_endian == ust) 13303 ep->X_add_number -= off; 13304 else 13305 ep->X_add_number += off; 13306 macro_build (ep, s2, "t,o(b)", tempreg, -1, 13307 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13308 13309 /* For M_USH_A re-retrieve the LSB. */ 13310 if (ust && large_offset) 13311 { 13312 if (target_big_endian) 13313 ep->X_add_number += off; 13314 else 13315 ep->X_add_number -= off; 13316 macro_build (&expr1, "lbu", "t,o(b)", AT, -1, 13317 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); 13318 } 13319 /* For ULH and M_USH_A OR the LSB in. */ 13320 if (!ust || large_offset) 13321 { 13322 tempreg = !large_offset ? AT : op[0]; 13323 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); 13324 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13325 } 13326 break; 13327 13328 default: 13329 /* FIXME: Check if this is one of the itbl macros, since they 13330 are added dynamically. */ 13331 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); 13332 break; 13333 } 13334 if (!mips_opts.at && used_at) 13335 as_bad (_("macro used $at after \".set noat\"")); 13336 } 13337 13338 /* Implement macros in mips16 mode. */ 13339 13340 static void 13341 mips16_macro (struct mips_cl_insn *ip) 13342 { 13343 const struct mips_operand_array *operands; 13344 int mask; 13345 int tmp; 13346 expressionS expr1; 13347 int dbl; 13348 const char *s, *s2, *s3; 13349 unsigned int op[MAX_OPERANDS]; 13350 unsigned int i; 13351 13352 mask = ip->insn_mo->mask; 13353 13354 operands = insn_operands (ip); 13355 for (i = 0; i < MAX_OPERANDS; i++) 13356 if (operands->operand[i]) 13357 op[i] = insn_extract_operand (ip, operands->operand[i]); 13358 else 13359 op[i] = -1; 13360 13361 expr1.X_op = O_constant; 13362 expr1.X_op_symbol = NULL; 13363 expr1.X_add_symbol = NULL; 13364 expr1.X_add_number = 1; 13365 13366 dbl = 0; 13367 13368 switch (mask) 13369 { 13370 default: 13371 abort (); 13372 13373 case M_DDIV_3: 13374 dbl = 1; 13375 case M_DIV_3: 13376 s = "mflo"; 13377 goto do_div3; 13378 case M_DREM_3: 13379 dbl = 1; 13380 case M_REM_3: 13381 s = "mfhi"; 13382 do_div3: 13383 start_noreorder (); 13384 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]); 13385 expr1.X_add_number = 2; 13386 macro_build (&expr1, "bnez", "x,p", op[2]); 13387 macro_build (NULL, "break", "6", 7); 13388 13389 /* FIXME: The normal code checks for of -1 / -0x80000000 here, 13390 since that causes an overflow. We should do that as well, 13391 but I don't see how to do the comparisons without a temporary 13392 register. */ 13393 end_noreorder (); 13394 macro_build (NULL, s, "x", op[0]); 13395 break; 13396 13397 case M_DIVU_3: 13398 s = "divu"; 13399 s2 = "mflo"; 13400 goto do_divu3; 13401 case M_REMU_3: 13402 s = "divu"; 13403 s2 = "mfhi"; 13404 goto do_divu3; 13405 case M_DDIVU_3: 13406 s = "ddivu"; 13407 s2 = "mflo"; 13408 goto do_divu3; 13409 case M_DREMU_3: 13410 s = "ddivu"; 13411 s2 = "mfhi"; 13412 do_divu3: 13413 start_noreorder (); 13414 macro_build (NULL, s, "0,x,y", op[1], op[2]); 13415 expr1.X_add_number = 2; 13416 macro_build (&expr1, "bnez", "x,p", op[2]); 13417 macro_build (NULL, "break", "6", 7); 13418 end_noreorder (); 13419 macro_build (NULL, s2, "x", op[0]); 13420 break; 13421 13422 case M_DMUL: 13423 dbl = 1; 13424 case M_MUL: 13425 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); 13426 macro_build (NULL, "mflo", "x", op[0]); 13427 break; 13428 13429 case M_DSUBU_I: 13430 dbl = 1; 13431 goto do_subu; 13432 case M_SUBU_I: 13433 do_subu: 13434 imm_expr.X_add_number = -imm_expr.X_add_number; 13435 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]); 13436 break; 13437 13438 case M_SUBU_I_2: 13439 imm_expr.X_add_number = -imm_expr.X_add_number; 13440 macro_build (&imm_expr, "addiu", "x,k", op[0]); 13441 break; 13442 13443 case M_DSUBU_I_2: 13444 imm_expr.X_add_number = -imm_expr.X_add_number; 13445 macro_build (&imm_expr, "daddiu", "y,j", op[0]); 13446 break; 13447 13448 case M_BEQ: 13449 s = "cmp"; 13450 s2 = "bteqz"; 13451 goto do_branch; 13452 case M_BNE: 13453 s = "cmp"; 13454 s2 = "btnez"; 13455 goto do_branch; 13456 case M_BLT: 13457 s = "slt"; 13458 s2 = "btnez"; 13459 goto do_branch; 13460 case M_BLTU: 13461 s = "sltu"; 13462 s2 = "btnez"; 13463 goto do_branch; 13464 case M_BLE: 13465 s = "slt"; 13466 s2 = "bteqz"; 13467 goto do_reverse_branch; 13468 case M_BLEU: 13469 s = "sltu"; 13470 s2 = "bteqz"; 13471 goto do_reverse_branch; 13472 case M_BGE: 13473 s = "slt"; 13474 s2 = "bteqz"; 13475 goto do_branch; 13476 case M_BGEU: 13477 s = "sltu"; 13478 s2 = "bteqz"; 13479 goto do_branch; 13480 case M_BGT: 13481 s = "slt"; 13482 s2 = "btnez"; 13483 goto do_reverse_branch; 13484 case M_BGTU: 13485 s = "sltu"; 13486 s2 = "btnez"; 13487 13488 do_reverse_branch: 13489 tmp = op[1]; 13490 op[1] = op[0]; 13491 op[0] = tmp; 13492 13493 do_branch: 13494 macro_build (NULL, s, "x,y", op[0], op[1]); 13495 macro_build (&offset_expr, s2, "p"); 13496 break; 13497 13498 case M_BEQ_I: 13499 s = "cmpi"; 13500 s2 = "bteqz"; 13501 s3 = "x,U"; 13502 goto do_branch_i; 13503 case M_BNE_I: 13504 s = "cmpi"; 13505 s2 = "btnez"; 13506 s3 = "x,U"; 13507 goto do_branch_i; 13508 case M_BLT_I: 13509 s = "slti"; 13510 s2 = "btnez"; 13511 s3 = "x,8"; 13512 goto do_branch_i; 13513 case M_BLTU_I: 13514 s = "sltiu"; 13515 s2 = "btnez"; 13516 s3 = "x,8"; 13517 goto do_branch_i; 13518 case M_BLE_I: 13519 s = "slti"; 13520 s2 = "btnez"; 13521 s3 = "x,8"; 13522 goto do_addone_branch_i; 13523 case M_BLEU_I: 13524 s = "sltiu"; 13525 s2 = "btnez"; 13526 s3 = "x,8"; 13527 goto do_addone_branch_i; 13528 case M_BGE_I: 13529 s = "slti"; 13530 s2 = "bteqz"; 13531 s3 = "x,8"; 13532 goto do_branch_i; 13533 case M_BGEU_I: 13534 s = "sltiu"; 13535 s2 = "bteqz"; 13536 s3 = "x,8"; 13537 goto do_branch_i; 13538 case M_BGT_I: 13539 s = "slti"; 13540 s2 = "bteqz"; 13541 s3 = "x,8"; 13542 goto do_addone_branch_i; 13543 case M_BGTU_I: 13544 s = "sltiu"; 13545 s2 = "bteqz"; 13546 s3 = "x,8"; 13547 13548 do_addone_branch_i: 13549 ++imm_expr.X_add_number; 13550 13551 do_branch_i: 13552 macro_build (&imm_expr, s, s3, op[0]); 13553 macro_build (&offset_expr, s2, "p"); 13554 break; 13555 13556 case M_ABS: 13557 expr1.X_add_number = 0; 13558 macro_build (&expr1, "slti", "x,8", op[1]); 13559 if (op[0] != op[1]) 13560 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); 13561 expr1.X_add_number = 2; 13562 macro_build (&expr1, "bteqz", "p"); 13563 macro_build (NULL, "neg", "x,w", op[0], op[0]); 13564 break; 13565 } 13566 } 13567 13568 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra 13569 opcode bits in *OPCODE_EXTRA. */ 13570 13571 static struct mips_opcode * 13572 mips_lookup_insn (struct hash_control *hash, const char *start, 13573 ssize_t length, unsigned int *opcode_extra) 13574 { 13575 char *name, *dot, *p; 13576 unsigned int mask, suffix; 13577 ssize_t opend; 13578 struct mips_opcode *insn; 13579 13580 /* Make a copy of the instruction so that we can fiddle with it. */ 13581 name = xstrndup (start, length); 13582 13583 /* Look up the instruction as-is. */ 13584 insn = (struct mips_opcode *) hash_find (hash, name); 13585 if (insn) 13586 goto end; 13587 13588 dot = strchr (name, '.'); 13589 if (dot && dot[1]) 13590 { 13591 /* Try to interpret the text after the dot as a VU0 channel suffix. */ 13592 p = mips_parse_vu0_channels (dot + 1, &mask); 13593 if (*p == 0 && mask != 0) 13594 { 13595 *dot = 0; 13596 insn = (struct mips_opcode *) hash_find (hash, name); 13597 *dot = '.'; 13598 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) 13599 { 13600 *opcode_extra |= mask << mips_vu0_channel_mask.lsb; 13601 goto end; 13602 } 13603 } 13604 } 13605 13606 if (mips_opts.micromips) 13607 { 13608 /* See if there's an instruction size override suffix, 13609 either `16' or `32', at the end of the mnemonic proper, 13610 that defines the operation, i.e. before the first `.' 13611 character if any. Strip it and retry. */ 13612 opend = dot != NULL ? dot - name : length; 13613 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') 13614 suffix = 2; 13615 else if (name[opend - 2] == '3' && name[opend - 1] == '2') 13616 suffix = 4; 13617 else 13618 suffix = 0; 13619 if (suffix) 13620 { 13621 memcpy (name + opend - 2, name + opend, length - opend + 1); 13622 insn = (struct mips_opcode *) hash_find (hash, name); 13623 if (insn) 13624 { 13625 forced_insn_length = suffix; 13626 goto end; 13627 } 13628 } 13629 } 13630 13631 insn = NULL; 13632 end: 13633 free (name); 13634 return insn; 13635 } 13636 13637 /* Assemble an instruction into its binary format. If the instruction 13638 is a macro, set imm_expr and offset_expr to the values associated 13639 with "I" and "A" operands respectively. Otherwise store the value 13640 of the relocatable field (if any) in offset_expr. In both cases 13641 set offset_reloc to the relocation operators applied to offset_expr. */ 13642 13643 static void 13644 mips_ip (char *str, struct mips_cl_insn *insn) 13645 { 13646 const struct mips_opcode *first, *past; 13647 struct hash_control *hash; 13648 char format; 13649 size_t end; 13650 struct mips_operand_token *tokens; 13651 unsigned int opcode_extra; 13652 13653 if (mips_opts.micromips) 13654 { 13655 hash = micromips_op_hash; 13656 past = µmips_opcodes[bfd_micromips_num_opcodes]; 13657 } 13658 else 13659 { 13660 hash = op_hash; 13661 past = &mips_opcodes[NUMOPCODES]; 13662 } 13663 forced_insn_length = 0; 13664 opcode_extra = 0; 13665 13666 /* We first try to match an instruction up to a space or to the end. */ 13667 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) 13668 continue; 13669 13670 first = mips_lookup_insn (hash, str, end, &opcode_extra); 13671 if (first == NULL) 13672 { 13673 set_insn_error (0, _("unrecognized opcode")); 13674 return; 13675 } 13676 13677 if (strcmp (first->name, "li.s") == 0) 13678 format = 'f'; 13679 else if (strcmp (first->name, "li.d") == 0) 13680 format = 'd'; 13681 else 13682 format = 0; 13683 tokens = mips_parse_arguments (str + end, format); 13684 if (!tokens) 13685 return; 13686 13687 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) 13688 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) 13689 set_insn_error (0, _("invalid operands")); 13690 13691 obstack_free (&mips_operand_tokens, tokens); 13692 } 13693 13694 /* As for mips_ip, but used when assembling MIPS16 code. 13695 Also set forced_insn_length to the resulting instruction size in 13696 bytes if the user explicitly requested a small or extended instruction. */ 13697 13698 static void 13699 mips16_ip (char *str, struct mips_cl_insn *insn) 13700 { 13701 char *end, *s, c; 13702 struct mips_opcode *first; 13703 struct mips_operand_token *tokens; 13704 13705 forced_insn_length = 0; 13706 13707 for (s = str; ISLOWER (*s); ++s) 13708 ; 13709 end = s; 13710 c = *end; 13711 switch (c) 13712 { 13713 case '\0': 13714 break; 13715 13716 case ' ': 13717 s++; 13718 break; 13719 13720 case '.': 13721 if (s[1] == 't' && s[2] == ' ') 13722 { 13723 forced_insn_length = 2; 13724 s += 3; 13725 break; 13726 } 13727 else if (s[1] == 'e' && s[2] == ' ') 13728 { 13729 forced_insn_length = 4; 13730 s += 3; 13731 break; 13732 } 13733 /* Fall through. */ 13734 default: 13735 set_insn_error (0, _("unrecognized opcode")); 13736 return; 13737 } 13738 13739 if (mips_opts.noautoextend && !forced_insn_length) 13740 forced_insn_length = 2; 13741 13742 *end = 0; 13743 first = (struct mips_opcode *) hash_find (mips16_op_hash, str); 13744 *end = c; 13745 13746 if (!first) 13747 { 13748 set_insn_error (0, _("unrecognized opcode")); 13749 return; 13750 } 13751 13752 tokens = mips_parse_arguments (s, 0); 13753 if (!tokens) 13754 return; 13755 13756 if (!match_mips16_insns (insn, first, tokens)) 13757 set_insn_error (0, _("invalid operands")); 13758 13759 obstack_free (&mips_operand_tokens, tokens); 13760 } 13761 13762 /* Marshal immediate value VAL for an extended MIPS16 instruction. 13763 NBITS is the number of significant bits in VAL. */ 13764 13765 static unsigned long 13766 mips16_immed_extend (offsetT val, unsigned int nbits) 13767 { 13768 int extval; 13769 if (nbits == 16) 13770 { 13771 extval = ((val >> 11) & 0x1f) | (val & 0x7e0); 13772 val &= 0x1f; 13773 } 13774 else if (nbits == 15) 13775 { 13776 extval = ((val >> 11) & 0xf) | (val & 0x7f0); 13777 val &= 0xf; 13778 } 13779 else 13780 { 13781 extval = ((val & 0x1f) << 6) | (val & 0x20); 13782 val = 0; 13783 } 13784 return (extval << 16) | val; 13785 } 13786 13787 /* Like decode_mips16_operand, but require the operand to be defined and 13788 require it to be an integer. */ 13789 13790 static const struct mips_int_operand * 13791 mips16_immed_operand (int type, bfd_boolean extended_p) 13792 { 13793 const struct mips_operand *operand; 13794 13795 operand = decode_mips16_operand (type, extended_p); 13796 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) 13797 abort (); 13798 return (const struct mips_int_operand *) operand; 13799 } 13800 13801 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ 13802 13803 static bfd_boolean 13804 mips16_immed_in_range_p (const struct mips_int_operand *operand, 13805 bfd_reloc_code_real_type reloc, offsetT sval) 13806 { 13807 int min_val, max_val; 13808 13809 min_val = mips_int_operand_min (operand); 13810 max_val = mips_int_operand_max (operand); 13811 if (reloc != BFD_RELOC_UNUSED) 13812 { 13813 if (min_val < 0) 13814 sval = SEXT_16BIT (sval); 13815 else 13816 sval &= 0xffff; 13817 } 13818 13819 return (sval >= min_val 13820 && sval <= max_val 13821 && (sval & ((1 << operand->shift) - 1)) == 0); 13822 } 13823 13824 /* Install immediate value VAL into MIPS16 instruction *INSN, 13825 extending it if necessary. The instruction in *INSN may 13826 already be extended. 13827 13828 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED 13829 if none. In the former case, VAL is a 16-bit number with no 13830 defined signedness. 13831 13832 TYPE is the type of the immediate field. USER_INSN_LENGTH 13833 is the length that the user requested, or 0 if none. */ 13834 13835 static void 13836 mips16_immed (const char *file, unsigned int line, int type, 13837 bfd_reloc_code_real_type reloc, offsetT val, 13838 unsigned int user_insn_length, unsigned long *insn) 13839 { 13840 const struct mips_int_operand *operand; 13841 unsigned int uval, length; 13842 13843 operand = mips16_immed_operand (type, FALSE); 13844 if (!mips16_immed_in_range_p (operand, reloc, val)) 13845 { 13846 /* We need an extended instruction. */ 13847 if (user_insn_length == 2) 13848 as_bad_where (file, line, _("invalid unextended operand value")); 13849 else 13850 *insn |= MIPS16_EXTEND; 13851 } 13852 else if (user_insn_length == 4) 13853 { 13854 /* The operand doesn't force an unextended instruction to be extended. 13855 Warn if the user wanted an extended instruction anyway. */ 13856 *insn |= MIPS16_EXTEND; 13857 as_warn_where (file, line, 13858 _("extended operand requested but not required")); 13859 } 13860 13861 length = mips16_opcode_length (*insn); 13862 if (length == 4) 13863 { 13864 operand = mips16_immed_operand (type, TRUE); 13865 if (!mips16_immed_in_range_p (operand, reloc, val)) 13866 as_bad_where (file, line, 13867 _("operand value out of range for instruction")); 13868 } 13869 uval = ((unsigned int) val >> operand->shift) - operand->bias; 13870 if (length == 2) 13871 *insn = mips_insert_operand (&operand->root, *insn, uval); 13872 else 13873 *insn |= mips16_immed_extend (uval, operand->root.size); 13874 } 13875 13876 struct percent_op_match 13878 { 13879 const char *str; 13880 bfd_reloc_code_real_type reloc; 13881 }; 13882 13883 static const struct percent_op_match mips_percent_op[] = 13884 { 13885 {"%lo", BFD_RELOC_LO16}, 13886 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, 13887 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, 13888 {"%call16", BFD_RELOC_MIPS_CALL16}, 13889 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, 13890 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, 13891 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, 13892 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, 13893 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, 13894 {"%got", BFD_RELOC_MIPS_GOT16}, 13895 {"%gp_rel", BFD_RELOC_GPREL16}, 13896 {"%half", BFD_RELOC_16}, 13897 {"%highest", BFD_RELOC_MIPS_HIGHEST}, 13898 {"%higher", BFD_RELOC_MIPS_HIGHER}, 13899 {"%neg", BFD_RELOC_MIPS_SUB}, 13900 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, 13901 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, 13902 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, 13903 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, 13904 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, 13905 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, 13906 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, 13907 {"%hi", BFD_RELOC_HI16_S}, 13908 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, 13909 {"%pcrel_lo", BFD_RELOC_LO16_PCREL} 13910 }; 13911 13912 static const struct percent_op_match mips16_percent_op[] = 13913 { 13914 {"%lo", BFD_RELOC_MIPS16_LO16}, 13915 {"%gprel", BFD_RELOC_MIPS16_GPREL}, 13916 {"%got", BFD_RELOC_MIPS16_GOT16}, 13917 {"%call16", BFD_RELOC_MIPS16_CALL16}, 13918 {"%hi", BFD_RELOC_MIPS16_HI16_S}, 13919 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, 13920 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, 13921 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, 13922 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, 13923 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, 13924 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, 13925 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} 13926 }; 13927 13928 13929 /* Return true if *STR points to a relocation operator. When returning true, 13930 move *STR over the operator and store its relocation code in *RELOC. 13931 Leave both *STR and *RELOC alone when returning false. */ 13932 13933 static bfd_boolean 13934 parse_relocation (char **str, bfd_reloc_code_real_type *reloc) 13935 { 13936 const struct percent_op_match *percent_op; 13937 size_t limit, i; 13938 13939 if (mips_opts.mips16) 13940 { 13941 percent_op = mips16_percent_op; 13942 limit = ARRAY_SIZE (mips16_percent_op); 13943 } 13944 else 13945 { 13946 percent_op = mips_percent_op; 13947 limit = ARRAY_SIZE (mips_percent_op); 13948 } 13949 13950 for (i = 0; i < limit; i++) 13951 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) 13952 { 13953 int len = strlen (percent_op[i].str); 13954 13955 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 13956 continue; 13957 13958 *str += strlen (percent_op[i].str); 13959 *reloc = percent_op[i].reloc; 13960 13961 /* Check whether the output BFD supports this relocation. 13962 If not, issue an error and fall back on something safe. */ 13963 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) 13964 { 13965 as_bad (_("relocation %s isn't supported by the current ABI"), 13966 percent_op[i].str); 13967 *reloc = BFD_RELOC_UNUSED; 13968 } 13969 return TRUE; 13970 } 13971 return FALSE; 13972 } 13973 13974 13975 /* Parse string STR as a 16-bit relocatable operand. Store the 13976 expression in *EP and the relocations in the array starting 13977 at RELOC. Return the number of relocation operators used. 13978 13979 On exit, EXPR_END points to the first character after the expression. */ 13980 13981 static size_t 13982 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 13983 char *str) 13984 { 13985 bfd_reloc_code_real_type reversed_reloc[3]; 13986 size_t reloc_index, i; 13987 int crux_depth, str_depth; 13988 char *crux; 13989 13990 /* Search for the start of the main expression, recoding relocations 13991 in REVERSED_RELOC. End the loop with CRUX pointing to the start 13992 of the main expression and with CRUX_DEPTH containing the number 13993 of open brackets at that point. */ 13994 reloc_index = -1; 13995 str_depth = 0; 13996 do 13997 { 13998 reloc_index++; 13999 crux = str; 14000 crux_depth = str_depth; 14001 14002 /* Skip over whitespace and brackets, keeping count of the number 14003 of brackets. */ 14004 while (*str == ' ' || *str == '\t' || *str == '(') 14005 if (*str++ == '(') 14006 str_depth++; 14007 } 14008 while (*str == '%' 14009 && reloc_index < (HAVE_NEWABI ? 3 : 1) 14010 && parse_relocation (&str, &reversed_reloc[reloc_index])); 14011 14012 my_getExpression (ep, crux); 14013 str = expr_end; 14014 14015 /* Match every open bracket. */ 14016 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 14017 if (*str++ == ')') 14018 crux_depth--; 14019 14020 if (crux_depth > 0) 14021 as_bad (_("unclosed '('")); 14022 14023 expr_end = str; 14024 14025 if (reloc_index != 0) 14026 { 14027 prev_reloc_op_frag = frag_now; 14028 for (i = 0; i < reloc_index; i++) 14029 reloc[i] = reversed_reloc[reloc_index - 1 - i]; 14030 } 14031 14032 return reloc_index; 14033 } 14034 14035 static void 14036 my_getExpression (expressionS *ep, char *str) 14037 { 14038 char *save_in; 14039 14040 save_in = input_line_pointer; 14041 input_line_pointer = str; 14042 expression (ep); 14043 expr_end = input_line_pointer; 14044 input_line_pointer = save_in; 14045 } 14046 14047 const char * 14048 md_atof (int type, char *litP, int *sizeP) 14049 { 14050 return ieee_md_atof (type, litP, sizeP, target_big_endian); 14051 } 14052 14053 void 14054 md_number_to_chars (char *buf, valueT val, int n) 14055 { 14056 if (target_big_endian) 14057 number_to_chars_bigendian (buf, val, n); 14058 else 14059 number_to_chars_littleendian (buf, val, n); 14060 } 14061 14062 static int support_64bit_objects(void) 14064 { 14065 const char **list, **l; 14066 int yes; 14067 14068 list = bfd_target_list (); 14069 for (l = list; *l != NULL; l++) 14070 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 14071 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) 14072 break; 14073 yes = (*l != NULL); 14074 free (list); 14075 return yes; 14076 } 14077 14078 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to 14079 NEW_VALUE. Warn if another value was already specified. Note: 14080 we have to defer parsing the -march and -mtune arguments in order 14081 to handle 'from-abi' correctly, since the ABI might be specified 14082 in a later argument. */ 14083 14084 static void 14085 mips_set_option_string (const char **string_ptr, const char *new_value) 14086 { 14087 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) 14088 as_warn (_("a different %s was already specified, is now %s"), 14089 string_ptr == &mips_arch_string ? "-march" : "-mtune", 14090 new_value); 14091 14092 *string_ptr = new_value; 14093 } 14094 14095 int 14096 md_parse_option (int c, const char *arg) 14097 { 14098 unsigned int i; 14099 14100 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 14101 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) 14102 { 14103 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, 14104 c == mips_ases[i].option_on); 14105 return 1; 14106 } 14107 14108 switch (c) 14109 { 14110 case OPTION_CONSTRUCT_FLOATS: 14111 mips_disable_float_construction = 0; 14112 break; 14113 14114 case OPTION_NO_CONSTRUCT_FLOATS: 14115 mips_disable_float_construction = 1; 14116 break; 14117 14118 case OPTION_TRAP: 14119 mips_trap = 1; 14120 break; 14121 14122 case OPTION_BREAK: 14123 mips_trap = 0; 14124 break; 14125 14126 case OPTION_EB: 14127 target_big_endian = 1; 14128 break; 14129 14130 case OPTION_EL: 14131 target_big_endian = 0; 14132 break; 14133 14134 case 'O': 14135 if (arg == NULL) 14136 mips_optimize = 1; 14137 else if (arg[0] == '0') 14138 mips_optimize = 0; 14139 else if (arg[0] == '1') 14140 mips_optimize = 1; 14141 else 14142 mips_optimize = 2; 14143 break; 14144 14145 case 'g': 14146 if (arg == NULL) 14147 mips_debug = 2; 14148 else 14149 mips_debug = atoi (arg); 14150 break; 14151 14152 case OPTION_MIPS1: 14153 file_mips_opts.isa = ISA_MIPS1; 14154 break; 14155 14156 case OPTION_MIPS2: 14157 file_mips_opts.isa = ISA_MIPS2; 14158 break; 14159 14160 case OPTION_MIPS3: 14161 file_mips_opts.isa = ISA_MIPS3; 14162 break; 14163 14164 case OPTION_MIPS4: 14165 file_mips_opts.isa = ISA_MIPS4; 14166 break; 14167 14168 case OPTION_MIPS5: 14169 file_mips_opts.isa = ISA_MIPS5; 14170 break; 14171 14172 case OPTION_MIPS32: 14173 file_mips_opts.isa = ISA_MIPS32; 14174 break; 14175 14176 case OPTION_MIPS32R2: 14177 file_mips_opts.isa = ISA_MIPS32R2; 14178 break; 14179 14180 case OPTION_MIPS32R3: 14181 file_mips_opts.isa = ISA_MIPS32R3; 14182 break; 14183 14184 case OPTION_MIPS32R5: 14185 file_mips_opts.isa = ISA_MIPS32R5; 14186 break; 14187 14188 case OPTION_MIPS32R6: 14189 file_mips_opts.isa = ISA_MIPS32R6; 14190 break; 14191 14192 case OPTION_MIPS64R2: 14193 file_mips_opts.isa = ISA_MIPS64R2; 14194 break; 14195 14196 case OPTION_MIPS64R3: 14197 file_mips_opts.isa = ISA_MIPS64R3; 14198 break; 14199 14200 case OPTION_MIPS64R5: 14201 file_mips_opts.isa = ISA_MIPS64R5; 14202 break; 14203 14204 case OPTION_MIPS64R6: 14205 file_mips_opts.isa = ISA_MIPS64R6; 14206 break; 14207 14208 case OPTION_MIPS64: 14209 file_mips_opts.isa = ISA_MIPS64; 14210 break; 14211 14212 case OPTION_MTUNE: 14213 mips_set_option_string (&mips_tune_string, arg); 14214 break; 14215 14216 case OPTION_MARCH: 14217 mips_set_option_string (&mips_arch_string, arg); 14218 break; 14219 14220 case OPTION_M4650: 14221 mips_set_option_string (&mips_arch_string, "4650"); 14222 mips_set_option_string (&mips_tune_string, "4650"); 14223 break; 14224 14225 case OPTION_NO_M4650: 14226 break; 14227 14228 case OPTION_M4010: 14229 mips_set_option_string (&mips_arch_string, "4010"); 14230 mips_set_option_string (&mips_tune_string, "4010"); 14231 break; 14232 14233 case OPTION_NO_M4010: 14234 break; 14235 14236 case OPTION_M4100: 14237 mips_set_option_string (&mips_arch_string, "4100"); 14238 mips_set_option_string (&mips_tune_string, "4100"); 14239 break; 14240 14241 case OPTION_NO_M4100: 14242 break; 14243 14244 case OPTION_M3900: 14245 mips_set_option_string (&mips_arch_string, "3900"); 14246 mips_set_option_string (&mips_tune_string, "3900"); 14247 break; 14248 14249 case OPTION_NO_M3900: 14250 break; 14251 14252 case OPTION_MICROMIPS: 14253 if (file_mips_opts.mips16 == 1) 14254 { 14255 as_bad (_("-mmicromips cannot be used with -mips16")); 14256 return 0; 14257 } 14258 file_mips_opts.micromips = 1; 14259 mips_no_prev_insn (); 14260 break; 14261 14262 case OPTION_NO_MICROMIPS: 14263 file_mips_opts.micromips = 0; 14264 mips_no_prev_insn (); 14265 break; 14266 14267 case OPTION_MIPS16: 14268 if (file_mips_opts.micromips == 1) 14269 { 14270 as_bad (_("-mips16 cannot be used with -micromips")); 14271 return 0; 14272 } 14273 file_mips_opts.mips16 = 1; 14274 mips_no_prev_insn (); 14275 break; 14276 14277 case OPTION_NO_MIPS16: 14278 file_mips_opts.mips16 = 0; 14279 mips_no_prev_insn (); 14280 break; 14281 14282 case OPTION_FIX_24K: 14283 mips_fix_24k = 1; 14284 break; 14285 14286 case OPTION_NO_FIX_24K: 14287 mips_fix_24k = 0; 14288 break; 14289 14290 case OPTION_FIX_RM7000: 14291 mips_fix_rm7000 = 1; 14292 break; 14293 14294 case OPTION_NO_FIX_RM7000: 14295 mips_fix_rm7000 = 0; 14296 break; 14297 14298 case OPTION_FIX_LOONGSON2F_JUMP: 14299 mips_fix_loongson2f_jump = TRUE; 14300 break; 14301 14302 case OPTION_NO_FIX_LOONGSON2F_JUMP: 14303 mips_fix_loongson2f_jump = FALSE; 14304 break; 14305 14306 case OPTION_FIX_LOONGSON2F_NOP: 14307 mips_fix_loongson2f_nop = TRUE; 14308 break; 14309 14310 case OPTION_NO_FIX_LOONGSON2F_NOP: 14311 mips_fix_loongson2f_nop = FALSE; 14312 break; 14313 14314 case OPTION_FIX_VR4120: 14315 mips_fix_vr4120 = 1; 14316 break; 14317 14318 case OPTION_NO_FIX_VR4120: 14319 mips_fix_vr4120 = 0; 14320 break; 14321 14322 case OPTION_FIX_VR4130: 14323 mips_fix_vr4130 = 1; 14324 break; 14325 14326 case OPTION_NO_FIX_VR4130: 14327 mips_fix_vr4130 = 0; 14328 break; 14329 14330 case OPTION_FIX_CN63XXP1: 14331 mips_fix_cn63xxp1 = TRUE; 14332 break; 14333 14334 case OPTION_NO_FIX_CN63XXP1: 14335 mips_fix_cn63xxp1 = FALSE; 14336 break; 14337 14338 case OPTION_RELAX_BRANCH: 14339 mips_relax_branch = 1; 14340 break; 14341 14342 case OPTION_NO_RELAX_BRANCH: 14343 mips_relax_branch = 0; 14344 break; 14345 14346 case OPTION_INSN32: 14347 file_mips_opts.insn32 = TRUE; 14348 break; 14349 14350 case OPTION_NO_INSN32: 14351 file_mips_opts.insn32 = FALSE; 14352 break; 14353 14354 case OPTION_MSHARED: 14355 mips_in_shared = TRUE; 14356 break; 14357 14358 case OPTION_MNO_SHARED: 14359 mips_in_shared = FALSE; 14360 break; 14361 14362 case OPTION_MSYM32: 14363 file_mips_opts.sym32 = TRUE; 14364 break; 14365 14366 case OPTION_MNO_SYM32: 14367 file_mips_opts.sym32 = FALSE; 14368 break; 14369 14370 /* When generating ELF code, we permit -KPIC and -call_shared to 14371 select SVR4_PIC, and -non_shared to select no PIC. This is 14372 intended to be compatible with Irix 5. */ 14373 case OPTION_CALL_SHARED: 14374 mips_pic = SVR4_PIC; 14375 mips_abicalls = TRUE; 14376 break; 14377 14378 case OPTION_CALL_NONPIC: 14379 mips_pic = NO_PIC; 14380 mips_abicalls = TRUE; 14381 break; 14382 14383 case OPTION_NON_SHARED: 14384 mips_pic = NO_PIC; 14385 mips_abicalls = FALSE; 14386 break; 14387 14388 /* The -xgot option tells the assembler to use 32 bit offsets 14389 when accessing the got in SVR4_PIC mode. It is for Irix 14390 compatibility. */ 14391 case OPTION_XGOT: 14392 mips_big_got = 1; 14393 break; 14394 14395 case 'G': 14396 g_switch_value = atoi (arg); 14397 g_switch_seen = 1; 14398 break; 14399 14400 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 14401 and -mabi=64. */ 14402 case OPTION_32: 14403 mips_abi = O32_ABI; 14404 break; 14405 14406 case OPTION_N32: 14407 mips_abi = N32_ABI; 14408 break; 14409 14410 case OPTION_64: 14411 mips_abi = N64_ABI; 14412 if (!support_64bit_objects()) 14413 as_fatal (_("no compiled in support for 64 bit object file format")); 14414 break; 14415 14416 case OPTION_GP32: 14417 file_mips_opts.gp = 32; 14418 break; 14419 14420 case OPTION_GP64: 14421 file_mips_opts.gp = 64; 14422 break; 14423 14424 case OPTION_FP32: 14425 file_mips_opts.fp = 32; 14426 break; 14427 14428 case OPTION_FPXX: 14429 file_mips_opts.fp = 0; 14430 break; 14431 14432 case OPTION_FP64: 14433 file_mips_opts.fp = 64; 14434 break; 14435 14436 case OPTION_ODD_SPREG: 14437 file_mips_opts.oddspreg = 1; 14438 break; 14439 14440 case OPTION_NO_ODD_SPREG: 14441 file_mips_opts.oddspreg = 0; 14442 break; 14443 14444 case OPTION_SINGLE_FLOAT: 14445 file_mips_opts.single_float = 1; 14446 break; 14447 14448 case OPTION_DOUBLE_FLOAT: 14449 file_mips_opts.single_float = 0; 14450 break; 14451 14452 case OPTION_SOFT_FLOAT: 14453 file_mips_opts.soft_float = 1; 14454 break; 14455 14456 case OPTION_HARD_FLOAT: 14457 file_mips_opts.soft_float = 0; 14458 break; 14459 14460 case OPTION_MABI: 14461 if (strcmp (arg, "32") == 0) 14462 mips_abi = O32_ABI; 14463 else if (strcmp (arg, "o64") == 0) 14464 mips_abi = O64_ABI; 14465 else if (strcmp (arg, "n32") == 0) 14466 mips_abi = N32_ABI; 14467 else if (strcmp (arg, "64") == 0) 14468 { 14469 mips_abi = N64_ABI; 14470 if (! support_64bit_objects()) 14471 as_fatal (_("no compiled in support for 64 bit object file " 14472 "format")); 14473 } 14474 else if (strcmp (arg, "eabi") == 0) 14475 mips_abi = EABI_ABI; 14476 else 14477 { 14478 as_fatal (_("invalid abi -mabi=%s"), arg); 14479 return 0; 14480 } 14481 break; 14482 14483 case OPTION_M7000_HILO_FIX: 14484 mips_7000_hilo_fix = TRUE; 14485 break; 14486 14487 case OPTION_MNO_7000_HILO_FIX: 14488 mips_7000_hilo_fix = FALSE; 14489 break; 14490 14491 case OPTION_MDEBUG: 14492 mips_flag_mdebug = TRUE; 14493 break; 14494 14495 case OPTION_NO_MDEBUG: 14496 mips_flag_mdebug = FALSE; 14497 break; 14498 14499 case OPTION_PDR: 14500 mips_flag_pdr = TRUE; 14501 break; 14502 14503 case OPTION_NO_PDR: 14504 mips_flag_pdr = FALSE; 14505 break; 14506 14507 case OPTION_MVXWORKS_PIC: 14508 mips_pic = VXWORKS_PIC; 14509 break; 14510 14511 case OPTION_NAN: 14512 if (strcmp (arg, "2008") == 0) 14513 mips_nan2008 = 1; 14514 else if (strcmp (arg, "legacy") == 0) 14515 mips_nan2008 = 0; 14516 else 14517 { 14518 as_fatal (_("invalid NaN setting -mnan=%s"), arg); 14519 return 0; 14520 } 14521 break; 14522 14523 default: 14524 return 0; 14525 } 14526 14527 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; 14528 14529 return 1; 14530 } 14531 14532 /* Set up globals to tune for the ISA or processor described by INFO. */ 14534 14535 static void 14536 mips_set_tune (const struct mips_cpu_info *info) 14537 { 14538 if (info != 0) 14539 mips_tune = info->cpu; 14540 } 14541 14542 14543 void 14544 mips_after_parse_args (void) 14545 { 14546 const struct mips_cpu_info *arch_info = 0; 14547 const struct mips_cpu_info *tune_info = 0; 14548 14549 /* GP relative stuff not working for PE */ 14550 if (strncmp (TARGET_OS, "pe", 2) == 0) 14551 { 14552 if (g_switch_seen && g_switch_value != 0) 14553 as_bad (_("-G not supported in this configuration")); 14554 g_switch_value = 0; 14555 } 14556 14557 if (mips_abi == NO_ABI) 14558 mips_abi = MIPS_DEFAULT_ABI; 14559 14560 /* The following code determines the architecture. 14561 Similar code was added to GCC 3.3 (see override_options() in 14562 config/mips/mips.c). The GAS and GCC code should be kept in sync 14563 as much as possible. */ 14564 14565 if (mips_arch_string != 0) 14566 arch_info = mips_parse_cpu ("-march", mips_arch_string); 14567 14568 if (file_mips_opts.isa != ISA_UNKNOWN) 14569 { 14570 /* Handle -mipsN. At this point, file_mips_opts.isa contains the 14571 ISA level specified by -mipsN, while arch_info->isa contains 14572 the -march selection (if any). */ 14573 if (arch_info != 0) 14574 { 14575 /* -march takes precedence over -mipsN, since it is more descriptive. 14576 There's no harm in specifying both as long as the ISA levels 14577 are the same. */ 14578 if (file_mips_opts.isa != arch_info->isa) 14579 as_bad (_("-%s conflicts with the other architecture options," 14580 " which imply -%s"), 14581 mips_cpu_info_from_isa (file_mips_opts.isa)->name, 14582 mips_cpu_info_from_isa (arch_info->isa)->name); 14583 } 14584 else 14585 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); 14586 } 14587 14588 if (arch_info == 0) 14589 { 14590 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); 14591 gas_assert (arch_info); 14592 } 14593 14594 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) 14595 as_bad (_("-march=%s is not compatible with the selected ABI"), 14596 arch_info->name); 14597 14598 file_mips_opts.arch = arch_info->cpu; 14599 file_mips_opts.isa = arch_info->isa; 14600 14601 /* Set up initial mips_opts state. */ 14602 mips_opts = file_mips_opts; 14603 14604 /* The register size inference code is now placed in 14605 file_mips_check_options. */ 14606 14607 /* Optimize for file_mips_opts.arch, unless -mtune selects a different 14608 processor. */ 14609 if (mips_tune_string != 0) 14610 tune_info = mips_parse_cpu ("-mtune", mips_tune_string); 14611 14612 if (tune_info == 0) 14613 mips_set_tune (arch_info); 14614 else 14615 mips_set_tune (tune_info); 14616 14617 if (mips_flag_mdebug < 0) 14618 mips_flag_mdebug = 0; 14619 } 14620 14621 void 14623 mips_init_after_args (void) 14624 { 14625 /* initialize opcodes */ 14626 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; 14627 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; 14628 } 14629 14630 long 14631 md_pcrel_from (fixS *fixP) 14632 { 14633 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 14634 switch (fixP->fx_r_type) 14635 { 14636 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 14637 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 14638 /* Return the address of the delay slot. */ 14639 return addr + 2; 14640 14641 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 14642 case BFD_RELOC_MICROMIPS_JMP: 14643 case BFD_RELOC_MIPS16_16_PCREL_S1: 14644 case BFD_RELOC_16_PCREL_S2: 14645 case BFD_RELOC_MIPS_21_PCREL_S2: 14646 case BFD_RELOC_MIPS_26_PCREL_S2: 14647 case BFD_RELOC_MIPS_JMP: 14648 /* Return the address of the delay slot. */ 14649 return addr + 4; 14650 14651 case BFD_RELOC_MIPS_18_PCREL_S3: 14652 /* Return the aligned address of the doubleword containing 14653 the instruction. */ 14654 return addr & ~7; 14655 14656 default: 14657 return addr; 14658 } 14659 } 14660 14661 /* This is called before the symbol table is processed. In order to 14662 work with gcc when using mips-tfile, we must keep all local labels. 14663 However, in other cases, we want to discard them. If we were 14664 called with -g, but we didn't see any debugging information, it may 14665 mean that gcc is smuggling debugging information through to 14666 mips-tfile, in which case we must generate all local labels. */ 14667 14668 void 14669 mips_frob_file_before_adjust (void) 14670 { 14671 #ifndef NO_ECOFF_DEBUGGING 14672 if (ECOFF_DEBUGGING 14673 && mips_debug != 0 14674 && ! ecoff_debugging_seen) 14675 flag_keep_locals = 1; 14676 #endif 14677 } 14678 14679 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede 14680 the corresponding LO16 reloc. This is called before md_apply_fix and 14681 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit 14682 relocation operators. 14683 14684 For our purposes, a %lo() expression matches a %got() or %hi() 14685 expression if: 14686 14687 (a) it refers to the same symbol; and 14688 (b) the offset applied in the %lo() expression is no lower than 14689 the offset applied in the %got() or %hi(). 14690 14691 (b) allows us to cope with code like: 14692 14693 lui $4,%hi(foo) 14694 lh $4,%lo(foo+2)($4) 14695 14696 ...which is legal on RELA targets, and has a well-defined behaviour 14697 if the user knows that adding 2 to "foo" will not induce a carry to 14698 the high 16 bits. 14699 14700 When several %lo()s match a particular %got() or %hi(), we use the 14701 following rules to distinguish them: 14702 14703 (1) %lo()s with smaller offsets are a better match than %lo()s with 14704 higher offsets. 14705 14706 (2) %lo()s with no matching %got() or %hi() are better than those 14707 that already have a matching %got() or %hi(). 14708 14709 (3) later %lo()s are better than earlier %lo()s. 14710 14711 These rules are applied in order. 14712 14713 (1) means, among other things, that %lo()s with identical offsets are 14714 chosen if they exist. 14715 14716 (2) means that we won't associate several high-part relocations with 14717 the same low-part relocation unless there's no alternative. Having 14718 several high parts for the same low part is a GNU extension; this rule 14719 allows careful users to avoid it. 14720 14721 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, 14722 with the last high-part relocation being at the front of the list. 14723 It therefore makes sense to choose the last matching low-part 14724 relocation, all other things being equal. It's also easier 14725 to code that way. */ 14726 14727 void 14728 mips_frob_file (void) 14729 { 14730 struct mips_hi_fixup *l; 14731 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; 14732 14733 for (l = mips_hi_fixup_list; l != NULL; l = l->next) 14734 { 14735 segment_info_type *seginfo; 14736 bfd_boolean matched_lo_p; 14737 fixS **hi_pos, **lo_pos, **pos; 14738 14739 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); 14740 14741 /* If a GOT16 relocation turns out to be against a global symbol, 14742 there isn't supposed to be a matching LO. Ignore %gots against 14743 constants; we'll report an error for those later. */ 14744 if (got16_reloc_p (l->fixp->fx_r_type) 14745 && !(l->fixp->fx_addsy 14746 && pic_need_relax (l->fixp->fx_addsy, l->seg))) 14747 continue; 14748 14749 /* Check quickly whether the next fixup happens to be a matching %lo. */ 14750 if (fixup_has_matching_lo_p (l->fixp)) 14751 continue; 14752 14753 seginfo = seg_info (l->seg); 14754 14755 /* Set HI_POS to the position of this relocation in the chain. 14756 Set LO_POS to the position of the chosen low-part relocation. 14757 MATCHED_LO_P is true on entry to the loop if *POS is a low-part 14758 relocation that matches an immediately-preceding high-part 14759 relocation. */ 14760 hi_pos = NULL; 14761 lo_pos = NULL; 14762 matched_lo_p = FALSE; 14763 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); 14764 14765 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) 14766 { 14767 if (*pos == l->fixp) 14768 hi_pos = pos; 14769 14770 if ((*pos)->fx_r_type == looking_for_rtype 14771 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) 14772 && (*pos)->fx_offset >= l->fixp->fx_offset 14773 && (lo_pos == NULL 14774 || (*pos)->fx_offset < (*lo_pos)->fx_offset 14775 || (!matched_lo_p 14776 && (*pos)->fx_offset == (*lo_pos)->fx_offset))) 14777 lo_pos = pos; 14778 14779 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) 14780 && fixup_has_matching_lo_p (*pos)); 14781 } 14782 14783 /* If we found a match, remove the high-part relocation from its 14784 current position and insert it before the low-part relocation. 14785 Make the offsets match so that fixup_has_matching_lo_p() 14786 will return true. 14787 14788 We don't warn about unmatched high-part relocations since some 14789 versions of gcc have been known to emit dead "lui ...%hi(...)" 14790 instructions. */ 14791 if (lo_pos != NULL) 14792 { 14793 l->fixp->fx_offset = (*lo_pos)->fx_offset; 14794 if (l->fixp->fx_next != *lo_pos) 14795 { 14796 *hi_pos = l->fixp->fx_next; 14797 l->fixp->fx_next = *lo_pos; 14798 *lo_pos = l->fixp; 14799 } 14800 } 14801 } 14802 } 14803 14804 int 14805 mips_force_relocation (fixS *fixp) 14806 { 14807 if (generic_force_reloc (fixp)) 14808 return 1; 14809 14810 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, 14811 so that the linker relaxation can update targets. */ 14812 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 14813 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 14814 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) 14815 return 1; 14816 14817 /* We want all PC-relative relocations to be kept for R6 relaxation. */ 14818 if (ISA_IS_R6 (file_mips_opts.isa) 14819 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 14820 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 14821 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 14822 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 14823 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 14824 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 14825 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) 14826 return 1; 14827 14828 return 0; 14829 } 14830 14831 /* Read the instruction associated with RELOC from BUF. */ 14832 14833 static unsigned int 14834 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) 14835 { 14836 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 14837 return read_compressed_insn (buf, 4); 14838 else 14839 return read_insn (buf); 14840 } 14841 14842 /* Write instruction INSN to BUF, given that it has been relocated 14843 by RELOC. */ 14844 14845 static void 14846 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, 14847 unsigned long insn) 14848 { 14849 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 14850 write_compressed_insn (buf, insn, 4); 14851 else 14852 write_insn (buf, insn); 14853 } 14854 14855 /* Apply a fixup to the object file. */ 14856 14857 void 14858 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 14859 { 14860 char *buf; 14861 unsigned long insn; 14862 reloc_howto_type *howto; 14863 14864 if (fixP->fx_pcrel) 14865 switch (fixP->fx_r_type) 14866 { 14867 case BFD_RELOC_16_PCREL_S2: 14868 case BFD_RELOC_MIPS16_16_PCREL_S1: 14869 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 14870 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 14871 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 14872 case BFD_RELOC_32_PCREL: 14873 case BFD_RELOC_MIPS_21_PCREL_S2: 14874 case BFD_RELOC_MIPS_26_PCREL_S2: 14875 case BFD_RELOC_MIPS_18_PCREL_S3: 14876 case BFD_RELOC_MIPS_19_PCREL_S2: 14877 case BFD_RELOC_HI16_S_PCREL: 14878 case BFD_RELOC_LO16_PCREL: 14879 break; 14880 14881 case BFD_RELOC_32: 14882 fixP->fx_r_type = BFD_RELOC_32_PCREL; 14883 break; 14884 14885 default: 14886 as_bad_where (fixP->fx_file, fixP->fx_line, 14887 _("PC-relative reference to a different section")); 14888 break; 14889 } 14890 14891 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations 14892 that have no MIPS ELF equivalent. */ 14893 if (fixP->fx_r_type != BFD_RELOC_8) 14894 { 14895 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 14896 if (!howto) 14897 return; 14898 } 14899 14900 gas_assert (fixP->fx_size == 2 14901 || fixP->fx_size == 4 14902 || fixP->fx_r_type == BFD_RELOC_8 14903 || fixP->fx_r_type == BFD_RELOC_16 14904 || fixP->fx_r_type == BFD_RELOC_64 14905 || fixP->fx_r_type == BFD_RELOC_CTOR 14906 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB 14907 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB 14908 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 14909 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 14910 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 14911 || fixP->fx_r_type == BFD_RELOC_NONE); 14912 14913 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 14914 14915 /* Don't treat parts of a composite relocation as done. There are two 14916 reasons for this: 14917 14918 (1) The second and third parts will be against 0 (RSS_UNDEF) but 14919 should nevertheless be emitted if the first part is. 14920 14921 (2) In normal usage, composite relocations are never assembly-time 14922 constants. The easiest way of dealing with the pathological 14923 exceptions is to generate a relocation against STN_UNDEF and 14924 leave everything up to the linker. */ 14925 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) 14926 fixP->fx_done = 1; 14927 14928 switch (fixP->fx_r_type) 14929 { 14930 case BFD_RELOC_MIPS_TLS_GD: 14931 case BFD_RELOC_MIPS_TLS_LDM: 14932 case BFD_RELOC_MIPS_TLS_DTPREL32: 14933 case BFD_RELOC_MIPS_TLS_DTPREL64: 14934 case BFD_RELOC_MIPS_TLS_DTPREL_HI16: 14935 case BFD_RELOC_MIPS_TLS_DTPREL_LO16: 14936 case BFD_RELOC_MIPS_TLS_GOTTPREL: 14937 case BFD_RELOC_MIPS_TLS_TPREL32: 14938 case BFD_RELOC_MIPS_TLS_TPREL64: 14939 case BFD_RELOC_MIPS_TLS_TPREL_HI16: 14940 case BFD_RELOC_MIPS_TLS_TPREL_LO16: 14941 case BFD_RELOC_MICROMIPS_TLS_GD: 14942 case BFD_RELOC_MICROMIPS_TLS_LDM: 14943 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: 14944 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: 14945 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: 14946 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: 14947 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: 14948 case BFD_RELOC_MIPS16_TLS_GD: 14949 case BFD_RELOC_MIPS16_TLS_LDM: 14950 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: 14951 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: 14952 case BFD_RELOC_MIPS16_TLS_GOTTPREL: 14953 case BFD_RELOC_MIPS16_TLS_TPREL_HI16: 14954 case BFD_RELOC_MIPS16_TLS_TPREL_LO16: 14955 if (fixP->fx_addsy) 14956 S_SET_THREAD_LOCAL (fixP->fx_addsy); 14957 else 14958 as_bad_where (fixP->fx_file, fixP->fx_line, 14959 _("TLS relocation against a constant")); 14960 break; 14961 14962 case BFD_RELOC_MIPS_JMP: 14963 case BFD_RELOC_MIPS_SHIFT5: 14964 case BFD_RELOC_MIPS_SHIFT6: 14965 case BFD_RELOC_MIPS_GOT_DISP: 14966 case BFD_RELOC_MIPS_GOT_PAGE: 14967 case BFD_RELOC_MIPS_GOT_OFST: 14968 case BFD_RELOC_MIPS_SUB: 14969 case BFD_RELOC_MIPS_INSERT_A: 14970 case BFD_RELOC_MIPS_INSERT_B: 14971 case BFD_RELOC_MIPS_DELETE: 14972 case BFD_RELOC_MIPS_HIGHEST: 14973 case BFD_RELOC_MIPS_HIGHER: 14974 case BFD_RELOC_MIPS_SCN_DISP: 14975 case BFD_RELOC_MIPS_REL16: 14976 case BFD_RELOC_MIPS_RELGOT: 14977 case BFD_RELOC_MIPS_JALR: 14978 case BFD_RELOC_HI16: 14979 case BFD_RELOC_HI16_S: 14980 case BFD_RELOC_LO16: 14981 case BFD_RELOC_GPREL16: 14982 case BFD_RELOC_MIPS_LITERAL: 14983 case BFD_RELOC_MIPS_CALL16: 14984 case BFD_RELOC_MIPS_GOT16: 14985 case BFD_RELOC_GPREL32: 14986 case BFD_RELOC_MIPS_GOT_HI16: 14987 case BFD_RELOC_MIPS_GOT_LO16: 14988 case BFD_RELOC_MIPS_CALL_HI16: 14989 case BFD_RELOC_MIPS_CALL_LO16: 14990 case BFD_RELOC_HI16_S_PCREL: 14991 case BFD_RELOC_LO16_PCREL: 14992 case BFD_RELOC_MIPS16_GPREL: 14993 case BFD_RELOC_MIPS16_GOT16: 14994 case BFD_RELOC_MIPS16_CALL16: 14995 case BFD_RELOC_MIPS16_HI16: 14996 case BFD_RELOC_MIPS16_HI16_S: 14997 case BFD_RELOC_MIPS16_LO16: 14998 case BFD_RELOC_MIPS16_JMP: 14999 case BFD_RELOC_MICROMIPS_JMP: 15000 case BFD_RELOC_MICROMIPS_GOT_DISP: 15001 case BFD_RELOC_MICROMIPS_GOT_PAGE: 15002 case BFD_RELOC_MICROMIPS_GOT_OFST: 15003 case BFD_RELOC_MICROMIPS_SUB: 15004 case BFD_RELOC_MICROMIPS_HIGHEST: 15005 case BFD_RELOC_MICROMIPS_HIGHER: 15006 case BFD_RELOC_MICROMIPS_SCN_DISP: 15007 case BFD_RELOC_MICROMIPS_JALR: 15008 case BFD_RELOC_MICROMIPS_HI16: 15009 case BFD_RELOC_MICROMIPS_HI16_S: 15010 case BFD_RELOC_MICROMIPS_LO16: 15011 case BFD_RELOC_MICROMIPS_GPREL16: 15012 case BFD_RELOC_MICROMIPS_LITERAL: 15013 case BFD_RELOC_MICROMIPS_CALL16: 15014 case BFD_RELOC_MICROMIPS_GOT16: 15015 case BFD_RELOC_MICROMIPS_GOT_HI16: 15016 case BFD_RELOC_MICROMIPS_GOT_LO16: 15017 case BFD_RELOC_MICROMIPS_CALL_HI16: 15018 case BFD_RELOC_MICROMIPS_CALL_LO16: 15019 case BFD_RELOC_MIPS_EH: 15020 if (fixP->fx_done) 15021 { 15022 offsetT value; 15023 15024 if (calculate_reloc (fixP->fx_r_type, *valP, &value)) 15025 { 15026 insn = read_reloc_insn (buf, fixP->fx_r_type); 15027 if (mips16_reloc_p (fixP->fx_r_type)) 15028 insn |= mips16_immed_extend (value, 16); 15029 else 15030 insn |= (value & 0xffff); 15031 write_reloc_insn (buf, fixP->fx_r_type, insn); 15032 } 15033 else 15034 as_bad_where (fixP->fx_file, fixP->fx_line, 15035 _("unsupported constant in relocation")); 15036 } 15037 break; 15038 15039 case BFD_RELOC_64: 15040 /* This is handled like BFD_RELOC_32, but we output a sign 15041 extended value if we are only 32 bits. */ 15042 if (fixP->fx_done) 15043 { 15044 if (8 <= sizeof (valueT)) 15045 md_number_to_chars (buf, *valP, 8); 15046 else 15047 { 15048 valueT hiv; 15049 15050 if ((*valP & 0x80000000) != 0) 15051 hiv = 0xffffffff; 15052 else 15053 hiv = 0; 15054 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); 15055 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); 15056 } 15057 } 15058 break; 15059 15060 case BFD_RELOC_RVA: 15061 case BFD_RELOC_32: 15062 case BFD_RELOC_32_PCREL: 15063 case BFD_RELOC_16: 15064 case BFD_RELOC_8: 15065 /* If we are deleting this reloc entry, we must fill in the 15066 value now. This can happen if we have a .word which is not 15067 resolved when it appears but is later defined. */ 15068 if (fixP->fx_done) 15069 md_number_to_chars (buf, *valP, fixP->fx_size); 15070 break; 15071 15072 case BFD_RELOC_MIPS_21_PCREL_S2: 15073 if ((*valP & 0x3) != 0) 15074 as_bad_where (fixP->fx_file, fixP->fx_line, 15075 _("branch to misaligned address (%lx)"), (long) *valP); 15076 if (!fixP->fx_done) 15077 break; 15078 15079 if (*valP + 0x400000 <= 0x7fffff) 15080 { 15081 insn = read_insn (buf); 15082 insn |= (*valP >> 2) & 0x1fffff; 15083 write_insn (buf, insn); 15084 } 15085 else 15086 as_bad_where (fixP->fx_file, fixP->fx_line, 15087 _("branch out of range")); 15088 break; 15089 15090 case BFD_RELOC_MIPS_26_PCREL_S2: 15091 if ((*valP & 0x3) != 0) 15092 as_bad_where (fixP->fx_file, fixP->fx_line, 15093 _("branch to misaligned address (%lx)"), (long) *valP); 15094 if (!fixP->fx_done) 15095 break; 15096 15097 if (*valP + 0x8000000 <= 0xfffffff) 15098 { 15099 insn = read_insn (buf); 15100 insn |= (*valP >> 2) & 0x3ffffff; 15101 write_insn (buf, insn); 15102 } 15103 else 15104 as_bad_where (fixP->fx_file, fixP->fx_line, 15105 _("branch out of range")); 15106 break; 15107 15108 case BFD_RELOC_MIPS_18_PCREL_S3: 15109 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) 15110 as_bad_where (fixP->fx_file, fixP->fx_line, 15111 _("PC-relative access using misaligned symbol (%lx)"), 15112 (long) S_GET_VALUE (fixP->fx_addsy)); 15113 if ((fixP->fx_offset & 0x7) != 0) 15114 as_bad_where (fixP->fx_file, fixP->fx_line, 15115 _("PC-relative access using misaligned offset (%lx)"), 15116 (long) fixP->fx_offset); 15117 if (!fixP->fx_done) 15118 break; 15119 15120 if (*valP + 0x100000 <= 0x1fffff) 15121 { 15122 insn = read_insn (buf); 15123 insn |= (*valP >> 3) & 0x3ffff; 15124 write_insn (buf, insn); 15125 } 15126 else 15127 as_bad_where (fixP->fx_file, fixP->fx_line, 15128 _("PC-relative access out of range")); 15129 break; 15130 15131 case BFD_RELOC_MIPS_19_PCREL_S2: 15132 if ((*valP & 0x3) != 0) 15133 as_bad_where (fixP->fx_file, fixP->fx_line, 15134 _("PC-relative access to misaligned address (%lx)"), 15135 (long) *valP); 15136 if (!fixP->fx_done) 15137 break; 15138 15139 if (*valP + 0x100000 <= 0x1fffff) 15140 { 15141 insn = read_insn (buf); 15142 insn |= (*valP >> 2) & 0x7ffff; 15143 write_insn (buf, insn); 15144 } 15145 else 15146 as_bad_where (fixP->fx_file, fixP->fx_line, 15147 _("PC-relative access out of range")); 15148 break; 15149 15150 case BFD_RELOC_16_PCREL_S2: 15151 if ((*valP & 0x3) != 0) 15152 as_bad_where (fixP->fx_file, fixP->fx_line, 15153 _("branch to misaligned address (%lx)"), (long) *valP); 15154 15155 /* We need to save the bits in the instruction since fixup_segment() 15156 might be deleting the relocation entry (i.e., a branch within 15157 the current segment). */ 15158 if (! fixP->fx_done) 15159 break; 15160 15161 /* Update old instruction data. */ 15162 insn = read_insn (buf); 15163 15164 if (*valP + 0x20000 <= 0x3ffff) 15165 { 15166 insn |= (*valP >> 2) & 0xffff; 15167 write_insn (buf, insn); 15168 } 15169 else if (mips_pic == NO_PIC 15170 && fixP->fx_done 15171 && fixP->fx_frag->fr_address >= text_section->vma 15172 && (fixP->fx_frag->fr_address 15173 < text_section->vma + bfd_get_section_size (text_section)) 15174 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 15175 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ 15176 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 15177 { 15178 /* The branch offset is too large. If this is an 15179 unconditional branch, and we are not generating PIC code, 15180 we can convert it to an absolute jump instruction. */ 15181 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ 15182 insn = 0x0c000000; /* jal */ 15183 else 15184 insn = 0x08000000; /* j */ 15185 fixP->fx_r_type = BFD_RELOC_MIPS_JMP; 15186 fixP->fx_done = 0; 15187 fixP->fx_addsy = section_symbol (text_section); 15188 *valP += md_pcrel_from (fixP); 15189 write_insn (buf, insn); 15190 } 15191 else 15192 { 15193 /* If we got here, we have branch-relaxation disabled, 15194 and there's nothing we can do to fix this instruction 15195 without turning it into a longer sequence. */ 15196 as_bad_where (fixP->fx_file, fixP->fx_line, 15197 _("branch out of range")); 15198 } 15199 break; 15200 15201 case BFD_RELOC_MIPS16_16_PCREL_S1: 15202 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15203 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15204 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15205 /* We adjust the offset back to even. */ 15206 if ((*valP & 0x1) != 0) 15207 --(*valP); 15208 15209 if (! fixP->fx_done) 15210 break; 15211 15212 /* Should never visit here, because we keep the relocation. */ 15213 abort (); 15214 break; 15215 15216 case BFD_RELOC_VTABLE_INHERIT: 15217 fixP->fx_done = 0; 15218 if (fixP->fx_addsy 15219 && !S_IS_DEFINED (fixP->fx_addsy) 15220 && !S_IS_WEAK (fixP->fx_addsy)) 15221 S_SET_WEAK (fixP->fx_addsy); 15222 break; 15223 15224 case BFD_RELOC_NONE: 15225 case BFD_RELOC_VTABLE_ENTRY: 15226 fixP->fx_done = 0; 15227 break; 15228 15229 default: 15230 abort (); 15231 } 15232 15233 /* Remember value for tc_gen_reloc. */ 15234 fixP->fx_addnumber = *valP; 15235 } 15236 15237 static symbolS * 15238 get_symbol (void) 15239 { 15240 int c; 15241 char *name; 15242 symbolS *p; 15243 15244 c = get_symbol_name (&name); 15245 p = (symbolS *) symbol_find_or_make (name); 15246 (void) restore_line_pointer (c); 15247 return p; 15248 } 15249 15250 /* Align the current frag to a given power of two. If a particular 15251 fill byte should be used, FILL points to an integer that contains 15252 that byte, otherwise FILL is null. 15253 15254 This function used to have the comment: 15255 15256 The MIPS assembler also automatically adjusts any preceding label. 15257 15258 The implementation therefore applied the adjustment to a maximum of 15259 one label. However, other label adjustments are applied to batches 15260 of labels, and adjusting just one caused problems when new labels 15261 were added for the sake of debugging or unwind information. 15262 We therefore adjust all preceding labels (given as LABELS) instead. */ 15263 15264 static void 15265 mips_align (int to, int *fill, struct insn_label_list *labels) 15266 { 15267 mips_emit_delays (); 15268 mips_record_compressed_mode (); 15269 if (fill == NULL && subseg_text_p (now_seg)) 15270 frag_align_code (to, 0); 15271 else 15272 frag_align (to, fill ? *fill : 0, 0); 15273 record_alignment (now_seg, to); 15274 mips_move_labels (labels, FALSE); 15275 } 15276 15277 /* Align to a given power of two. .align 0 turns off the automatic 15278 alignment used by the data creating pseudo-ops. */ 15279 15280 static void 15281 s_align (int x ATTRIBUTE_UNUSED) 15282 { 15283 int temp, fill_value, *fill_ptr; 15284 long max_alignment = 28; 15285 15286 /* o Note that the assembler pulls down any immediately preceding label 15287 to the aligned address. 15288 o It's not documented but auto alignment is reinstated by 15289 a .align pseudo instruction. 15290 o Note also that after auto alignment is turned off the mips assembler 15291 issues an error on attempt to assemble an improperly aligned data item. 15292 We don't. */ 15293 15294 temp = get_absolute_expression (); 15295 if (temp > max_alignment) 15296 as_bad (_("alignment too large, %d assumed"), temp = max_alignment); 15297 else if (temp < 0) 15298 { 15299 as_warn (_("alignment negative, 0 assumed")); 15300 temp = 0; 15301 } 15302 if (*input_line_pointer == ',') 15303 { 15304 ++input_line_pointer; 15305 fill_value = get_absolute_expression (); 15306 fill_ptr = &fill_value; 15307 } 15308 else 15309 fill_ptr = 0; 15310 if (temp) 15311 { 15312 segment_info_type *si = seg_info (now_seg); 15313 struct insn_label_list *l = si->label_list; 15314 /* Auto alignment should be switched on by next section change. */ 15315 auto_align = 1; 15316 mips_align (temp, fill_ptr, l); 15317 } 15318 else 15319 { 15320 auto_align = 0; 15321 } 15322 15323 demand_empty_rest_of_line (); 15324 } 15325 15326 static void 15327 s_change_sec (int sec) 15328 { 15329 segT seg; 15330 15331 /* The ELF backend needs to know that we are changing sections, so 15332 that .previous works correctly. We could do something like check 15333 for an obj_section_change_hook macro, but that might be confusing 15334 as it would not be appropriate to use it in the section changing 15335 functions in read.c, since obj-elf.c intercepts those. FIXME: 15336 This should be cleaner, somehow. */ 15337 obj_elf_section_change_hook (); 15338 15339 mips_emit_delays (); 15340 15341 switch (sec) 15342 { 15343 case 't': 15344 s_text (0); 15345 break; 15346 case 'd': 15347 s_data (0); 15348 break; 15349 case 'b': 15350 subseg_set (bss_section, (subsegT) get_absolute_expression ()); 15351 demand_empty_rest_of_line (); 15352 break; 15353 15354 case 'r': 15355 seg = subseg_new (RDATA_SECTION_NAME, 15356 (subsegT) get_absolute_expression ()); 15357 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD 15358 | SEC_READONLY | SEC_RELOC 15359 | SEC_DATA)); 15360 if (strncmp (TARGET_OS, "elf", 3) != 0) 15361 record_alignment (seg, 4); 15362 demand_empty_rest_of_line (); 15363 break; 15364 15365 case 's': 15366 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); 15367 bfd_set_section_flags (stdoutput, seg, 15368 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); 15369 if (strncmp (TARGET_OS, "elf", 3) != 0) 15370 record_alignment (seg, 4); 15371 demand_empty_rest_of_line (); 15372 break; 15373 15374 case 'B': 15375 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); 15376 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); 15377 if (strncmp (TARGET_OS, "elf", 3) != 0) 15378 record_alignment (seg, 4); 15379 demand_empty_rest_of_line (); 15380 break; 15381 } 15382 15383 auto_align = 1; 15384 } 15385 15386 void 15387 s_change_section (int ignore ATTRIBUTE_UNUSED) 15388 { 15389 char *saved_ilp; 15390 char *section_name; 15391 char c, endc; 15392 char next_c = 0; 15393 int section_type; 15394 int section_flag; 15395 int section_entry_size; 15396 int section_alignment; 15397 15398 saved_ilp = input_line_pointer; 15399 endc = get_symbol_name (§ion_name); 15400 c = (endc == '"' ? input_line_pointer[1] : endc); 15401 if (c) 15402 next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; 15403 15404 /* Do we have .section Name<,"flags">? */ 15405 if (c != ',' || (c == ',' && next_c == '"')) 15406 { 15407 /* Just after name is now '\0'. */ 15408 (void) restore_line_pointer (endc); 15409 input_line_pointer = saved_ilp; 15410 obj_elf_section (ignore); 15411 return; 15412 } 15413 15414 section_name = xstrdup (section_name); 15415 c = restore_line_pointer (endc); 15416 15417 input_line_pointer++; 15418 15419 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ 15420 if (c == ',') 15421 section_type = get_absolute_expression (); 15422 else 15423 section_type = 0; 15424 15425 if (*input_line_pointer++ == ',') 15426 section_flag = get_absolute_expression (); 15427 else 15428 section_flag = 0; 15429 15430 if (*input_line_pointer++ == ',') 15431 section_entry_size = get_absolute_expression (); 15432 else 15433 section_entry_size = 0; 15434 15435 if (*input_line_pointer++ == ',') 15436 section_alignment = get_absolute_expression (); 15437 else 15438 section_alignment = 0; 15439 15440 /* FIXME: really ignore? */ 15441 (void) section_alignment; 15442 15443 /* When using the generic form of .section (as implemented by obj-elf.c), 15444 there's no way to set the section type to SHT_MIPS_DWARF. Users have 15445 traditionally had to fall back on the more common @progbits instead. 15446 15447 There's nothing really harmful in this, since bfd will correct 15448 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it 15449 means that, for backwards compatibility, the special_section entries 15450 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. 15451 15452 Even so, we shouldn't force users of the MIPS .section syntax to 15453 incorrectly label the sections as SHT_PROGBITS. The best compromise 15454 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the 15455 generic type-checking code. */ 15456 if (section_type == SHT_MIPS_DWARF) 15457 section_type = SHT_PROGBITS; 15458 15459 obj_elf_change_section (section_name, section_type, section_flag, 15460 section_entry_size, 0, 0, 0); 15461 15462 if (now_seg->name != section_name) 15463 free (section_name); 15464 } 15465 15466 void 15467 mips_enable_auto_align (void) 15468 { 15469 auto_align = 1; 15470 } 15471 15472 static void 15473 s_cons (int log_size) 15474 { 15475 segment_info_type *si = seg_info (now_seg); 15476 struct insn_label_list *l = si->label_list; 15477 15478 mips_emit_delays (); 15479 if (log_size > 0 && auto_align) 15480 mips_align (log_size, 0, l); 15481 cons (1 << log_size); 15482 mips_clear_insn_labels (); 15483 } 15484 15485 static void 15486 s_float_cons (int type) 15487 { 15488 segment_info_type *si = seg_info (now_seg); 15489 struct insn_label_list *l = si->label_list; 15490 15491 mips_emit_delays (); 15492 15493 if (auto_align) 15494 { 15495 if (type == 'd') 15496 mips_align (3, 0, l); 15497 else 15498 mips_align (2, 0, l); 15499 } 15500 15501 float_cons (type); 15502 mips_clear_insn_labels (); 15503 } 15504 15505 /* Handle .globl. We need to override it because on Irix 5 you are 15506 permitted to say 15507 .globl foo .text 15508 where foo is an undefined symbol, to mean that foo should be 15509 considered to be the address of a function. */ 15510 15511 static void 15512 s_mips_globl (int x ATTRIBUTE_UNUSED) 15513 { 15514 char *name; 15515 int c; 15516 symbolS *symbolP; 15517 flagword flag; 15518 15519 do 15520 { 15521 c = get_symbol_name (&name); 15522 symbolP = symbol_find_or_make (name); 15523 S_SET_EXTERNAL (symbolP); 15524 15525 *input_line_pointer = c; 15526 SKIP_WHITESPACE_AFTER_NAME (); 15527 15528 /* On Irix 5, every global symbol that is not explicitly labelled as 15529 being a function is apparently labelled as being an object. */ 15530 flag = BSF_OBJECT; 15531 15532 if (!is_end_of_line[(unsigned char) *input_line_pointer] 15533 && (*input_line_pointer != ',')) 15534 { 15535 char *secname; 15536 asection *sec; 15537 15538 c = get_symbol_name (&secname); 15539 sec = bfd_get_section_by_name (stdoutput, secname); 15540 if (sec == NULL) 15541 as_bad (_("%s: no such section"), secname); 15542 (void) restore_line_pointer (c); 15543 15544 if (sec != NULL && (sec->flags & SEC_CODE) != 0) 15545 flag = BSF_FUNCTION; 15546 } 15547 15548 symbol_get_bfdsym (symbolP)->flags |= flag; 15549 15550 c = *input_line_pointer; 15551 if (c == ',') 15552 { 15553 input_line_pointer++; 15554 SKIP_WHITESPACE (); 15555 if (is_end_of_line[(unsigned char) *input_line_pointer]) 15556 c = '\n'; 15557 } 15558 } 15559 while (c == ','); 15560 15561 demand_empty_rest_of_line (); 15562 } 15563 15564 static void 15565 s_option (int x ATTRIBUTE_UNUSED) 15566 { 15567 char *opt; 15568 char c; 15569 15570 c = get_symbol_name (&opt); 15571 15572 if (*opt == 'O') 15573 { 15574 /* FIXME: What does this mean? */ 15575 } 15576 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') 15577 { 15578 int i; 15579 15580 i = atoi (opt + 3); 15581 if (i != 0 && i != 2) 15582 as_bad (_(".option pic%d not supported"), i); 15583 else if (mips_pic == VXWORKS_PIC) 15584 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); 15585 else if (i == 0) 15586 mips_pic = NO_PIC; 15587 else if (i == 2) 15588 { 15589 mips_pic = SVR4_PIC; 15590 mips_abicalls = TRUE; 15591 } 15592 15593 if (mips_pic == SVR4_PIC) 15594 { 15595 if (g_switch_seen && g_switch_value != 0) 15596 as_warn (_("-G may not be used with SVR4 PIC code")); 15597 g_switch_value = 0; 15598 bfd_set_gp_size (stdoutput, 0); 15599 } 15600 } 15601 else 15602 as_warn (_("unrecognized option \"%s\""), opt); 15603 15604 (void) restore_line_pointer (c); 15605 demand_empty_rest_of_line (); 15606 } 15607 15608 /* This structure is used to hold a stack of .set values. */ 15609 15610 struct mips_option_stack 15611 { 15612 struct mips_option_stack *next; 15613 struct mips_set_options options; 15614 }; 15615 15616 static struct mips_option_stack *mips_opts_stack; 15617 15618 /* Return status for .set/.module option handling. */ 15619 15620 enum code_option_type 15621 { 15622 /* Unrecognized option. */ 15623 OPTION_TYPE_BAD = -1, 15624 15625 /* Ordinary option. */ 15626 OPTION_TYPE_NORMAL, 15627 15628 /* ISA changing option. */ 15629 OPTION_TYPE_ISA 15630 }; 15631 15632 /* Handle common .set/.module options. Return status indicating option 15633 type. */ 15634 15635 static enum code_option_type 15636 parse_code_option (char * name) 15637 { 15638 bfd_boolean isa_set = FALSE; 15639 const struct mips_ase *ase; 15640 15641 if (strncmp (name, "at=", 3) == 0) 15642 { 15643 char *s = name + 3; 15644 15645 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) 15646 as_bad (_("unrecognized register name `%s'"), s); 15647 } 15648 else if (strcmp (name, "at") == 0) 15649 mips_opts.at = ATREG; 15650 else if (strcmp (name, "noat") == 0) 15651 mips_opts.at = ZERO; 15652 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) 15653 mips_opts.nomove = 0; 15654 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) 15655 mips_opts.nomove = 1; 15656 else if (strcmp (name, "bopt") == 0) 15657 mips_opts.nobopt = 0; 15658 else if (strcmp (name, "nobopt") == 0) 15659 mips_opts.nobopt = 1; 15660 else if (strcmp (name, "gp=32") == 0) 15661 mips_opts.gp = 32; 15662 else if (strcmp (name, "gp=64") == 0) 15663 mips_opts.gp = 64; 15664 else if (strcmp (name, "fp=32") == 0) 15665 mips_opts.fp = 32; 15666 else if (strcmp (name, "fp=xx") == 0) 15667 mips_opts.fp = 0; 15668 else if (strcmp (name, "fp=64") == 0) 15669 mips_opts.fp = 64; 15670 else if (strcmp (name, "softfloat") == 0) 15671 mips_opts.soft_float = 1; 15672 else if (strcmp (name, "hardfloat") == 0) 15673 mips_opts.soft_float = 0; 15674 else if (strcmp (name, "singlefloat") == 0) 15675 mips_opts.single_float = 1; 15676 else if (strcmp (name, "doublefloat") == 0) 15677 mips_opts.single_float = 0; 15678 else if (strcmp (name, "nooddspreg") == 0) 15679 mips_opts.oddspreg = 0; 15680 else if (strcmp (name, "oddspreg") == 0) 15681 mips_opts.oddspreg = 1; 15682 else if (strcmp (name, "mips16") == 0 15683 || strcmp (name, "MIPS-16") == 0) 15684 mips_opts.mips16 = 1; 15685 else if (strcmp (name, "nomips16") == 0 15686 || strcmp (name, "noMIPS-16") == 0) 15687 mips_opts.mips16 = 0; 15688 else if (strcmp (name, "micromips") == 0) 15689 mips_opts.micromips = 1; 15690 else if (strcmp (name, "nomicromips") == 0) 15691 mips_opts.micromips = 0; 15692 else if (name[0] == 'n' 15693 && name[1] == 'o' 15694 && (ase = mips_lookup_ase (name + 2))) 15695 mips_set_ase (ase, &mips_opts, FALSE); 15696 else if ((ase = mips_lookup_ase (name))) 15697 mips_set_ase (ase, &mips_opts, TRUE); 15698 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) 15699 { 15700 /* Permit the user to change the ISA and architecture on the fly. 15701 Needless to say, misuse can cause serious problems. */ 15702 if (strncmp (name, "arch=", 5) == 0) 15703 { 15704 const struct mips_cpu_info *p; 15705 15706 p = mips_parse_cpu ("internal use", name + 5); 15707 if (!p) 15708 as_bad (_("unknown architecture %s"), name + 5); 15709 else 15710 { 15711 mips_opts.arch = p->cpu; 15712 mips_opts.isa = p->isa; 15713 isa_set = TRUE; 15714 } 15715 } 15716 else if (strncmp (name, "mips", 4) == 0) 15717 { 15718 const struct mips_cpu_info *p; 15719 15720 p = mips_parse_cpu ("internal use", name); 15721 if (!p) 15722 as_bad (_("unknown ISA level %s"), name + 4); 15723 else 15724 { 15725 mips_opts.arch = p->cpu; 15726 mips_opts.isa = p->isa; 15727 isa_set = TRUE; 15728 } 15729 } 15730 else 15731 as_bad (_("unknown ISA or architecture %s"), name); 15732 } 15733 else if (strcmp (name, "autoextend") == 0) 15734 mips_opts.noautoextend = 0; 15735 else if (strcmp (name, "noautoextend") == 0) 15736 mips_opts.noautoextend = 1; 15737 else if (strcmp (name, "insn32") == 0) 15738 mips_opts.insn32 = TRUE; 15739 else if (strcmp (name, "noinsn32") == 0) 15740 mips_opts.insn32 = FALSE; 15741 else if (strcmp (name, "sym32") == 0) 15742 mips_opts.sym32 = TRUE; 15743 else if (strcmp (name, "nosym32") == 0) 15744 mips_opts.sym32 = FALSE; 15745 else 15746 return OPTION_TYPE_BAD; 15747 15748 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; 15749 } 15750 15751 /* Handle the .set pseudo-op. */ 15752 15753 static void 15754 s_mipsset (int x ATTRIBUTE_UNUSED) 15755 { 15756 enum code_option_type type = OPTION_TYPE_NORMAL; 15757 char *name = input_line_pointer, ch; 15758 15759 file_mips_check_options (); 15760 15761 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 15762 ++input_line_pointer; 15763 ch = *input_line_pointer; 15764 *input_line_pointer = '\0'; 15765 15766 if (strchr (name, ',')) 15767 { 15768 /* Generic ".set" directive; use the generic handler. */ 15769 *input_line_pointer = ch; 15770 input_line_pointer = name; 15771 s_set (0); 15772 return; 15773 } 15774 15775 if (strcmp (name, "reorder") == 0) 15776 { 15777 if (mips_opts.noreorder) 15778 end_noreorder (); 15779 } 15780 else if (strcmp (name, "noreorder") == 0) 15781 { 15782 if (!mips_opts.noreorder) 15783 start_noreorder (); 15784 } 15785 else if (strcmp (name, "macro") == 0) 15786 mips_opts.warn_about_macros = 0; 15787 else if (strcmp (name, "nomacro") == 0) 15788 { 15789 if (mips_opts.noreorder == 0) 15790 as_bad (_("`noreorder' must be set before `nomacro'")); 15791 mips_opts.warn_about_macros = 1; 15792 } 15793 else if (strcmp (name, "gp=default") == 0) 15794 mips_opts.gp = file_mips_opts.gp; 15795 else if (strcmp (name, "fp=default") == 0) 15796 mips_opts.fp = file_mips_opts.fp; 15797 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) 15798 { 15799 mips_opts.isa = file_mips_opts.isa; 15800 mips_opts.arch = file_mips_opts.arch; 15801 mips_opts.gp = file_mips_opts.gp; 15802 mips_opts.fp = file_mips_opts.fp; 15803 } 15804 else if (strcmp (name, "push") == 0) 15805 { 15806 struct mips_option_stack *s; 15807 15808 s = XNEW (struct mips_option_stack); 15809 s->next = mips_opts_stack; 15810 s->options = mips_opts; 15811 mips_opts_stack = s; 15812 } 15813 else if (strcmp (name, "pop") == 0) 15814 { 15815 struct mips_option_stack *s; 15816 15817 s = mips_opts_stack; 15818 if (s == NULL) 15819 as_bad (_(".set pop with no .set push")); 15820 else 15821 { 15822 /* If we're changing the reorder mode we need to handle 15823 delay slots correctly. */ 15824 if (s->options.noreorder && ! mips_opts.noreorder) 15825 start_noreorder (); 15826 else if (! s->options.noreorder && mips_opts.noreorder) 15827 end_noreorder (); 15828 15829 mips_opts = s->options; 15830 mips_opts_stack = s->next; 15831 free (s); 15832 } 15833 } 15834 else 15835 { 15836 type = parse_code_option (name); 15837 if (type == OPTION_TYPE_BAD) 15838 as_warn (_("tried to set unrecognized symbol: %s\n"), name); 15839 } 15840 15841 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp 15842 registers based on what is supported by the arch/cpu. */ 15843 if (type == OPTION_TYPE_ISA) 15844 { 15845 switch (mips_opts.isa) 15846 { 15847 case 0: 15848 break; 15849 case ISA_MIPS1: 15850 /* MIPS I cannot support FPXX. */ 15851 mips_opts.fp = 32; 15852 /* fall-through. */ 15853 case ISA_MIPS2: 15854 case ISA_MIPS32: 15855 case ISA_MIPS32R2: 15856 case ISA_MIPS32R3: 15857 case ISA_MIPS32R5: 15858 mips_opts.gp = 32; 15859 if (mips_opts.fp != 0) 15860 mips_opts.fp = 32; 15861 break; 15862 case ISA_MIPS32R6: 15863 mips_opts.gp = 32; 15864 mips_opts.fp = 64; 15865 break; 15866 case ISA_MIPS3: 15867 case ISA_MIPS4: 15868 case ISA_MIPS5: 15869 case ISA_MIPS64: 15870 case ISA_MIPS64R2: 15871 case ISA_MIPS64R3: 15872 case ISA_MIPS64R5: 15873 case ISA_MIPS64R6: 15874 mips_opts.gp = 64; 15875 if (mips_opts.fp != 0) 15876 { 15877 if (mips_opts.arch == CPU_R5900) 15878 mips_opts.fp = 32; 15879 else 15880 mips_opts.fp = 64; 15881 } 15882 break; 15883 default: 15884 as_bad (_("unknown ISA level %s"), name + 4); 15885 break; 15886 } 15887 } 15888 15889 mips_check_options (&mips_opts, FALSE); 15890 15891 mips_check_isa_supports_ases (); 15892 *input_line_pointer = ch; 15893 demand_empty_rest_of_line (); 15894 } 15895 15896 /* Handle the .module pseudo-op. */ 15897 15898 static void 15899 s_module (int ignore ATTRIBUTE_UNUSED) 15900 { 15901 char *name = input_line_pointer, ch; 15902 15903 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 15904 ++input_line_pointer; 15905 ch = *input_line_pointer; 15906 *input_line_pointer = '\0'; 15907 15908 if (!file_mips_opts_checked) 15909 { 15910 if (parse_code_option (name) == OPTION_TYPE_BAD) 15911 as_bad (_(".module used with unrecognized symbol: %s\n"), name); 15912 15913 /* Update module level settings from mips_opts. */ 15914 file_mips_opts = mips_opts; 15915 } 15916 else 15917 as_bad (_(".module is not permitted after generating code")); 15918 15919 *input_line_pointer = ch; 15920 demand_empty_rest_of_line (); 15921 } 15922 15923 /* Handle the .abicalls pseudo-op. I believe this is equivalent to 15924 .option pic2. It means to generate SVR4 PIC calls. */ 15925 15926 static void 15927 s_abicalls (int ignore ATTRIBUTE_UNUSED) 15928 { 15929 mips_pic = SVR4_PIC; 15930 mips_abicalls = TRUE; 15931 15932 if (g_switch_seen && g_switch_value != 0) 15933 as_warn (_("-G may not be used with SVR4 PIC code")); 15934 g_switch_value = 0; 15935 15936 bfd_set_gp_size (stdoutput, 0); 15937 demand_empty_rest_of_line (); 15938 } 15939 15940 /* Handle the .cpload pseudo-op. This is used when generating SVR4 15941 PIC code. It sets the $gp register for the function based on the 15942 function address, which is in the register named in the argument. 15943 This uses a relocation against _gp_disp, which is handled specially 15944 by the linker. The result is: 15945 lui $gp,%hi(_gp_disp) 15946 addiu $gp,$gp,%lo(_gp_disp) 15947 addu $gp,$gp,.cpload argument 15948 The .cpload argument is normally $25 == $t9. 15949 15950 The -mno-shared option changes this to: 15951 lui $gp,%hi(__gnu_local_gp) 15952 addiu $gp,$gp,%lo(__gnu_local_gp) 15953 and the argument is ignored. This saves an instruction, but the 15954 resulting code is not position independent; it uses an absolute 15955 address for __gnu_local_gp. Thus code assembled with -mno-shared 15956 can go into an ordinary executable, but not into a shared library. */ 15957 15958 static void 15959 s_cpload (int ignore ATTRIBUTE_UNUSED) 15960 { 15961 expressionS ex; 15962 int reg; 15963 int in_shared; 15964 15965 file_mips_check_options (); 15966 15967 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 15968 .cpload is ignored. */ 15969 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 15970 { 15971 s_ignore (0); 15972 return; 15973 } 15974 15975 if (mips_opts.mips16) 15976 { 15977 as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); 15978 ignore_rest_of_line (); 15979 return; 15980 } 15981 15982 /* .cpload should be in a .set noreorder section. */ 15983 if (mips_opts.noreorder == 0) 15984 as_warn (_(".cpload not in noreorder section")); 15985 15986 reg = tc_get_register (0); 15987 15988 /* If we need to produce a 64-bit address, we are better off using 15989 the default instruction sequence. */ 15990 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; 15991 15992 ex.X_op = O_symbol; 15993 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : 15994 "__gnu_local_gp"); 15995 ex.X_op_symbol = NULL; 15996 ex.X_add_number = 0; 15997 15998 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 15999 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 16000 16001 mips_mark_labels (); 16002 mips_assembling_insn = TRUE; 16003 16004 macro_start (); 16005 macro_build_lui (&ex, mips_gp_register); 16006 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 16007 mips_gp_register, BFD_RELOC_LO16); 16008 if (in_shared) 16009 macro_build (NULL, "addu", "d,v,t", mips_gp_register, 16010 mips_gp_register, reg); 16011 macro_end (); 16012 16013 mips_assembling_insn = FALSE; 16014 demand_empty_rest_of_line (); 16015 } 16016 16017 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: 16018 .cpsetup $reg1, offset|$reg2, label 16019 16020 If offset is given, this results in: 16021 sd $gp, offset($sp) 16022 lui $gp, %hi(%neg(%gp_rel(label))) 16023 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 16024 daddu $gp, $gp, $reg1 16025 16026 If $reg2 is given, this results in: 16027 or $reg2, $gp, $0 16028 lui $gp, %hi(%neg(%gp_rel(label))) 16029 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 16030 daddu $gp, $gp, $reg1 16031 $reg1 is normally $25 == $t9. 16032 16033 The -mno-shared option replaces the last three instructions with 16034 lui $gp,%hi(_gp) 16035 addiu $gp,$gp,%lo(_gp) */ 16036 16037 static void 16038 s_cpsetup (int ignore ATTRIBUTE_UNUSED) 16039 { 16040 expressionS ex_off; 16041 expressionS ex_sym; 16042 int reg1; 16043 16044 file_mips_check_options (); 16045 16046 /* If we are not generating SVR4 PIC code, .cpsetup is ignored. 16047 We also need NewABI support. */ 16048 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16049 { 16050 s_ignore (0); 16051 return; 16052 } 16053 16054 if (mips_opts.mips16) 16055 { 16056 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); 16057 ignore_rest_of_line (); 16058 return; 16059 } 16060 16061 reg1 = tc_get_register (0); 16062 SKIP_WHITESPACE (); 16063 if (*input_line_pointer != ',') 16064 { 16065 as_bad (_("missing argument separator ',' for .cpsetup")); 16066 return; 16067 } 16068 else 16069 ++input_line_pointer; 16070 SKIP_WHITESPACE (); 16071 if (*input_line_pointer == '$') 16072 { 16073 mips_cpreturn_register = tc_get_register (0); 16074 mips_cpreturn_offset = -1; 16075 } 16076 else 16077 { 16078 mips_cpreturn_offset = get_absolute_expression (); 16079 mips_cpreturn_register = -1; 16080 } 16081 SKIP_WHITESPACE (); 16082 if (*input_line_pointer != ',') 16083 { 16084 as_bad (_("missing argument separator ',' for .cpsetup")); 16085 return; 16086 } 16087 else 16088 ++input_line_pointer; 16089 SKIP_WHITESPACE (); 16090 expression (&ex_sym); 16091 16092 mips_mark_labels (); 16093 mips_assembling_insn = TRUE; 16094 16095 macro_start (); 16096 if (mips_cpreturn_register == -1) 16097 { 16098 ex_off.X_op = O_constant; 16099 ex_off.X_add_symbol = NULL; 16100 ex_off.X_op_symbol = NULL; 16101 ex_off.X_add_number = mips_cpreturn_offset; 16102 16103 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, 16104 BFD_RELOC_LO16, SP); 16105 } 16106 else 16107 move_register (mips_cpreturn_register, mips_gp_register); 16108 16109 if (mips_in_shared || HAVE_64BIT_SYMBOLS) 16110 { 16111 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, 16112 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, 16113 BFD_RELOC_HI16_S); 16114 16115 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, 16116 mips_gp_register, -1, BFD_RELOC_GPREL16, 16117 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); 16118 16119 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, 16120 mips_gp_register, reg1); 16121 } 16122 else 16123 { 16124 expressionS ex; 16125 16126 ex.X_op = O_symbol; 16127 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); 16128 ex.X_op_symbol = NULL; 16129 ex.X_add_number = 0; 16130 16131 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 16132 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 16133 16134 macro_build_lui (&ex, mips_gp_register); 16135 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 16136 mips_gp_register, BFD_RELOC_LO16); 16137 } 16138 16139 macro_end (); 16140 16141 mips_assembling_insn = FALSE; 16142 demand_empty_rest_of_line (); 16143 } 16144 16145 static void 16146 s_cplocal (int ignore ATTRIBUTE_UNUSED) 16147 { 16148 file_mips_check_options (); 16149 16150 /* If we are not generating SVR4 PIC code, or if this is not NewABI code, 16151 .cplocal is ignored. */ 16152 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16153 { 16154 s_ignore (0); 16155 return; 16156 } 16157 16158 if (mips_opts.mips16) 16159 { 16160 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); 16161 ignore_rest_of_line (); 16162 return; 16163 } 16164 16165 mips_gp_register = tc_get_register (0); 16166 demand_empty_rest_of_line (); 16167 } 16168 16169 /* Handle the .cprestore pseudo-op. This stores $gp into a given 16170 offset from $sp. The offset is remembered, and after making a PIC 16171 call $gp is restored from that location. */ 16172 16173 static void 16174 s_cprestore (int ignore ATTRIBUTE_UNUSED) 16175 { 16176 expressionS ex; 16177 16178 file_mips_check_options (); 16179 16180 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 16181 .cprestore is ignored. */ 16182 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 16183 { 16184 s_ignore (0); 16185 return; 16186 } 16187 16188 if (mips_opts.mips16) 16189 { 16190 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); 16191 ignore_rest_of_line (); 16192 return; 16193 } 16194 16195 mips_cprestore_offset = get_absolute_expression (); 16196 mips_cprestore_valid = 1; 16197 16198 ex.X_op = O_constant; 16199 ex.X_add_symbol = NULL; 16200 ex.X_op_symbol = NULL; 16201 ex.X_add_number = mips_cprestore_offset; 16202 16203 mips_mark_labels (); 16204 mips_assembling_insn = TRUE; 16205 16206 macro_start (); 16207 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, 16208 SP, HAVE_64BIT_ADDRESSES); 16209 macro_end (); 16210 16211 mips_assembling_insn = FALSE; 16212 demand_empty_rest_of_line (); 16213 } 16214 16215 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset 16216 was given in the preceding .cpsetup, it results in: 16217 ld $gp, offset($sp) 16218 16219 If a register $reg2 was given there, it results in: 16220 or $gp, $reg2, $0 */ 16221 16222 static void 16223 s_cpreturn (int ignore ATTRIBUTE_UNUSED) 16224 { 16225 expressionS ex; 16226 16227 file_mips_check_options (); 16228 16229 /* If we are not generating SVR4 PIC code, .cpreturn is ignored. 16230 We also need NewABI support. */ 16231 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16232 { 16233 s_ignore (0); 16234 return; 16235 } 16236 16237 if (mips_opts.mips16) 16238 { 16239 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); 16240 ignore_rest_of_line (); 16241 return; 16242 } 16243 16244 mips_mark_labels (); 16245 mips_assembling_insn = TRUE; 16246 16247 macro_start (); 16248 if (mips_cpreturn_register == -1) 16249 { 16250 ex.X_op = O_constant; 16251 ex.X_add_symbol = NULL; 16252 ex.X_op_symbol = NULL; 16253 ex.X_add_number = mips_cpreturn_offset; 16254 16255 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); 16256 } 16257 else 16258 move_register (mips_gp_register, mips_cpreturn_register); 16259 16260 macro_end (); 16261 16262 mips_assembling_insn = FALSE; 16263 demand_empty_rest_of_line (); 16264 } 16265 16266 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword 16267 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size 16268 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF 16269 debug information or MIPS16 TLS. */ 16270 16271 static void 16272 s_tls_rel_directive (const size_t bytes, const char *dirstr, 16273 bfd_reloc_code_real_type rtype) 16274 { 16275 expressionS ex; 16276 char *p; 16277 16278 expression (&ex); 16279 16280 if (ex.X_op != O_symbol) 16281 { 16282 as_bad (_("unsupported use of %s"), dirstr); 16283 ignore_rest_of_line (); 16284 } 16285 16286 p = frag_more (bytes); 16287 md_number_to_chars (p, 0, bytes); 16288 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); 16289 demand_empty_rest_of_line (); 16290 mips_clear_insn_labels (); 16291 } 16292 16293 /* Handle .dtprelword. */ 16294 16295 static void 16296 s_dtprelword (int ignore ATTRIBUTE_UNUSED) 16297 { 16298 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); 16299 } 16300 16301 /* Handle .dtpreldword. */ 16302 16303 static void 16304 s_dtpreldword (int ignore ATTRIBUTE_UNUSED) 16305 { 16306 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); 16307 } 16308 16309 /* Handle .tprelword. */ 16310 16311 static void 16312 s_tprelword (int ignore ATTRIBUTE_UNUSED) 16313 { 16314 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); 16315 } 16316 16317 /* Handle .tpreldword. */ 16318 16319 static void 16320 s_tpreldword (int ignore ATTRIBUTE_UNUSED) 16321 { 16322 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); 16323 } 16324 16325 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC 16326 code. It sets the offset to use in gp_rel relocations. */ 16327 16328 static void 16329 s_gpvalue (int ignore ATTRIBUTE_UNUSED) 16330 { 16331 /* If we are not generating SVR4 PIC code, .gpvalue is ignored. 16332 We also need NewABI support. */ 16333 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16334 { 16335 s_ignore (0); 16336 return; 16337 } 16338 16339 mips_gprel_offset = get_absolute_expression (); 16340 16341 demand_empty_rest_of_line (); 16342 } 16343 16344 /* Handle the .gpword pseudo-op. This is used when generating PIC 16345 code. It generates a 32 bit GP relative reloc. */ 16346 16347 static void 16348 s_gpword (int ignore ATTRIBUTE_UNUSED) 16349 { 16350 segment_info_type *si; 16351 struct insn_label_list *l; 16352 expressionS ex; 16353 char *p; 16354 16355 /* When not generating PIC code, this is treated as .word. */ 16356 if (mips_pic != SVR4_PIC) 16357 { 16358 s_cons (2); 16359 return; 16360 } 16361 16362 si = seg_info (now_seg); 16363 l = si->label_list; 16364 mips_emit_delays (); 16365 if (auto_align) 16366 mips_align (2, 0, l); 16367 16368 expression (&ex); 16369 mips_clear_insn_labels (); 16370 16371 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16372 { 16373 as_bad (_("unsupported use of .gpword")); 16374 ignore_rest_of_line (); 16375 } 16376 16377 p = frag_more (4); 16378 md_number_to_chars (p, 0, 4); 16379 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16380 BFD_RELOC_GPREL32); 16381 16382 demand_empty_rest_of_line (); 16383 } 16384 16385 static void 16386 s_gpdword (int ignore ATTRIBUTE_UNUSED) 16387 { 16388 segment_info_type *si; 16389 struct insn_label_list *l; 16390 expressionS ex; 16391 char *p; 16392 16393 /* When not generating PIC code, this is treated as .dword. */ 16394 if (mips_pic != SVR4_PIC) 16395 { 16396 s_cons (3); 16397 return; 16398 } 16399 16400 si = seg_info (now_seg); 16401 l = si->label_list; 16402 mips_emit_delays (); 16403 if (auto_align) 16404 mips_align (3, 0, l); 16405 16406 expression (&ex); 16407 mips_clear_insn_labels (); 16408 16409 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16410 { 16411 as_bad (_("unsupported use of .gpdword")); 16412 ignore_rest_of_line (); 16413 } 16414 16415 p = frag_more (8); 16416 md_number_to_chars (p, 0, 8); 16417 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16418 BFD_RELOC_GPREL32)->fx_tcbit = 1; 16419 16420 /* GPREL32 composed with 64 gives a 64-bit GP offset. */ 16421 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, 16422 FALSE, BFD_RELOC_64)->fx_tcbit = 1; 16423 16424 demand_empty_rest_of_line (); 16425 } 16426 16427 /* Handle the .ehword pseudo-op. This is used when generating unwinding 16428 tables. It generates a R_MIPS_EH reloc. */ 16429 16430 static void 16431 s_ehword (int ignore ATTRIBUTE_UNUSED) 16432 { 16433 expressionS ex; 16434 char *p; 16435 16436 mips_emit_delays (); 16437 16438 expression (&ex); 16439 mips_clear_insn_labels (); 16440 16441 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16442 { 16443 as_bad (_("unsupported use of .ehword")); 16444 ignore_rest_of_line (); 16445 } 16446 16447 p = frag_more (4); 16448 md_number_to_chars (p, 0, 4); 16449 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16450 BFD_RELOC_32_PCREL); 16451 16452 demand_empty_rest_of_line (); 16453 } 16454 16455 /* Handle the .cpadd pseudo-op. This is used when dealing with switch 16456 tables in SVR4 PIC code. */ 16457 16458 static void 16459 s_cpadd (int ignore ATTRIBUTE_UNUSED) 16460 { 16461 int reg; 16462 16463 file_mips_check_options (); 16464 16465 /* This is ignored when not generating SVR4 PIC code. */ 16466 if (mips_pic != SVR4_PIC) 16467 { 16468 s_ignore (0); 16469 return; 16470 } 16471 16472 mips_mark_labels (); 16473 mips_assembling_insn = TRUE; 16474 16475 /* Add $gp to the register named as an argument. */ 16476 macro_start (); 16477 reg = tc_get_register (0); 16478 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); 16479 macro_end (); 16480 16481 mips_assembling_insn = FALSE; 16482 demand_empty_rest_of_line (); 16483 } 16484 16485 /* Handle the .insn pseudo-op. This marks instruction labels in 16486 mips16/micromips mode. This permits the linker to handle them specially, 16487 such as generating jalx instructions when needed. We also make 16488 them odd for the duration of the assembly, in order to generate the 16489 right sort of code. We will make them even in the adjust_symtab 16490 routine, while leaving them marked. This is convenient for the 16491 debugger and the disassembler. The linker knows to make them odd 16492 again. */ 16493 16494 static void 16495 s_insn (int ignore ATTRIBUTE_UNUSED) 16496 { 16497 file_mips_check_options (); 16498 file_ase_mips16 |= mips_opts.mips16; 16499 file_ase_micromips |= mips_opts.micromips; 16500 16501 mips_mark_labels (); 16502 16503 demand_empty_rest_of_line (); 16504 } 16505 16506 /* Handle the .nan pseudo-op. */ 16507 16508 static void 16509 s_nan (int ignore ATTRIBUTE_UNUSED) 16510 { 16511 static const char str_legacy[] = "legacy"; 16512 static const char str_2008[] = "2008"; 16513 size_t i; 16514 16515 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); 16516 16517 if (i == sizeof (str_2008) - 1 16518 && memcmp (input_line_pointer, str_2008, i) == 0) 16519 mips_nan2008 = 1; 16520 else if (i == sizeof (str_legacy) - 1 16521 && memcmp (input_line_pointer, str_legacy, i) == 0) 16522 { 16523 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) 16524 mips_nan2008 = 0; 16525 else 16526 as_bad (_("`%s' does not support legacy NaN"), 16527 mips_cpu_info_from_isa (file_mips_opts.isa)->name); 16528 } 16529 else 16530 as_bad (_("bad .nan directive")); 16531 16532 input_line_pointer += i; 16533 demand_empty_rest_of_line (); 16534 } 16535 16536 /* Handle a .stab[snd] directive. Ideally these directives would be 16537 implemented in a transparent way, so that removing them would not 16538 have any effect on the generated instructions. However, s_stab 16539 internally changes the section, so in practice we need to decide 16540 now whether the preceding label marks compressed code. We do not 16541 support changing the compression mode of a label after a .stab* 16542 directive, such as in: 16543 16544 foo: 16545 .stabs ... 16546 .set mips16 16547 16548 so the current mode wins. */ 16549 16550 static void 16551 s_mips_stab (int type) 16552 { 16553 mips_mark_labels (); 16554 s_stab (type); 16555 } 16556 16557 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ 16558 16559 static void 16560 s_mips_weakext (int ignore ATTRIBUTE_UNUSED) 16561 { 16562 char *name; 16563 int c; 16564 symbolS *symbolP; 16565 expressionS exp; 16566 16567 c = get_symbol_name (&name); 16568 symbolP = symbol_find_or_make (name); 16569 S_SET_WEAK (symbolP); 16570 *input_line_pointer = c; 16571 16572 SKIP_WHITESPACE_AFTER_NAME (); 16573 16574 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 16575 { 16576 if (S_IS_DEFINED (symbolP)) 16577 { 16578 as_bad (_("ignoring attempt to redefine symbol %s"), 16579 S_GET_NAME (symbolP)); 16580 ignore_rest_of_line (); 16581 return; 16582 } 16583 16584 if (*input_line_pointer == ',') 16585 { 16586 ++input_line_pointer; 16587 SKIP_WHITESPACE (); 16588 } 16589 16590 expression (&exp); 16591 if (exp.X_op != O_symbol) 16592 { 16593 as_bad (_("bad .weakext directive")); 16594 ignore_rest_of_line (); 16595 return; 16596 } 16597 symbol_set_value_expression (symbolP, &exp); 16598 } 16599 16600 demand_empty_rest_of_line (); 16601 } 16602 16603 /* Parse a register string into a number. Called from the ECOFF code 16604 to parse .frame. The argument is non-zero if this is the frame 16605 register, so that we can record it in mips_frame_reg. */ 16606 16607 int 16608 tc_get_register (int frame) 16609 { 16610 unsigned int reg; 16611 16612 SKIP_WHITESPACE (); 16613 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) 16614 reg = 0; 16615 if (frame) 16616 { 16617 mips_frame_reg = reg != 0 ? reg : SP; 16618 mips_frame_reg_valid = 1; 16619 mips_cprestore_valid = 0; 16620 } 16621 return reg; 16622 } 16623 16624 valueT 16625 md_section_align (asection *seg, valueT addr) 16626 { 16627 int align = bfd_get_section_alignment (stdoutput, seg); 16628 16629 /* We don't need to align ELF sections to the full alignment. 16630 However, Irix 5 may prefer that we align them at least to a 16 16631 byte boundary. We don't bother to align the sections if we 16632 are targeted for an embedded system. */ 16633 if (strncmp (TARGET_OS, "elf", 3) == 0) 16634 return addr; 16635 if (align > 4) 16636 align = 4; 16637 16638 return ((addr + (1 << align) - 1) & -(1 << align)); 16639 } 16640 16641 /* Utility routine, called from above as well. If called while the 16642 input file is still being read, it's only an approximation. (For 16643 example, a symbol may later become defined which appeared to be 16644 undefined earlier.) */ 16645 16646 static int 16647 nopic_need_relax (symbolS *sym, int before_relaxing) 16648 { 16649 if (sym == 0) 16650 return 0; 16651 16652 if (g_switch_value > 0) 16653 { 16654 const char *symname; 16655 int change; 16656 16657 /* Find out whether this symbol can be referenced off the $gp 16658 register. It can be if it is smaller than the -G size or if 16659 it is in the .sdata or .sbss section. Certain symbols can 16660 not be referenced off the $gp, although it appears as though 16661 they can. */ 16662 symname = S_GET_NAME (sym); 16663 if (symname != (const char *) NULL 16664 && (strcmp (symname, "eprol") == 0 16665 || strcmp (symname, "etext") == 0 16666 || strcmp (symname, "_gp") == 0 16667 || strcmp (symname, "edata") == 0 16668 || strcmp (symname, "_fbss") == 0 16669 || strcmp (symname, "_fdata") == 0 16670 || strcmp (symname, "_ftext") == 0 16671 || strcmp (symname, "end") == 0 16672 || strcmp (symname, "_gp_disp") == 0)) 16673 change = 1; 16674 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) 16675 && (0 16676 #ifndef NO_ECOFF_DEBUGGING 16677 || (symbol_get_obj (sym)->ecoff_extern_size != 0 16678 && (symbol_get_obj (sym)->ecoff_extern_size 16679 <= g_switch_value)) 16680 #endif 16681 /* We must defer this decision until after the whole 16682 file has been read, since there might be a .extern 16683 after the first use of this symbol. */ 16684 || (before_relaxing 16685 #ifndef NO_ECOFF_DEBUGGING 16686 && symbol_get_obj (sym)->ecoff_extern_size == 0 16687 #endif 16688 && S_GET_VALUE (sym) == 0) 16689 || (S_GET_VALUE (sym) != 0 16690 && S_GET_VALUE (sym) <= g_switch_value))) 16691 change = 0; 16692 else 16693 { 16694 const char *segname; 16695 16696 segname = segment_name (S_GET_SEGMENT (sym)); 16697 gas_assert (strcmp (segname, ".lit8") != 0 16698 && strcmp (segname, ".lit4") != 0); 16699 change = (strcmp (segname, ".sdata") != 0 16700 && strcmp (segname, ".sbss") != 0 16701 && strncmp (segname, ".sdata.", 7) != 0 16702 && strncmp (segname, ".sbss.", 6) != 0 16703 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 16704 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); 16705 } 16706 return change; 16707 } 16708 else 16709 /* We are not optimizing for the $gp register. */ 16710 return 1; 16711 } 16712 16713 16714 /* Return true if the given symbol should be considered local for SVR4 PIC. */ 16715 16716 static bfd_boolean 16717 pic_need_relax (symbolS *sym, asection *segtype) 16718 { 16719 asection *symsec; 16720 16721 /* Handle the case of a symbol equated to another symbol. */ 16722 while (symbol_equated_reloc_p (sym)) 16723 { 16724 symbolS *n; 16725 16726 /* It's possible to get a loop here in a badly written program. */ 16727 n = symbol_get_value_expression (sym)->X_add_symbol; 16728 if (n == sym) 16729 break; 16730 sym = n; 16731 } 16732 16733 if (symbol_section_p (sym)) 16734 return TRUE; 16735 16736 symsec = S_GET_SEGMENT (sym); 16737 16738 /* This must duplicate the test in adjust_reloc_syms. */ 16739 return (!bfd_is_und_section (symsec) 16740 && !bfd_is_abs_section (symsec) 16741 && !bfd_is_com_section (symsec) 16742 && !s_is_linkonce (sym, segtype) 16743 /* A global or weak symbol is treated as external. */ 16744 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); 16745 } 16746 16747 16748 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an 16749 extended opcode. SEC is the section the frag is in. */ 16750 16751 static int 16752 mips16_extended_frag (fragS *fragp, asection *sec, long stretch) 16753 { 16754 int type; 16755 const struct mips_int_operand *operand; 16756 offsetT val; 16757 segT symsec; 16758 fragS *sym_frag; 16759 16760 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 16761 return 0; 16762 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 16763 return 1; 16764 16765 symsec = S_GET_SEGMENT (fragp->fr_symbol); 16766 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 16767 operand = mips16_immed_operand (type, FALSE); 16768 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) 16769 || (operand->root.type == OP_PCREL 16770 ? sec != symsec 16771 : !bfd_is_abs_section (symsec))) 16772 return 1; 16773 16774 sym_frag = symbol_get_frag (fragp->fr_symbol); 16775 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 16776 16777 if (operand->root.type == OP_PCREL) 16778 { 16779 const struct mips_pcrel_operand *pcrel_op; 16780 addressT addr; 16781 offsetT maxtiny; 16782 16783 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) 16784 return 1; 16785 16786 pcrel_op = (const struct mips_pcrel_operand *) operand; 16787 16788 /* If the relax_marker of the symbol fragment differs from the 16789 relax_marker of this fragment, we have not yet adjusted the 16790 symbol fragment fr_address. We want to add in STRETCH in 16791 order to get a better estimate of the address. This 16792 particularly matters because of the shift bits. */ 16793 if (stretch != 0 16794 && sym_frag->relax_marker != fragp->relax_marker) 16795 { 16796 fragS *f; 16797 16798 /* Adjust stretch for any alignment frag. Note that if have 16799 been expanding the earlier code, the symbol may be 16800 defined in what appears to be an earlier frag. FIXME: 16801 This doesn't handle the fr_subtype field, which specifies 16802 a maximum number of bytes to skip when doing an 16803 alignment. */ 16804 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 16805 { 16806 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 16807 { 16808 if (stretch < 0) 16809 stretch = - ((- stretch) 16810 & ~ ((1 << (int) f->fr_offset) - 1)); 16811 else 16812 stretch &= ~ ((1 << (int) f->fr_offset) - 1); 16813 if (stretch == 0) 16814 break; 16815 } 16816 } 16817 if (f != NULL) 16818 val += stretch; 16819 } 16820 16821 addr = fragp->fr_address + fragp->fr_fix; 16822 16823 /* The base address rules are complicated. The base address of 16824 a branch is the following instruction. The base address of a 16825 PC relative load or add is the instruction itself, but if it 16826 is in a delay slot (in which case it can not be extended) use 16827 the address of the instruction whose delay slot it is in. */ 16828 if (pcrel_op->include_isa_bit) 16829 { 16830 addr += 2; 16831 16832 /* If we are currently assuming that this frag should be 16833 extended, then, the current address is two bytes 16834 higher. */ 16835 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 16836 addr += 2; 16837 16838 /* Ignore the low bit in the target, since it will be set 16839 for a text label. */ 16840 val &= -2; 16841 } 16842 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 16843 addr -= 4; 16844 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 16845 addr -= 2; 16846 16847 val -= addr & -(1 << pcrel_op->align_log2); 16848 16849 /* If any of the shifted bits are set, we must use an extended 16850 opcode. If the address depends on the size of this 16851 instruction, this can lead to a loop, so we arrange to always 16852 use an extended opcode. */ 16853 if ((val & ((1 << operand->shift) - 1)) != 0) 16854 { 16855 fragp->fr_subtype = 16856 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 16857 return 1; 16858 } 16859 16860 /* If we are about to mark a frag as extended because the value 16861 is precisely the next value above maxtiny, then there is a 16862 chance of an infinite loop as in the following code: 16863 la $4,foo 16864 .skip 1020 16865 .align 2 16866 foo: 16867 In this case when the la is extended, foo is 0x3fc bytes 16868 away, so the la can be shrunk, but then foo is 0x400 away, so 16869 the la must be extended. To avoid this loop, we mark the 16870 frag as extended if it was small, and is about to become 16871 extended with the next value above maxtiny. */ 16872 maxtiny = mips_int_operand_max (operand); 16873 if (val == maxtiny + (1 << operand->shift) 16874 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 16875 { 16876 fragp->fr_subtype = 16877 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 16878 return 1; 16879 } 16880 } 16881 16882 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); 16883 } 16884 16885 /* Compute the length of a branch sequence, and adjust the 16886 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 16887 worst-case length is computed, with UPDATE being used to indicate 16888 whether an unconditional (-1), branch-likely (+1) or regular (0) 16889 branch is to be computed. */ 16890 static int 16891 relaxed_branch_length (fragS *fragp, asection *sec, int update) 16892 { 16893 bfd_boolean toofar; 16894 int length; 16895 16896 if (fragp 16897 && S_IS_DEFINED (fragp->fr_symbol) 16898 && !S_IS_WEAK (fragp->fr_symbol) 16899 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 16900 { 16901 addressT addr; 16902 offsetT val; 16903 16904 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 16905 16906 addr = fragp->fr_address + fragp->fr_fix + 4; 16907 16908 val -= addr; 16909 16910 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); 16911 } 16912 else 16913 /* If the symbol is not defined or it's in a different segment, 16914 we emit the long sequence. */ 16915 toofar = TRUE; 16916 16917 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 16918 fragp->fr_subtype 16919 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), 16920 RELAX_BRANCH_UNCOND (fragp->fr_subtype), 16921 RELAX_BRANCH_LIKELY (fragp->fr_subtype), 16922 RELAX_BRANCH_LINK (fragp->fr_subtype), 16923 toofar); 16924 16925 length = 4; 16926 if (toofar) 16927 { 16928 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) 16929 length += 8; 16930 16931 if (mips_pic != NO_PIC) 16932 { 16933 /* Additional space for PIC loading of target address. */ 16934 length += 8; 16935 if (mips_opts.isa == ISA_MIPS1) 16936 /* Additional space for $at-stabilizing nop. */ 16937 length += 4; 16938 } 16939 16940 /* If branch is conditional. */ 16941 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) 16942 length += 8; 16943 } 16944 16945 return length; 16946 } 16947 16948 /* Compute the length of a branch sequence, and adjust the 16949 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the 16950 worst-case length is computed, with UPDATE being used to indicate 16951 whether an unconditional (-1), or regular (0) branch is to be 16952 computed. */ 16953 16954 static int 16955 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) 16956 { 16957 bfd_boolean toofar; 16958 int length; 16959 16960 if (fragp 16961 && S_IS_DEFINED (fragp->fr_symbol) 16962 && !S_IS_WEAK (fragp->fr_symbol) 16963 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 16964 { 16965 addressT addr; 16966 offsetT val; 16967 16968 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 16969 /* Ignore the low bit in the target, since it will be set 16970 for a text label. */ 16971 if ((val & 1) != 0) 16972 --val; 16973 16974 addr = fragp->fr_address + fragp->fr_fix + 4; 16975 16976 val -= addr; 16977 16978 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); 16979 } 16980 else 16981 /* If the symbol is not defined or it's in a different segment, 16982 we emit the long sequence. */ 16983 toofar = TRUE; 16984 16985 if (fragp && update 16986 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 16987 fragp->fr_subtype = (toofar 16988 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) 16989 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); 16990 16991 length = 4; 16992 if (toofar) 16993 { 16994 bfd_boolean compact_known = fragp != NULL; 16995 bfd_boolean compact = FALSE; 16996 bfd_boolean uncond; 16997 16998 if (compact_known) 16999 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 17000 if (fragp) 17001 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); 17002 else 17003 uncond = update < 0; 17004 17005 /* If label is out of range, we turn branch <br>: 17006 17007 <br> label # 4 bytes 17008 0: 17009 17010 into: 17011 17012 j label # 4 bytes 17013 nop # 2 bytes if compact && !PIC 17014 0: 17015 */ 17016 if (mips_pic == NO_PIC && (!compact_known || compact)) 17017 length += 2; 17018 17019 /* If assembling PIC code, we further turn: 17020 17021 j label # 4 bytes 17022 17023 into: 17024 17025 lw/ld at, %got(label)(gp) # 4 bytes 17026 d/addiu at, %lo(label) # 4 bytes 17027 jr/c at # 2 bytes 17028 */ 17029 if (mips_pic != NO_PIC) 17030 length += 6; 17031 17032 /* If branch <br> is conditional, we prepend negated branch <brneg>: 17033 17034 <brneg> 0f # 4 bytes 17035 nop # 2 bytes if !compact 17036 */ 17037 if (!uncond) 17038 length += (compact_known && compact) ? 4 : 6; 17039 } 17040 17041 return length; 17042 } 17043 17044 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 17045 bit accordingly. */ 17046 17047 static int 17048 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) 17049 { 17050 bfd_boolean toofar; 17051 17052 if (fragp 17053 && S_IS_DEFINED (fragp->fr_symbol) 17054 && !S_IS_WEAK (fragp->fr_symbol) 17055 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 17056 { 17057 addressT addr; 17058 offsetT val; 17059 int type; 17060 17061 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17062 /* Ignore the low bit in the target, since it will be set 17063 for a text label. */ 17064 if ((val & 1) != 0) 17065 --val; 17066 17067 /* Assume this is a 2-byte branch. */ 17068 addr = fragp->fr_address + fragp->fr_fix + 2; 17069 17070 /* We try to avoid the infinite loop by not adding 2 more bytes for 17071 long branches. */ 17072 17073 val -= addr; 17074 17075 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 17076 if (type == 'D') 17077 toofar = val < - (0x200 << 1) || val >= (0x200 << 1); 17078 else if (type == 'E') 17079 toofar = val < - (0x40 << 1) || val >= (0x40 << 1); 17080 else 17081 abort (); 17082 } 17083 else 17084 /* If the symbol is not defined or it's in a different segment, 17085 we emit a normal 32-bit branch. */ 17086 toofar = TRUE; 17087 17088 if (fragp && update 17089 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 17090 fragp->fr_subtype 17091 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) 17092 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); 17093 17094 if (toofar) 17095 return 4; 17096 17097 return 2; 17098 } 17099 17100 /* Estimate the size of a frag before relaxing. Unless this is the 17101 mips16, we are not really relaxing here, and the final size is 17102 encoded in the subtype information. For the mips16, we have to 17103 decide whether we are using an extended opcode or not. */ 17104 17105 int 17106 md_estimate_size_before_relax (fragS *fragp, asection *segtype) 17107 { 17108 int change; 17109 17110 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17111 { 17112 17113 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); 17114 17115 return fragp->fr_var; 17116 } 17117 17118 if (RELAX_MIPS16_P (fragp->fr_subtype)) 17119 /* We don't want to modify the EXTENDED bit here; it might get us 17120 into infinite loops. We change it only in mips_relax_frag(). */ 17121 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); 17122 17123 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17124 { 17125 int length = 4; 17126 17127 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 17128 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); 17129 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 17130 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); 17131 fragp->fr_var = length; 17132 17133 return length; 17134 } 17135 17136 if (mips_pic == NO_PIC) 17137 change = nopic_need_relax (fragp->fr_symbol, 0); 17138 else if (mips_pic == SVR4_PIC) 17139 change = pic_need_relax (fragp->fr_symbol, segtype); 17140 else if (mips_pic == VXWORKS_PIC) 17141 /* For vxworks, GOT16 relocations never have a corresponding LO16. */ 17142 change = 0; 17143 else 17144 abort (); 17145 17146 if (change) 17147 { 17148 fragp->fr_subtype |= RELAX_USE_SECOND; 17149 return -RELAX_FIRST (fragp->fr_subtype); 17150 } 17151 else 17152 return -RELAX_SECOND (fragp->fr_subtype); 17153 } 17154 17155 /* This is called to see whether a reloc against a defined symbol 17156 should be converted into a reloc against a section. */ 17157 17158 int 17159 mips_fix_adjustable (fixS *fixp) 17160 { 17161 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 17162 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 17163 return 0; 17164 17165 if (fixp->fx_addsy == NULL) 17166 return 1; 17167 17168 /* Allow relocs used for EH tables. */ 17169 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 17170 return 1; 17171 17172 /* If symbol SYM is in a mergeable section, relocations of the form 17173 SYM + 0 can usually be made section-relative. The mergeable data 17174 is then identified by the section offset rather than by the symbol. 17175 17176 However, if we're generating REL LO16 relocations, the offset is split 17177 between the LO16 and parterning high part relocation. The linker will 17178 need to recalculate the complete offset in order to correctly identify 17179 the merge data. 17180 17181 The linker has traditionally not looked for the parterning high part 17182 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be 17183 placed anywhere. Rather than break backwards compatibility by changing 17184 this, it seems better not to force the issue, and instead keep the 17185 original symbol. This will work with either linker behavior. */ 17186 if ((lo16_reloc_p (fixp->fx_r_type) 17187 || reloc_needs_lo_p (fixp->fx_r_type)) 17188 && HAVE_IN_PLACE_ADDENDS 17189 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) 17190 return 0; 17191 17192 /* There is no place to store an in-place offset for JALR relocations. */ 17193 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) 17194 return 0; 17195 17196 /* Likewise an in-range offset of limited PC-relative relocations may 17197 overflow the in-place relocatable field if recalculated against the 17198 start address of the symbol's containing section. 17199 17200 Also, PC relative relocations for MIPS R6 need to be symbol rather than 17201 section relative to allow linker relaxations to be performed later on. */ 17202 if (limited_pcrel_reloc_p (fixp->fx_r_type) 17203 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) 17204 return 0; 17205 17206 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve 17207 to a floating-point stub. The same is true for non-R_MIPS16_26 17208 relocations against MIPS16 functions; in this case, the stub becomes 17209 the function's canonical address. 17210 17211 Floating-point stubs are stored in unique .mips16.call.* or 17212 .mips16.fn.* sections. If a stub T for function F is in section S, 17213 the first relocation in section S must be against F; this is how the 17214 linker determines the target function. All relocations that might 17215 resolve to T must also be against F. We therefore have the following 17216 restrictions, which are given in an intentionally-redundant way: 17217 17218 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 17219 symbols. 17220 17221 2. We cannot reduce a stub's relocations against non-MIPS16 symbols 17222 if that stub might be used. 17223 17224 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 17225 symbols. 17226 17227 4. We cannot reduce a stub's relocations against MIPS16 symbols if 17228 that stub might be used. 17229 17230 There is a further restriction: 17231 17232 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or 17233 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, 17234 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, 17235 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) 17236 against MIPS16 or microMIPS symbols because we need to keep the 17237 MIPS16 or microMIPS symbol for the purpose of mode mismatch 17238 detection and JAL to JALX instruction conversion in the linker. 17239 17240 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation 17241 against a MIPS16 symbol. We deal with (5) by additionally leaving 17242 alone any jump and branch relocations against a microMIPS symbol. 17243 17244 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 17245 relocation against some symbol R, no relocation against R may be 17246 reduced. (Note that this deals with (2) as well as (1) because 17247 relocations against global symbols will never be reduced on ELF 17248 targets.) This approach is a little simpler than trying to detect 17249 stub sections, and gives the "all or nothing" per-symbol consistency 17250 that we have for MIPS16 symbols. */ 17251 if (fixp->fx_subsy == NULL 17252 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) 17253 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) 17254 && (jmp_reloc_p (fixp->fx_r_type) 17255 || b_reloc_p (fixp->fx_r_type))) 17256 || *symbol_get_tc (fixp->fx_addsy))) 17257 return 0; 17258 17259 return 1; 17260 } 17261 17262 /* Translate internal representation of relocation info to BFD target 17263 format. */ 17264 17265 arelent ** 17266 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 17267 { 17268 static arelent *retval[4]; 17269 arelent *reloc; 17270 bfd_reloc_code_real_type code; 17271 17272 memset (retval, 0, sizeof(retval)); 17273 reloc = retval[0] = XCNEW (arelent); 17274 reloc->sym_ptr_ptr = XNEW (asymbol *); 17275 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 17276 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 17277 17278 if (fixp->fx_pcrel) 17279 { 17280 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 17281 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 17282 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 17283 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 17284 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 17285 || fixp->fx_r_type == BFD_RELOC_32_PCREL 17286 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 17287 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 17288 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 17289 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 17290 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 17291 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); 17292 17293 /* At this point, fx_addnumber is "symbol offset - pcrel address". 17294 Relocations want only the symbol offset. */ 17295 switch (fixp->fx_r_type) 17296 { 17297 case BFD_RELOC_MIPS_18_PCREL_S3: 17298 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); 17299 break; 17300 default: 17301 reloc->addend = fixp->fx_addnumber + reloc->address; 17302 break; 17303 } 17304 } 17305 else if (HAVE_IN_PLACE_ADDENDS 17306 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP 17307 && (read_compressed_insn (fixp->fx_frag->fr_literal 17308 + fixp->fx_where, 4) >> 26) == 0x3c) 17309 { 17310 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place 17311 addend accordingly. */ 17312 reloc->addend = fixp->fx_addnumber >> 1; 17313 } 17314 else 17315 reloc->addend = fixp->fx_addnumber; 17316 17317 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable 17318 entry to be used in the relocation's section offset. */ 17319 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 17320 { 17321 reloc->address = reloc->addend; 17322 reloc->addend = 0; 17323 } 17324 17325 code = fixp->fx_r_type; 17326 17327 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 17328 if (reloc->howto == NULL) 17329 { 17330 as_bad_where (fixp->fx_file, fixp->fx_line, 17331 _("cannot represent %s relocation in this object file" 17332 " format"), 17333 bfd_get_reloc_code_name (code)); 17334 retval[0] = NULL; 17335 } 17336 17337 return retval; 17338 } 17339 17340 /* Relax a machine dependent frag. This returns the amount by which 17341 the current size of the frag should change. */ 17342 17343 int 17344 mips_relax_frag (asection *sec, fragS *fragp, long stretch) 17345 { 17346 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17347 { 17348 offsetT old_var = fragp->fr_var; 17349 17350 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 17351 17352 return fragp->fr_var - old_var; 17353 } 17354 17355 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17356 { 17357 offsetT old_var = fragp->fr_var; 17358 offsetT new_var = 4; 17359 17360 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 17361 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); 17362 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 17363 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); 17364 fragp->fr_var = new_var; 17365 17366 return new_var - old_var; 17367 } 17368 17369 if (! RELAX_MIPS16_P (fragp->fr_subtype)) 17370 return 0; 17371 17372 if (mips16_extended_frag (fragp, sec, stretch)) 17373 { 17374 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17375 return 0; 17376 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 17377 return 2; 17378 } 17379 else 17380 { 17381 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17382 return 0; 17383 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 17384 return -2; 17385 } 17386 17387 return 0; 17388 } 17389 17390 /* Convert a machine dependent frag. */ 17391 17392 void 17393 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) 17394 { 17395 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17396 { 17397 char *buf; 17398 unsigned long insn; 17399 expressionS exp; 17400 fixS *fixp; 17401 17402 buf = fragp->fr_literal + fragp->fr_fix; 17403 insn = read_insn (buf); 17404 17405 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 17406 { 17407 /* We generate a fixup instead of applying it right now 17408 because, if there are linker relaxations, we're going to 17409 need the relocations. */ 17410 exp.X_op = O_symbol; 17411 exp.X_add_symbol = fragp->fr_symbol; 17412 exp.X_add_number = fragp->fr_offset; 17413 17414 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, 17415 BFD_RELOC_16_PCREL_S2); 17416 fixp->fx_file = fragp->fr_file; 17417 fixp->fx_line = fragp->fr_line; 17418 17419 buf = write_insn (buf, insn); 17420 } 17421 else 17422 { 17423 int i; 17424 17425 as_warn_where (fragp->fr_file, fragp->fr_line, 17426 _("relaxed out-of-range branch into a jump")); 17427 17428 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) 17429 goto uncond; 17430 17431 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17432 { 17433 /* Reverse the branch. */ 17434 switch ((insn >> 28) & 0xf) 17435 { 17436 case 4: 17437 if ((insn & 0xff000000) == 0x47000000 17438 || (insn & 0xff600000) == 0x45600000) 17439 { 17440 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition 17441 reversed by tweaking bit 23. */ 17442 insn ^= 0x00800000; 17443 } 17444 else 17445 { 17446 /* bc[0-3][tf]l? instructions can have the condition 17447 reversed by tweaking a single TF bit, and their 17448 opcodes all have 0x4???????. */ 17449 gas_assert ((insn & 0xf3e00000) == 0x41000000); 17450 insn ^= 0x00010000; 17451 } 17452 break; 17453 17454 case 0: 17455 /* bltz 0x04000000 bgez 0x04010000 17456 bltzal 0x04100000 bgezal 0x04110000 */ 17457 gas_assert ((insn & 0xfc0e0000) == 0x04000000); 17458 insn ^= 0x00010000; 17459 break; 17460 17461 case 1: 17462 /* beq 0x10000000 bne 0x14000000 17463 blez 0x18000000 bgtz 0x1c000000 */ 17464 insn ^= 0x04000000; 17465 break; 17466 17467 default: 17468 abort (); 17469 } 17470 } 17471 17472 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 17473 { 17474 /* Clear the and-link bit. */ 17475 gas_assert ((insn & 0xfc1c0000) == 0x04100000); 17476 17477 /* bltzal 0x04100000 bgezal 0x04110000 17478 bltzall 0x04120000 bgezall 0x04130000 */ 17479 insn &= ~0x00100000; 17480 } 17481 17482 /* Branch over the branch (if the branch was likely) or the 17483 full jump (not likely case). Compute the offset from the 17484 current instruction to branch to. */ 17485 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17486 i = 16; 17487 else 17488 { 17489 /* How many bytes in instructions we've already emitted? */ 17490 i = buf - fragp->fr_literal - fragp->fr_fix; 17491 /* How many bytes in instructions from here to the end? */ 17492 i = fragp->fr_var - i; 17493 } 17494 /* Convert to instruction count. */ 17495 i >>= 2; 17496 /* Branch counts from the next instruction. */ 17497 i--; 17498 insn |= i; 17499 /* Branch over the jump. */ 17500 buf = write_insn (buf, insn); 17501 17502 /* nop */ 17503 buf = write_insn (buf, 0); 17504 17505 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17506 { 17507 /* beql $0, $0, 2f */ 17508 insn = 0x50000000; 17509 /* Compute the PC offset from the current instruction to 17510 the end of the variable frag. */ 17511 /* How many bytes in instructions we've already emitted? */ 17512 i = buf - fragp->fr_literal - fragp->fr_fix; 17513 /* How many bytes in instructions from here to the end? */ 17514 i = fragp->fr_var - i; 17515 /* Convert to instruction count. */ 17516 i >>= 2; 17517 /* Don't decrement i, because we want to branch over the 17518 delay slot. */ 17519 insn |= i; 17520 17521 buf = write_insn (buf, insn); 17522 buf = write_insn (buf, 0); 17523 } 17524 17525 uncond: 17526 if (mips_pic == NO_PIC) 17527 { 17528 /* j or jal. */ 17529 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) 17530 ? 0x0c000000 : 0x08000000); 17531 exp.X_op = O_symbol; 17532 exp.X_add_symbol = fragp->fr_symbol; 17533 exp.X_add_number = fragp->fr_offset; 17534 17535 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 17536 FALSE, BFD_RELOC_MIPS_JMP); 17537 fixp->fx_file = fragp->fr_file; 17538 fixp->fx_line = fragp->fr_line; 17539 17540 buf = write_insn (buf, insn); 17541 } 17542 else 17543 { 17544 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); 17545 17546 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ 17547 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; 17548 insn |= at << OP_SH_RT; 17549 exp.X_op = O_symbol; 17550 exp.X_add_symbol = fragp->fr_symbol; 17551 exp.X_add_number = fragp->fr_offset; 17552 17553 if (fragp->fr_offset) 17554 { 17555 exp.X_add_symbol = make_expr_symbol (&exp); 17556 exp.X_add_number = 0; 17557 } 17558 17559 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 17560 FALSE, BFD_RELOC_MIPS_GOT16); 17561 fixp->fx_file = fragp->fr_file; 17562 fixp->fx_line = fragp->fr_line; 17563 17564 buf = write_insn (buf, insn); 17565 17566 if (mips_opts.isa == ISA_MIPS1) 17567 /* nop */ 17568 buf = write_insn (buf, 0); 17569 17570 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ 17571 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; 17572 insn |= at << OP_SH_RS | at << OP_SH_RT; 17573 17574 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 17575 FALSE, BFD_RELOC_LO16); 17576 fixp->fx_file = fragp->fr_file; 17577 fixp->fx_line = fragp->fr_line; 17578 17579 buf = write_insn (buf, insn); 17580 17581 /* j(al)r $at. */ 17582 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 17583 insn = 0x0000f809; 17584 else 17585 insn = 0x00000008; 17586 insn |= at << OP_SH_RS; 17587 17588 buf = write_insn (buf, insn); 17589 } 17590 } 17591 17592 fragp->fr_fix += fragp->fr_var; 17593 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 17594 return; 17595 } 17596 17597 /* Relax microMIPS branches. */ 17598 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17599 { 17600 char *buf = fragp->fr_literal + fragp->fr_fix; 17601 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 17602 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); 17603 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 17604 bfd_boolean short_ds; 17605 unsigned long insn; 17606 expressionS exp; 17607 fixS *fixp; 17608 17609 exp.X_op = O_symbol; 17610 exp.X_add_symbol = fragp->fr_symbol; 17611 exp.X_add_number = fragp->fr_offset; 17612 17613 fragp->fr_fix += fragp->fr_var; 17614 17615 /* Handle 16-bit branches that fit or are forced to fit. */ 17616 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 17617 { 17618 /* We generate a fixup instead of applying it right now, 17619 because if there is linker relaxation, we're going to 17620 need the relocations. */ 17621 if (type == 'D') 17622 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, 17623 BFD_RELOC_MICROMIPS_10_PCREL_S1); 17624 else if (type == 'E') 17625 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, 17626 BFD_RELOC_MICROMIPS_7_PCREL_S1); 17627 else 17628 abort (); 17629 17630 fixp->fx_file = fragp->fr_file; 17631 fixp->fx_line = fragp->fr_line; 17632 17633 /* These relocations can have an addend that won't fit in 17634 2 octets. */ 17635 fixp->fx_no_overflow = 1; 17636 17637 return; 17638 } 17639 17640 /* Handle 32-bit branches that fit or are forced to fit. */ 17641 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 17642 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 17643 { 17644 /* We generate a fixup instead of applying it right now, 17645 because if there is linker relaxation, we're going to 17646 need the relocations. */ 17647 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, 17648 BFD_RELOC_MICROMIPS_16_PCREL_S1); 17649 fixp->fx_file = fragp->fr_file; 17650 fixp->fx_line = fragp->fr_line; 17651 17652 if (type == 0) 17653 return; 17654 } 17655 17656 /* Relax 16-bit branches to 32-bit branches. */ 17657 if (type != 0) 17658 { 17659 insn = read_compressed_insn (buf, 2); 17660 17661 if ((insn & 0xfc00) == 0xcc00) /* b16 */ 17662 insn = 0x94000000; /* beq */ 17663 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ 17664 { 17665 unsigned long regno; 17666 17667 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; 17668 regno = micromips_to_32_reg_d_map [regno]; 17669 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ 17670 insn |= regno << MICROMIPSOP_SH_RS; 17671 } 17672 else 17673 abort (); 17674 17675 /* Nothing else to do, just write it out. */ 17676 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 17677 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 17678 { 17679 buf = write_compressed_insn (buf, insn, 4); 17680 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 17681 return; 17682 } 17683 } 17684 else 17685 insn = read_compressed_insn (buf, 4); 17686 17687 /* Relax 32-bit branches to a sequence of instructions. */ 17688 as_warn_where (fragp->fr_file, fragp->fr_line, 17689 _("relaxed out-of-range branch into a jump")); 17690 17691 /* Set the short-delay-slot bit. */ 17692 short_ds = al && (insn & 0x02000000) != 0; 17693 17694 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) 17695 { 17696 symbolS *l; 17697 17698 /* Reverse the branch. */ 17699 if ((insn & 0xfc000000) == 0x94000000 /* beq */ 17700 || (insn & 0xfc000000) == 0xb4000000) /* bne */ 17701 insn ^= 0x20000000; 17702 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ 17703 || (insn & 0xffe00000) == 0x40400000 /* bgez */ 17704 || (insn & 0xffe00000) == 0x40800000 /* blez */ 17705 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ 17706 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ 17707 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ 17708 || (insn & 0xffe00000) == 0x40200000 /* bltzal */ 17709 || (insn & 0xffe00000) == 0x40600000 /* bgezal */ 17710 || (insn & 0xffe00000) == 0x42200000 /* bltzals */ 17711 || (insn & 0xffe00000) == 0x42600000) /* bgezals */ 17712 insn ^= 0x00400000; 17713 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ 17714 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ 17715 || (insn & 0xffe30000) == 0x42800000 /* bc2f */ 17716 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ 17717 insn ^= 0x00200000; 17718 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df 17719 BNZ.df */ 17720 || (insn & 0xff600000) == 0x81600000) /* BZ.V 17721 BNZ.V */ 17722 insn ^= 0x00800000; 17723 else 17724 abort (); 17725 17726 if (al) 17727 { 17728 /* Clear the and-link and short-delay-slot bits. */ 17729 gas_assert ((insn & 0xfda00000) == 0x40200000); 17730 17731 /* bltzal 0x40200000 bgezal 0x40600000 */ 17732 /* bltzals 0x42200000 bgezals 0x42600000 */ 17733 insn &= ~0x02200000; 17734 } 17735 17736 /* Make a label at the end for use with the branch. */ 17737 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); 17738 micromips_label_inc (); 17739 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); 17740 17741 /* Refer to it. */ 17742 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, 17743 BFD_RELOC_MICROMIPS_16_PCREL_S1); 17744 fixp->fx_file = fragp->fr_file; 17745 fixp->fx_line = fragp->fr_line; 17746 17747 /* Branch over the jump. */ 17748 buf = write_compressed_insn (buf, insn, 4); 17749 if (!compact) 17750 /* nop */ 17751 buf = write_compressed_insn (buf, 0x0c00, 2); 17752 } 17753 17754 if (mips_pic == NO_PIC) 17755 { 17756 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ 17757 17758 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ 17759 insn = al ? jal : 0xd4000000; 17760 17761 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 17762 BFD_RELOC_MICROMIPS_JMP); 17763 fixp->fx_file = fragp->fr_file; 17764 fixp->fx_line = fragp->fr_line; 17765 17766 buf = write_compressed_insn (buf, insn, 4); 17767 if (compact) 17768 /* nop */ 17769 buf = write_compressed_insn (buf, 0x0c00, 2); 17770 } 17771 else 17772 { 17773 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); 17774 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ 17775 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ 17776 17777 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ 17778 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; 17779 insn |= at << MICROMIPSOP_SH_RT; 17780 17781 if (exp.X_add_number) 17782 { 17783 exp.X_add_symbol = make_expr_symbol (&exp); 17784 exp.X_add_number = 0; 17785 } 17786 17787 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 17788 BFD_RELOC_MICROMIPS_GOT16); 17789 fixp->fx_file = fragp->fr_file; 17790 fixp->fx_line = fragp->fr_line; 17791 17792 buf = write_compressed_insn (buf, insn, 4); 17793 17794 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ 17795 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; 17796 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; 17797 17798 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 17799 BFD_RELOC_MICROMIPS_LO16); 17800 fixp->fx_file = fragp->fr_file; 17801 fixp->fx_line = fragp->fr_line; 17802 17803 buf = write_compressed_insn (buf, insn, 4); 17804 17805 /* jr/jrc/jalr/jalrs $at */ 17806 insn = al ? jalr : jr; 17807 insn |= at << MICROMIPSOP_SH_MJ; 17808 17809 buf = write_compressed_insn (buf, insn, 2); 17810 } 17811 17812 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 17813 return; 17814 } 17815 17816 if (RELAX_MIPS16_P (fragp->fr_subtype)) 17817 { 17818 int type; 17819 const struct mips_int_operand *operand; 17820 offsetT val; 17821 char *buf; 17822 unsigned int user_length, length; 17823 unsigned long insn; 17824 bfd_boolean ext; 17825 segT symsec; 17826 17827 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 17828 operand = mips16_immed_operand (type, FALSE); 17829 17830 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); 17831 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; 17832 if (operand->root.type == OP_PCREL) 17833 { 17834 const struct mips_pcrel_operand *pcrel_op; 17835 addressT addr; 17836 17837 pcrel_op = (const struct mips_pcrel_operand *) operand; 17838 addr = fragp->fr_address + fragp->fr_fix; 17839 17840 /* The rules for the base address of a PC relative reloc are 17841 complicated; see mips16_extended_frag. */ 17842 if (pcrel_op->include_isa_bit) 17843 { 17844 addr += 2; 17845 if (ext) 17846 addr += 2; 17847 /* Ignore the low bit in the target, since it will be 17848 set for a text label. */ 17849 val &= -2; 17850 } 17851 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 17852 addr -= 4; 17853 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 17854 addr -= 2; 17855 17856 addr &= -(1 << pcrel_op->align_log2); 17857 val -= addr; 17858 17859 /* Make sure the section winds up with the alignment we have 17860 assumed. */ 17861 if (operand->shift > 0) 17862 record_alignment (asec, operand->shift); 17863 } 17864 17865 if (ext 17866 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) 17867 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) 17868 as_warn_where (fragp->fr_file, fragp->fr_line, 17869 _("extended instruction in delay slot")); 17870 17871 buf = fragp->fr_literal + fragp->fr_fix; 17872 17873 insn = read_compressed_insn (buf, 2); 17874 if (ext) 17875 insn |= MIPS16_EXTEND; 17876 17877 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 17878 user_length = 4; 17879 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 17880 user_length = 2; 17881 else 17882 user_length = 0; 17883 17884 symsec = S_GET_SEGMENT (fragp->fr_symbol); 17885 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) 17886 || (operand->root.type == OP_PCREL 17887 ? asec != symsec 17888 : !bfd_is_abs_section (symsec))) 17889 { 17890 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; 17891 expressionS exp; 17892 fixS *fixp; 17893 17894 switch (type) 17895 { 17896 case 'p': 17897 case 'q': 17898 reloc = BFD_RELOC_MIPS16_16_PCREL_S1; 17899 break; 17900 default: 17901 as_bad_where (fragp->fr_file, fragp->fr_line, 17902 _("unsupported relocation")); 17903 break; 17904 } 17905 if (reloc != BFD_RELOC_NONE) 17906 { 17907 gas_assert (ext); 17908 17909 exp.X_op = O_symbol; 17910 exp.X_add_symbol = fragp->fr_symbol; 17911 exp.X_add_number = fragp->fr_offset; 17912 17913 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, 17914 TRUE, reloc); 17915 17916 fixp->fx_file = fragp->fr_file; 17917 fixp->fx_line = fragp->fr_line; 17918 17919 /* These relocations can have an addend that won't fit 17920 in 2 octets. */ 17921 fixp->fx_no_overflow = 1; 17922 } 17923 } 17924 else 17925 mips16_immed (fragp->fr_file, fragp->fr_line, type, 17926 BFD_RELOC_UNUSED, val, user_length, &insn); 17927 17928 length = (ext ? 4 : 2); 17929 gas_assert (mips16_opcode_length (insn) == length); 17930 write_compressed_insn (buf, insn, length); 17931 fragp->fr_fix += length; 17932 } 17933 else 17934 { 17935 relax_substateT subtype = fragp->fr_subtype; 17936 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; 17937 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; 17938 int first, second; 17939 fixS *fixp; 17940 17941 first = RELAX_FIRST (subtype); 17942 second = RELAX_SECOND (subtype); 17943 fixp = (fixS *) fragp->fr_opcode; 17944 17945 /* If the delay slot chosen does not match the size of the instruction, 17946 then emit a warning. */ 17947 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) 17948 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) 17949 { 17950 relax_substateT s; 17951 const char *msg; 17952 17953 s = subtype & (RELAX_DELAY_SLOT_16BIT 17954 | RELAX_DELAY_SLOT_SIZE_FIRST 17955 | RELAX_DELAY_SLOT_SIZE_SECOND); 17956 msg = macro_warning (s); 17957 if (msg != NULL) 17958 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 17959 subtype &= ~s; 17960 } 17961 17962 /* Possibly emit a warning if we've chosen the longer option. */ 17963 if (use_second == second_longer) 17964 { 17965 relax_substateT s; 17966 const char *msg; 17967 17968 s = (subtype 17969 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); 17970 msg = macro_warning (s); 17971 if (msg != NULL) 17972 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 17973 subtype &= ~s; 17974 } 17975 17976 /* Go through all the fixups for the first sequence. Disable them 17977 (by marking them as done) if we're going to use the second 17978 sequence instead. */ 17979 while (fixp 17980 && fixp->fx_frag == fragp 17981 && fixp->fx_where < fragp->fr_fix - second) 17982 { 17983 if (subtype & RELAX_USE_SECOND) 17984 fixp->fx_done = 1; 17985 fixp = fixp->fx_next; 17986 } 17987 17988 /* Go through the fixups for the second sequence. Disable them if 17989 we're going to use the first sequence, otherwise adjust their 17990 addresses to account for the relaxation. */ 17991 while (fixp && fixp->fx_frag == fragp) 17992 { 17993 if (subtype & RELAX_USE_SECOND) 17994 fixp->fx_where -= first; 17995 else 17996 fixp->fx_done = 1; 17997 fixp = fixp->fx_next; 17998 } 17999 18000 /* Now modify the frag contents. */ 18001 if (subtype & RELAX_USE_SECOND) 18002 { 18003 char *start; 18004 18005 start = fragp->fr_literal + fragp->fr_fix - first - second; 18006 memmove (start, start + first, second); 18007 fragp->fr_fix -= first; 18008 } 18009 else 18010 fragp->fr_fix -= second; 18011 } 18012 } 18013 18014 /* This function is called after the relocs have been generated. 18015 We've been storing mips16 text labels as odd. Here we convert them 18016 back to even for the convenience of the debugger. */ 18017 18018 void 18019 mips_frob_file_after_relocs (void) 18020 { 18021 asymbol **syms; 18022 unsigned int count, i; 18023 18024 syms = bfd_get_outsymbols (stdoutput); 18025 count = bfd_get_symcount (stdoutput); 18026 for (i = 0; i < count; i++, syms++) 18027 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) 18028 && ((*syms)->value & 1) != 0) 18029 { 18030 (*syms)->value &= ~1; 18031 /* If the symbol has an odd size, it was probably computed 18032 incorrectly, so adjust that as well. */ 18033 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) 18034 ++elf_symbol (*syms)->internal_elf_sym.st_size; 18035 } 18036 } 18037 18038 /* This function is called whenever a label is defined, including fake 18039 labels instantiated off the dot special symbol. It is used when 18040 handling branch delays; if a branch has a label, we assume we cannot 18041 move it. This also bumps the value of the symbol by 1 in compressed 18042 code. */ 18043 18044 static void 18045 mips_record_label (symbolS *sym) 18046 { 18047 segment_info_type *si = seg_info (now_seg); 18048 struct insn_label_list *l; 18049 18050 if (free_insn_labels == NULL) 18051 l = XNEW (struct insn_label_list); 18052 else 18053 { 18054 l = free_insn_labels; 18055 free_insn_labels = l->next; 18056 } 18057 18058 l->label = sym; 18059 l->next = si->label_list; 18060 si->label_list = l; 18061 } 18062 18063 /* This function is called as tc_frob_label() whenever a label is defined 18064 and adds a DWARF-2 record we only want for true labels. */ 18065 18066 void 18067 mips_define_label (symbolS *sym) 18068 { 18069 mips_record_label (sym); 18070 dwarf2_emit_label (sym); 18071 } 18072 18073 /* This function is called by tc_new_dot_label whenever a new dot symbol 18074 is defined. */ 18075 18076 void 18077 mips_add_dot_label (symbolS *sym) 18078 { 18079 mips_record_label (sym); 18080 if (mips_assembling_insn && HAVE_CODE_COMPRESSION) 18081 mips_compressed_mark_label (sym); 18082 } 18083 18084 /* Converting ASE flags from internal to .MIPS.abiflags values. */ 18086 static unsigned int 18087 mips_convert_ase_flags (int ase) 18088 { 18089 unsigned int ext_ases = 0; 18090 18091 if (ase & ASE_DSP) 18092 ext_ases |= AFL_ASE_DSP; 18093 if (ase & ASE_DSPR2) 18094 ext_ases |= AFL_ASE_DSPR2; 18095 if (ase & ASE_DSPR3) 18096 ext_ases |= AFL_ASE_DSPR3; 18097 if (ase & ASE_EVA) 18098 ext_ases |= AFL_ASE_EVA; 18099 if (ase & ASE_MCU) 18100 ext_ases |= AFL_ASE_MCU; 18101 if (ase & ASE_MDMX) 18102 ext_ases |= AFL_ASE_MDMX; 18103 if (ase & ASE_MIPS3D) 18104 ext_ases |= AFL_ASE_MIPS3D; 18105 if (ase & ASE_MT) 18106 ext_ases |= AFL_ASE_MT; 18107 if (ase & ASE_SMARTMIPS) 18108 ext_ases |= AFL_ASE_SMARTMIPS; 18109 if (ase & ASE_VIRT) 18110 ext_ases |= AFL_ASE_VIRT; 18111 if (ase & ASE_MSA) 18112 ext_ases |= AFL_ASE_MSA; 18113 if (ase & ASE_XPA) 18114 ext_ases |= AFL_ASE_XPA; 18115 18116 return ext_ases; 18117 } 18118 /* Some special processing for a MIPS ELF file. */ 18119 18120 void 18121 mips_elf_final_processing (void) 18122 { 18123 int fpabi; 18124 Elf_Internal_ABIFlags_v0 flags; 18125 18126 flags.version = 0; 18127 flags.isa_rev = 0; 18128 switch (file_mips_opts.isa) 18129 { 18130 case INSN_ISA1: 18131 flags.isa_level = 1; 18132 break; 18133 case INSN_ISA2: 18134 flags.isa_level = 2; 18135 break; 18136 case INSN_ISA3: 18137 flags.isa_level = 3; 18138 break; 18139 case INSN_ISA4: 18140 flags.isa_level = 4; 18141 break; 18142 case INSN_ISA5: 18143 flags.isa_level = 5; 18144 break; 18145 case INSN_ISA32: 18146 flags.isa_level = 32; 18147 flags.isa_rev = 1; 18148 break; 18149 case INSN_ISA32R2: 18150 flags.isa_level = 32; 18151 flags.isa_rev = 2; 18152 break; 18153 case INSN_ISA32R3: 18154 flags.isa_level = 32; 18155 flags.isa_rev = 3; 18156 break; 18157 case INSN_ISA32R5: 18158 flags.isa_level = 32; 18159 flags.isa_rev = 5; 18160 break; 18161 case INSN_ISA32R6: 18162 flags.isa_level = 32; 18163 flags.isa_rev = 6; 18164 break; 18165 case INSN_ISA64: 18166 flags.isa_level = 64; 18167 flags.isa_rev = 1; 18168 break; 18169 case INSN_ISA64R2: 18170 flags.isa_level = 64; 18171 flags.isa_rev = 2; 18172 break; 18173 case INSN_ISA64R3: 18174 flags.isa_level = 64; 18175 flags.isa_rev = 3; 18176 break; 18177 case INSN_ISA64R5: 18178 flags.isa_level = 64; 18179 flags.isa_rev = 5; 18180 break; 18181 case INSN_ISA64R6: 18182 flags.isa_level = 64; 18183 flags.isa_rev = 6; 18184 break; 18185 } 18186 18187 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; 18188 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE 18189 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 18190 : (file_mips_opts.fp == 64) ? AFL_REG_64 18191 : AFL_REG_32; 18192 flags.cpr2_size = AFL_REG_NONE; 18193 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 18194 Tag_GNU_MIPS_ABI_FP); 18195 flags.isa_ext = bfd_mips_isa_ext (stdoutput); 18196 flags.ases = mips_convert_ase_flags (file_mips_opts.ase); 18197 if (file_ase_mips16) 18198 flags.ases |= AFL_ASE_MIPS16; 18199 if (file_ase_micromips) 18200 flags.ases |= AFL_ASE_MICROMIPS; 18201 flags.flags1 = 0; 18202 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) 18203 || file_mips_opts.fp == 64) 18204 && file_mips_opts.oddspreg) 18205 flags.flags1 |= AFL_FLAGS1_ODDSPREG; 18206 flags.flags2 = 0; 18207 18208 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, 18209 ((Elf_External_ABIFlags_v0 *) 18210 mips_flags_frag)); 18211 18212 /* Write out the register information. */ 18213 if (mips_abi != N64_ABI) 18214 { 18215 Elf32_RegInfo s; 18216 18217 s.ri_gprmask = mips_gprmask; 18218 s.ri_cprmask[0] = mips_cprmask[0]; 18219 s.ri_cprmask[1] = mips_cprmask[1]; 18220 s.ri_cprmask[2] = mips_cprmask[2]; 18221 s.ri_cprmask[3] = mips_cprmask[3]; 18222 /* The gp_value field is set by the MIPS ELF backend. */ 18223 18224 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, 18225 ((Elf32_External_RegInfo *) 18226 mips_regmask_frag)); 18227 } 18228 else 18229 { 18230 Elf64_Internal_RegInfo s; 18231 18232 s.ri_gprmask = mips_gprmask; 18233 s.ri_pad = 0; 18234 s.ri_cprmask[0] = mips_cprmask[0]; 18235 s.ri_cprmask[1] = mips_cprmask[1]; 18236 s.ri_cprmask[2] = mips_cprmask[2]; 18237 s.ri_cprmask[3] = mips_cprmask[3]; 18238 /* The gp_value field is set by the MIPS ELF backend. */ 18239 18240 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, 18241 ((Elf64_External_RegInfo *) 18242 mips_regmask_frag)); 18243 } 18244 18245 /* Set the MIPS ELF flag bits. FIXME: There should probably be some 18246 sort of BFD interface for this. */ 18247 if (mips_any_noreorder) 18248 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; 18249 if (mips_pic != NO_PIC) 18250 { 18251 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; 18252 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 18253 } 18254 if (mips_abicalls) 18255 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 18256 18257 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags 18258 defined at present; this might need to change in future. */ 18259 if (file_ase_mips16) 18260 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; 18261 if (file_ase_micromips) 18262 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; 18263 if (file_mips_opts.ase & ASE_MDMX) 18264 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; 18265 18266 /* Set the MIPS ELF ABI flags. */ 18267 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) 18268 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; 18269 else if (mips_abi == O64_ABI) 18270 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; 18271 else if (mips_abi == EABI_ABI) 18272 { 18273 if (file_mips_opts.gp == 64) 18274 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; 18275 else 18276 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; 18277 } 18278 else if (mips_abi == N32_ABI) 18279 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; 18280 18281 /* Nothing to do for N64_ABI. */ 18282 18283 if (mips_32bitmode) 18284 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; 18285 18286 if (mips_nan2008 == 1) 18287 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; 18288 18289 /* 32 bit code with 64 bit FP registers. */ 18290 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 18291 Tag_GNU_MIPS_ABI_FP); 18292 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) 18293 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; 18294 } 18295 18296 typedef struct proc { 18298 symbolS *func_sym; 18299 symbolS *func_end_sym; 18300 unsigned long reg_mask; 18301 unsigned long reg_offset; 18302 unsigned long fpreg_mask; 18303 unsigned long fpreg_offset; 18304 unsigned long frame_offset; 18305 unsigned long frame_reg; 18306 unsigned long pc_reg; 18307 } procS; 18308 18309 static procS cur_proc; 18310 static procS *cur_proc_ptr; 18311 static int numprocs; 18312 18313 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop 18314 as "2", and a normal nop as "0". */ 18315 18316 #define NOP_OPCODE_MIPS 0 18317 #define NOP_OPCODE_MIPS16 1 18318 #define NOP_OPCODE_MICROMIPS 2 18319 18320 char 18321 mips_nop_opcode (void) 18322 { 18323 if (seg_info (now_seg)->tc_segment_info_data.micromips) 18324 return NOP_OPCODE_MICROMIPS; 18325 else if (seg_info (now_seg)->tc_segment_info_data.mips16) 18326 return NOP_OPCODE_MIPS16; 18327 else 18328 return NOP_OPCODE_MIPS; 18329 } 18330 18331 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use 18332 32-bit microMIPS NOPs here (if applicable). */ 18333 18334 void 18335 mips_handle_align (fragS *fragp) 18336 { 18337 char nop_opcode; 18338 char *p; 18339 int bytes, size, excess; 18340 valueT opcode; 18341 18342 if (fragp->fr_type != rs_align_code) 18343 return; 18344 18345 p = fragp->fr_literal + fragp->fr_fix; 18346 nop_opcode = *p; 18347 switch (nop_opcode) 18348 { 18349 case NOP_OPCODE_MICROMIPS: 18350 opcode = micromips_nop32_insn.insn_opcode; 18351 size = 4; 18352 break; 18353 case NOP_OPCODE_MIPS16: 18354 opcode = mips16_nop_insn.insn_opcode; 18355 size = 2; 18356 break; 18357 case NOP_OPCODE_MIPS: 18358 default: 18359 opcode = nop_insn.insn_opcode; 18360 size = 4; 18361 break; 18362 } 18363 18364 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 18365 excess = bytes % size; 18366 18367 /* Handle the leading part if we're not inserting a whole number of 18368 instructions, and make it the end of the fixed part of the frag. 18369 Try to fit in a short microMIPS NOP if applicable and possible, 18370 and use zeroes otherwise. */ 18371 gas_assert (excess < 4); 18372 fragp->fr_fix += excess; 18373 switch (excess) 18374 { 18375 case 3: 18376 *p++ = '\0'; 18377 /* Fall through. */ 18378 case 2: 18379 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) 18380 { 18381 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); 18382 break; 18383 } 18384 *p++ = '\0'; 18385 /* Fall through. */ 18386 case 1: 18387 *p++ = '\0'; 18388 /* Fall through. */ 18389 case 0: 18390 break; 18391 } 18392 18393 md_number_to_chars (p, opcode, size); 18394 fragp->fr_var = size; 18395 } 18396 18397 static long 18398 get_number (void) 18399 { 18400 int negative = 0; 18401 long val = 0; 18402 18403 if (*input_line_pointer == '-') 18404 { 18405 ++input_line_pointer; 18406 negative = 1; 18407 } 18408 if (!ISDIGIT (*input_line_pointer)) 18409 as_bad (_("expected simple number")); 18410 if (input_line_pointer[0] == '0') 18411 { 18412 if (input_line_pointer[1] == 'x') 18413 { 18414 input_line_pointer += 2; 18415 while (ISXDIGIT (*input_line_pointer)) 18416 { 18417 val <<= 4; 18418 val |= hex_value (*input_line_pointer++); 18419 } 18420 return negative ? -val : val; 18421 } 18422 else 18423 { 18424 ++input_line_pointer; 18425 while (ISDIGIT (*input_line_pointer)) 18426 { 18427 val <<= 3; 18428 val |= *input_line_pointer++ - '0'; 18429 } 18430 return negative ? -val : val; 18431 } 18432 } 18433 if (!ISDIGIT (*input_line_pointer)) 18434 { 18435 printf (_(" *input_line_pointer == '%c' 0x%02x\n"), 18436 *input_line_pointer, *input_line_pointer); 18437 as_warn (_("invalid number")); 18438 return -1; 18439 } 18440 while (ISDIGIT (*input_line_pointer)) 18441 { 18442 val *= 10; 18443 val += *input_line_pointer++ - '0'; 18444 } 18445 return negative ? -val : val; 18446 } 18447 18448 /* The .file directive; just like the usual .file directive, but there 18449 is an initial number which is the ECOFF file index. In the non-ECOFF 18450 case .file implies DWARF-2. */ 18451 18452 static void 18453 s_mips_file (int x ATTRIBUTE_UNUSED) 18454 { 18455 static int first_file_directive = 0; 18456 18457 if (ECOFF_DEBUGGING) 18458 { 18459 get_number (); 18460 s_app_file (0); 18461 } 18462 else 18463 { 18464 char *filename; 18465 18466 filename = dwarf2_directive_file (0); 18467 18468 /* Versions of GCC up to 3.1 start files with a ".file" 18469 directive even for stabs output. Make sure that this 18470 ".file" is handled. Note that you need a version of GCC 18471 after 3.1 in order to support DWARF-2 on MIPS. */ 18472 if (filename != NULL && ! first_file_directive) 18473 { 18474 (void) new_logical_line (filename, -1); 18475 s_app_file_string (filename, 0); 18476 } 18477 first_file_directive = 1; 18478 } 18479 } 18480 18481 /* The .loc directive, implying DWARF-2. */ 18482 18483 static void 18484 s_mips_loc (int x ATTRIBUTE_UNUSED) 18485 { 18486 if (!ECOFF_DEBUGGING) 18487 dwarf2_directive_loc (0); 18488 } 18489 18490 /* The .end directive. */ 18491 18492 static void 18493 s_mips_end (int x ATTRIBUTE_UNUSED) 18494 { 18495 symbolS *p; 18496 18497 /* Following functions need their own .frame and .cprestore directives. */ 18498 mips_frame_reg_valid = 0; 18499 mips_cprestore_valid = 0; 18500 18501 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 18502 { 18503 p = get_symbol (); 18504 demand_empty_rest_of_line (); 18505 } 18506 else 18507 p = NULL; 18508 18509 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 18510 as_warn (_(".end not in text section")); 18511 18512 if (!cur_proc_ptr) 18513 { 18514 as_warn (_(".end directive without a preceding .ent directive")); 18515 demand_empty_rest_of_line (); 18516 return; 18517 } 18518 18519 if (p != NULL) 18520 { 18521 gas_assert (S_GET_NAME (p)); 18522 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) 18523 as_warn (_(".end symbol does not match .ent symbol")); 18524 18525 if (debug_type == DEBUG_STABS) 18526 stabs_generate_asm_endfunc (S_GET_NAME (p), 18527 S_GET_NAME (p)); 18528 } 18529 else 18530 as_warn (_(".end directive missing or unknown symbol")); 18531 18532 /* Create an expression to calculate the size of the function. */ 18533 if (p && cur_proc_ptr) 18534 { 18535 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); 18536 expressionS *exp = XNEW (expressionS); 18537 18538 obj->size = exp; 18539 exp->X_op = O_subtract; 18540 exp->X_add_symbol = symbol_temp_new_now (); 18541 exp->X_op_symbol = p; 18542 exp->X_add_number = 0; 18543 18544 cur_proc_ptr->func_end_sym = exp->X_add_symbol; 18545 } 18546 18547 /* Generate a .pdr section. */ 18548 if (!ECOFF_DEBUGGING && mips_flag_pdr) 18549 { 18550 segT saved_seg = now_seg; 18551 subsegT saved_subseg = now_subseg; 18552 expressionS exp; 18553 char *fragp; 18554 18555 #ifdef md_flush_pending_output 18556 md_flush_pending_output (); 18557 #endif 18558 18559 gas_assert (pdr_seg); 18560 subseg_set (pdr_seg, 0); 18561 18562 /* Write the symbol. */ 18563 exp.X_op = O_symbol; 18564 exp.X_add_symbol = p; 18565 exp.X_add_number = 0; 18566 emit_expr (&exp, 4); 18567 18568 fragp = frag_more (7 * 4); 18569 18570 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); 18571 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); 18572 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); 18573 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); 18574 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); 18575 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); 18576 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); 18577 18578 subseg_set (saved_seg, saved_subseg); 18579 } 18580 18581 cur_proc_ptr = NULL; 18582 } 18583 18584 /* The .aent and .ent directives. */ 18585 18586 static void 18587 s_mips_ent (int aent) 18588 { 18589 symbolS *symbolP; 18590 18591 symbolP = get_symbol (); 18592 if (*input_line_pointer == ',') 18593 ++input_line_pointer; 18594 SKIP_WHITESPACE (); 18595 if (ISDIGIT (*input_line_pointer) 18596 || *input_line_pointer == '-') 18597 get_number (); 18598 18599 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 18600 as_warn (_(".ent or .aent not in text section")); 18601 18602 if (!aent && cur_proc_ptr) 18603 as_warn (_("missing .end")); 18604 18605 if (!aent) 18606 { 18607 /* This function needs its own .frame and .cprestore directives. */ 18608 mips_frame_reg_valid = 0; 18609 mips_cprestore_valid = 0; 18610 18611 cur_proc_ptr = &cur_proc; 18612 memset (cur_proc_ptr, '\0', sizeof (procS)); 18613 18614 cur_proc_ptr->func_sym = symbolP; 18615 18616 ++numprocs; 18617 18618 if (debug_type == DEBUG_STABS) 18619 stabs_generate_asm_func (S_GET_NAME (symbolP), 18620 S_GET_NAME (symbolP)); 18621 } 18622 18623 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 18624 18625 demand_empty_rest_of_line (); 18626 } 18627 18628 /* The .frame directive. If the mdebug section is present (IRIX 5 native) 18629 then ecoff.c (ecoff_directive_frame) is used. For embedded targets, 18630 s_mips_frame is used so that we can set the PDR information correctly. 18631 We can't use the ecoff routines because they make reference to the ecoff 18632 symbol table (in the mdebug section). */ 18633 18634 static void 18635 s_mips_frame (int ignore ATTRIBUTE_UNUSED) 18636 { 18637 if (ECOFF_DEBUGGING) 18638 s_ignore (ignore); 18639 else 18640 { 18641 long val; 18642 18643 if (cur_proc_ptr == (procS *) NULL) 18644 { 18645 as_warn (_(".frame outside of .ent")); 18646 demand_empty_rest_of_line (); 18647 return; 18648 } 18649 18650 cur_proc_ptr->frame_reg = tc_get_register (1); 18651 18652 SKIP_WHITESPACE (); 18653 if (*input_line_pointer++ != ',' 18654 || get_absolute_expression_and_terminator (&val) != ',') 18655 { 18656 as_warn (_("bad .frame directive")); 18657 --input_line_pointer; 18658 demand_empty_rest_of_line (); 18659 return; 18660 } 18661 18662 cur_proc_ptr->frame_offset = val; 18663 cur_proc_ptr->pc_reg = tc_get_register (0); 18664 18665 demand_empty_rest_of_line (); 18666 } 18667 } 18668 18669 /* The .fmask and .mask directives. If the mdebug section is present 18670 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For 18671 embedded targets, s_mips_mask is used so that we can set the PDR 18672 information correctly. We can't use the ecoff routines because they 18673 make reference to the ecoff symbol table (in the mdebug section). */ 18674 18675 static void 18676 s_mips_mask (int reg_type) 18677 { 18678 if (ECOFF_DEBUGGING) 18679 s_ignore (reg_type); 18680 else 18681 { 18682 long mask, off; 18683 18684 if (cur_proc_ptr == (procS *) NULL) 18685 { 18686 as_warn (_(".mask/.fmask outside of .ent")); 18687 demand_empty_rest_of_line (); 18688 return; 18689 } 18690 18691 if (get_absolute_expression_and_terminator (&mask) != ',') 18692 { 18693 as_warn (_("bad .mask/.fmask directive")); 18694 --input_line_pointer; 18695 demand_empty_rest_of_line (); 18696 return; 18697 } 18698 18699 off = get_absolute_expression (); 18700 18701 if (reg_type == 'F') 18702 { 18703 cur_proc_ptr->fpreg_mask = mask; 18704 cur_proc_ptr->fpreg_offset = off; 18705 } 18706 else 18707 { 18708 cur_proc_ptr->reg_mask = mask; 18709 cur_proc_ptr->reg_offset = off; 18710 } 18711 18712 demand_empty_rest_of_line (); 18713 } 18714 } 18715 18716 /* A table describing all the processors gas knows about. Names are 18717 matched in the order listed. 18718 18719 To ease comparison, please keep this table in the same order as 18720 gcc's mips_cpu_info_table[]. */ 18721 static const struct mips_cpu_info mips_cpu_info_table[] = 18722 { 18723 /* Entries for generic ISAs */ 18724 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, 18725 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, 18726 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, 18727 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, 18728 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, 18729 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, 18730 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18731 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, 18732 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, 18733 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, 18734 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, 18735 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, 18736 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, 18737 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, 18738 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, 18739 18740 /* MIPS I */ 18741 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, 18742 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, 18743 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, 18744 18745 /* MIPS II */ 18746 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, 18747 18748 /* MIPS III */ 18749 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, 18750 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, 18751 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, 18752 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, 18753 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, 18754 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, 18755 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, 18756 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, 18757 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, 18758 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, 18759 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, 18760 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, 18761 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, 18762 /* ST Microelectronics Loongson 2E and 2F cores */ 18763 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, 18764 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, 18765 18766 /* MIPS IV */ 18767 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, 18768 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, 18769 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, 18770 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, 18771 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, 18772 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, 18773 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, 18774 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, 18775 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, 18776 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, 18777 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, 18778 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, 18779 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, 18780 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, 18781 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, 18782 18783 /* MIPS 32 */ 18784 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 18785 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 18786 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 18787 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, 18788 18789 /* MIPS 32 Release 2 */ 18790 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18791 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18792 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18793 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, 18794 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18795 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18796 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 18797 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 18798 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 18799 ISA_MIPS32R2, CPU_MIPS32R2 }, 18800 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 18801 ISA_MIPS32R2, CPU_MIPS32R2 }, 18802 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18803 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18804 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18805 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18806 /* Deprecated forms of the above. */ 18807 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18808 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18809 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ 18810 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18811 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18812 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18813 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18814 /* Deprecated forms of the above. */ 18815 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18816 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18817 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ 18818 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18819 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18820 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18821 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18822 /* Deprecated forms of the above. */ 18823 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18824 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18825 /* 34Kn is a 34kc without DSP. */ 18826 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18827 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ 18828 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18829 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18830 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18831 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18832 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18833 /* Deprecated forms of the above. */ 18834 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18835 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18836 /* 1004K cores are multiprocessor versions of the 34K. */ 18837 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18838 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18839 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18840 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18841 /* interaptiv is the new name for 1004kf */ 18842 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18843 /* M5100 family */ 18844 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, 18845 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, 18846 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ 18847 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, 18848 18849 /* MIPS 64 */ 18850 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 18851 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 18852 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 18853 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 18854 18855 /* Broadcom SB-1 CPU core */ 18856 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 18857 /* Broadcom SB-1A CPU core */ 18858 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 18859 18860 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, 18861 18862 /* MIPS 64 Release 2 */ 18863 18864 /* Cavium Networks Octeon CPU core */ 18865 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, 18866 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, 18867 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, 18868 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, 18869 18870 /* RMI Xlr */ 18871 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, 18872 18873 /* Broadcom XLP. 18874 XLP is mostly like XLR, with the prominent exception that it is 18875 MIPS64R2 rather than MIPS64. */ 18876 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, 18877 18878 /* MIPS 64 Release 6 */ 18879 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 18880 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 18881 18882 /* End marker */ 18883 { NULL, 0, 0, 0, 0 } 18884 }; 18885 18886 18887 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 18888 with a final "000" replaced by "k". Ignore case. 18889 18890 Note: this function is shared between GCC and GAS. */ 18891 18892 static bfd_boolean 18893 mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 18894 { 18895 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 18896 given++, canonical++; 18897 18898 return ((*given == 0 && *canonical == 0) 18899 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 18900 } 18901 18902 18903 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 18904 CPU name. We've traditionally allowed a lot of variation here. 18905 18906 Note: this function is shared between GCC and GAS. */ 18907 18908 static bfd_boolean 18909 mips_matching_cpu_name_p (const char *canonical, const char *given) 18910 { 18911 /* First see if the name matches exactly, or with a final "000" 18912 turned into "k". */ 18913 if (mips_strict_matching_cpu_name_p (canonical, given)) 18914 return TRUE; 18915 18916 /* If not, try comparing based on numerical designation alone. 18917 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 18918 if (TOLOWER (*given) == 'r') 18919 given++; 18920 if (!ISDIGIT (*given)) 18921 return FALSE; 18922 18923 /* Skip over some well-known prefixes in the canonical name, 18924 hoping to find a number there too. */ 18925 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 18926 canonical += 2; 18927 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 18928 canonical += 2; 18929 else if (TOLOWER (canonical[0]) == 'r') 18930 canonical += 1; 18931 18932 return mips_strict_matching_cpu_name_p (canonical, given); 18933 } 18934 18935 18936 /* Parse an option that takes the name of a processor as its argument. 18937 OPTION is the name of the option and CPU_STRING is the argument. 18938 Return the corresponding processor enumeration if the CPU_STRING is 18939 recognized, otherwise report an error and return null. 18940 18941 A similar function exists in GCC. */ 18942 18943 static const struct mips_cpu_info * 18944 mips_parse_cpu (const char *option, const char *cpu_string) 18945 { 18946 const struct mips_cpu_info *p; 18947 18948 /* 'from-abi' selects the most compatible architecture for the given 18949 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 18950 EABIs, we have to decide whether we're using the 32-bit or 64-bit 18951 version. Look first at the -mgp options, if given, otherwise base 18952 the choice on MIPS_DEFAULT_64BIT. 18953 18954 Treat NO_ABI like the EABIs. One reason to do this is that the 18955 plain 'mips' and 'mips64' configs have 'from-abi' as their default 18956 architecture. This code picks MIPS I for 'mips' and MIPS III for 18957 'mips64', just as we did in the days before 'from-abi'. */ 18958 if (strcasecmp (cpu_string, "from-abi") == 0) 18959 { 18960 if (ABI_NEEDS_32BIT_REGS (mips_abi)) 18961 return mips_cpu_info_from_isa (ISA_MIPS1); 18962 18963 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 18964 return mips_cpu_info_from_isa (ISA_MIPS3); 18965 18966 if (file_mips_opts.gp >= 0) 18967 return mips_cpu_info_from_isa (file_mips_opts.gp == 32 18968 ? ISA_MIPS1 : ISA_MIPS3); 18969 18970 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT 18971 ? ISA_MIPS3 18972 : ISA_MIPS1); 18973 } 18974 18975 /* 'default' has traditionally been a no-op. Probably not very useful. */ 18976 if (strcasecmp (cpu_string, "default") == 0) 18977 return 0; 18978 18979 for (p = mips_cpu_info_table; p->name != 0; p++) 18980 if (mips_matching_cpu_name_p (p->name, cpu_string)) 18981 return p; 18982 18983 as_bad (_("bad value (%s) for %s"), cpu_string, option); 18984 return 0; 18985 } 18986 18987 /* Return the canonical processor information for ISA (a member of the 18988 ISA_MIPS* enumeration). */ 18989 18990 static const struct mips_cpu_info * 18991 mips_cpu_info_from_isa (int isa) 18992 { 18993 int i; 18994 18995 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 18996 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) 18997 && isa == mips_cpu_info_table[i].isa) 18998 return (&mips_cpu_info_table[i]); 18999 19000 return NULL; 19001 } 19002 19003 static const struct mips_cpu_info * 19004 mips_cpu_info_from_arch (int arch) 19005 { 19006 int i; 19007 19008 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 19009 if (arch == mips_cpu_info_table[i].cpu) 19010 return (&mips_cpu_info_table[i]); 19011 19012 return NULL; 19013 } 19014 19015 static void 19017 show (FILE *stream, const char *string, int *col_p, int *first_p) 19018 { 19019 if (*first_p) 19020 { 19021 fprintf (stream, "%24s", ""); 19022 *col_p = 24; 19023 } 19024 else 19025 { 19026 fprintf (stream, ", "); 19027 *col_p += 2; 19028 } 19029 19030 if (*col_p + strlen (string) > 72) 19031 { 19032 fprintf (stream, "\n%24s", ""); 19033 *col_p = 24; 19034 } 19035 19036 fprintf (stream, "%s", string); 19037 *col_p += strlen (string); 19038 19039 *first_p = 0; 19040 } 19041 19042 void 19043 md_show_usage (FILE *stream) 19044 { 19045 int column, first; 19046 size_t i; 19047 19048 fprintf (stream, _("\ 19049 MIPS options:\n\ 19050 -EB generate big endian output\n\ 19051 -EL generate little endian output\n\ 19052 -g, -g2 do not remove unneeded NOPs or swap branches\n\ 19053 -G NUM allow referencing objects up to NUM bytes\n\ 19054 implicitly with the gp register [default 8]\n")); 19055 fprintf (stream, _("\ 19056 -mips1 generate MIPS ISA I instructions\n\ 19057 -mips2 generate MIPS ISA II instructions\n\ 19058 -mips3 generate MIPS ISA III instructions\n\ 19059 -mips4 generate MIPS ISA IV instructions\n\ 19060 -mips5 generate MIPS ISA V instructions\n\ 19061 -mips32 generate MIPS32 ISA instructions\n\ 19062 -mips32r2 generate MIPS32 release 2 ISA instructions\n\ 19063 -mips32r3 generate MIPS32 release 3 ISA instructions\n\ 19064 -mips32r5 generate MIPS32 release 5 ISA instructions\n\ 19065 -mips32r6 generate MIPS32 release 6 ISA instructions\n\ 19066 -mips64 generate MIPS64 ISA instructions\n\ 19067 -mips64r2 generate MIPS64 release 2 ISA instructions\n\ 19068 -mips64r3 generate MIPS64 release 3 ISA instructions\n\ 19069 -mips64r5 generate MIPS64 release 5 ISA instructions\n\ 19070 -mips64r6 generate MIPS64 release 6 ISA instructions\n\ 19071 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); 19072 19073 first = 1; 19074 19075 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 19076 show (stream, mips_cpu_info_table[i].name, &column, &first); 19077 show (stream, "from-abi", &column, &first); 19078 fputc ('\n', stream); 19079 19080 fprintf (stream, _("\ 19081 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ 19082 -no-mCPU don't generate code specific to CPU.\n\ 19083 For -mCPU and -no-mCPU, CPU must be one of:\n")); 19084 19085 first = 1; 19086 19087 show (stream, "3900", &column, &first); 19088 show (stream, "4010", &column, &first); 19089 show (stream, "4100", &column, &first); 19090 show (stream, "4650", &column, &first); 19091 fputc ('\n', stream); 19092 19093 fprintf (stream, _("\ 19094 -mips16 generate mips16 instructions\n\ 19095 -no-mips16 do not generate mips16 instructions\n")); 19096 fprintf (stream, _("\ 19097 -mmicromips generate microMIPS instructions\n\ 19098 -mno-micromips do not generate microMIPS instructions\n")); 19099 fprintf (stream, _("\ 19100 -msmartmips generate smartmips instructions\n\ 19101 -mno-smartmips do not generate smartmips instructions\n")); 19102 fprintf (stream, _("\ 19103 -mdsp generate DSP instructions\n\ 19104 -mno-dsp do not generate DSP instructions\n")); 19105 fprintf (stream, _("\ 19106 -mdspr2 generate DSP R2 instructions\n\ 19107 -mno-dspr2 do not generate DSP R2 instructions\n")); 19108 fprintf (stream, _("\ 19109 -mdspr3 generate DSP R3 instructions\n\ 19110 -mno-dspr3 do not generate DSP R3 instructions\n")); 19111 fprintf (stream, _("\ 19112 -mmt generate MT instructions\n\ 19113 -mno-mt do not generate MT instructions\n")); 19114 fprintf (stream, _("\ 19115 -mmcu generate MCU instructions\n\ 19116 -mno-mcu do not generate MCU instructions\n")); 19117 fprintf (stream, _("\ 19118 -mmsa generate MSA instructions\n\ 19119 -mno-msa do not generate MSA instructions\n")); 19120 fprintf (stream, _("\ 19121 -mxpa generate eXtended Physical Address (XPA) instructions\n\ 19122 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); 19123 fprintf (stream, _("\ 19124 -mvirt generate Virtualization instructions\n\ 19125 -mno-virt do not generate Virtualization instructions\n")); 19126 fprintf (stream, _("\ 19127 -minsn32 only generate 32-bit microMIPS instructions\n\ 19128 -mno-insn32 generate all microMIPS instructions\n")); 19129 fprintf (stream, _("\ 19130 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ 19131 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ 19132 -mfix-vr4120 work around certain VR4120 errata\n\ 19133 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ 19134 -mfix-24k insert a nop after ERET and DERET instructions\n\ 19135 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ 19136 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ 19137 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ 19138 -msym32 assume all symbols have 32-bit values\n\ 19139 -O0 remove unneeded NOPs, do not swap branches\n\ 19140 -O remove unneeded NOPs and swap branches\n\ 19141 --trap, --no-break trap exception on div by 0 and mult overflow\n\ 19142 --break, --no-trap break exception on div by 0 and mult overflow\n")); 19143 fprintf (stream, _("\ 19144 -mhard-float allow floating-point instructions\n\ 19145 -msoft-float do not allow floating-point instructions\n\ 19146 -msingle-float only allow 32-bit floating-point operations\n\ 19147 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ 19148 --[no-]construct-floats [dis]allow floating point values to be constructed\n\ 19149 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ 19150 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); 19151 19152 first = 1; 19153 19154 show (stream, "legacy", &column, &first); 19155 show (stream, "2008", &column, &first); 19156 19157 fputc ('\n', stream); 19158 19159 fprintf (stream, _("\ 19160 -KPIC, -call_shared generate SVR4 position independent code\n\ 19161 -call_nonpic generate non-PIC code that can operate with DSOs\n\ 19162 -mvxworks-pic generate VxWorks position independent code\n\ 19163 -non_shared do not generate code that can operate with DSOs\n\ 19164 -xgot assume a 32 bit GOT\n\ 19165 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ 19166 -mshared, -mno-shared disable/enable .cpload optimization for\n\ 19167 position dependent (non shared) code\n\ 19168 -mabi=ABI create ABI conformant object file for:\n")); 19169 19170 first = 1; 19171 19172 show (stream, "32", &column, &first); 19173 show (stream, "o64", &column, &first); 19174 show (stream, "n32", &column, &first); 19175 show (stream, "64", &column, &first); 19176 show (stream, "eabi", &column, &first); 19177 19178 fputc ('\n', stream); 19179 19180 fprintf (stream, _("\ 19181 -32 create o32 ABI object file (default)\n\ 19182 -n32 create n32 ABI object file\n\ 19183 -64 create 64 ABI object file\n")); 19184 } 19185 19186 #ifdef TE_IRIX 19187 enum dwarf2_format 19188 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) 19189 { 19190 if (HAVE_64BIT_SYMBOLS) 19191 return dwarf2_format_64bit_irix; 19192 else 19193 return dwarf2_format_32bit; 19194 } 19195 #endif 19196 19197 int 19198 mips_dwarf2_addr_size (void) 19199 { 19200 if (HAVE_64BIT_OBJECTS) 19201 return 8; 19202 else 19203 return 4; 19204 } 19205 19206 /* Standard calling conventions leave the CFA at SP on entry. */ 19207 void 19208 mips_cfi_frame_initial_instructions (void) 19209 { 19210 cfi_add_CFA_def_cfa_register (SP); 19211 } 19212 19213 int 19214 tc_mips_regname_to_dw2regnum (char *regname) 19215 { 19216 unsigned int regnum = -1; 19217 unsigned int reg; 19218 19219 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) 19220 regnum = reg; 19221 19222 return regnum; 19223 } 19224 19225 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. 19226 Given a symbolic attribute NAME, return the proper integer value. 19227 Returns -1 if the attribute is not known. */ 19228 19229 int 19230 mips_convert_symbolic_attribute (const char *name) 19231 { 19232 static const struct 19233 { 19234 const char * name; 19235 const int tag; 19236 } 19237 attribute_table[] = 19238 { 19239 #define T(tag) {#tag, tag} 19240 T (Tag_GNU_MIPS_ABI_FP), 19241 T (Tag_GNU_MIPS_ABI_MSA), 19242 #undef T 19243 }; 19244 unsigned int i; 19245 19246 if (name == NULL) 19247 return -1; 19248 19249 for (i = 0; i < ARRAY_SIZE (attribute_table); i++) 19250 if (streq (name, attribute_table[i].name)) 19251 return attribute_table[i].tag; 19252 19253 return -1; 19254 } 19255 19256 void 19257 md_mips_end (void) 19258 { 19259 int fpabi = Val_GNU_MIPS_ABI_FP_ANY; 19260 19261 mips_emit_delays (); 19262 if (cur_proc_ptr) 19263 as_warn (_("missing .end at end of assembly")); 19264 19265 /* Just in case no code was emitted, do the consistency check. */ 19266 file_mips_check_options (); 19267 19268 /* Set a floating-point ABI if the user did not. */ 19269 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) 19270 { 19271 /* Perform consistency checks on the floating-point ABI. */ 19272 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19273 Tag_GNU_MIPS_ABI_FP); 19274 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) 19275 check_fpabi (fpabi); 19276 } 19277 else 19278 { 19279 /* Soft-float gets precedence over single-float, the two options should 19280 not be used together so this should not matter. */ 19281 if (file_mips_opts.soft_float == 1) 19282 fpabi = Val_GNU_MIPS_ABI_FP_SOFT; 19283 /* Single-float gets precedence over all double_float cases. */ 19284 else if (file_mips_opts.single_float == 1) 19285 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; 19286 else 19287 { 19288 switch (file_mips_opts.fp) 19289 { 19290 case 32: 19291 if (file_mips_opts.gp == 32) 19292 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 19293 break; 19294 case 0: 19295 fpabi = Val_GNU_MIPS_ABI_FP_XX; 19296 break; 19297 case 64: 19298 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) 19299 fpabi = Val_GNU_MIPS_ABI_FP_64A; 19300 else if (file_mips_opts.gp == 32) 19301 fpabi = Val_GNU_MIPS_ABI_FP_64; 19302 else 19303 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 19304 break; 19305 } 19306 } 19307 19308 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19309 Tag_GNU_MIPS_ABI_FP, fpabi); 19310 } 19311 } 19312 19313 /* Returns the relocation type required for a particular CFI encoding. */ 19314 19315 bfd_reloc_code_real_type 19316 mips_cfi_reloc_for_encoding (int encoding) 19317 { 19318 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) 19319 return BFD_RELOC_32_PCREL; 19320 else return BFD_RELOC_NONE; 19321 } 19322
