| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/cr16/ |
| pop_test.s | 5 # pop uimm3 regr RA
7 pop $1,r7,RA
8 pop $2,r6,RA
9 pop $3,r5,RA
10 pop $4,r4,RA
11 pop $5,r3,RA
12 pop $6,r2,RA
13 pop $7,r1,RA
25 # pop RA
27 pop RA
[all...] |
| popret_test.s | 5 # popret uimm3 regr RA
7 popret $1,r7,RA
8 popret $2,r6,RA
9 popret $3,r5,RA
10 popret $4,r4,RA
11 popret $5,r3,RA
12 popret $6,r2,RA
13 popret $7,r1,RA
25 # popret RA
27 popret RA
[all...] |
| push_test.s | 5 # push uimm3 regr RA
7 push $1,r7,RA
8 push $2,r6,RA
9 push $3,r5,RA
10 push $4,r4,RA
11 push $5,r3,RA
12 push $6,r2,RA
13 push $7,r1,RA
14 #push $6,r12,RA
15 #push $7,r13,RA
[all...] |
| push_test.d | 10 0: 87 01 push \$0x1,r7,RA
11 2: 96 01 push \$0x2,r6,RA
12 4: a5 01 push \$0x3,r5,RA
13 6: b4 01 push \$0x4,r4,RA
14 8: c3 01 push \$0x5,r3,RA
15 a: d2 01 push \$0x6,r2,RA
16 c: e1 01 push \$0x7,r1,RA
25 1e: 1e 01 push RA
26 20: 1e 01 push RA
|
| pop_test.d | 10 0: 87 02 pop \$0x1,r7,RA
11 2: 96 02 pop \$0x2,r6,RA
12 4: a5 02 pop \$0x3,r5,RA
13 6: b4 02 pop \$0x4,r4,RA
14 8: c3 02 pop \$0x5,r3,RA
15 a: d2 02 pop \$0x6,r2,RA
16 c: e1 02 pop \$0x7,r1,RA
24 1c: 1e 02 pop RA
|
| popret_test.d | 10 0: 87 03 popret \$0x1,r7,RA
11 2: 96 03 popret \$0x2,r6,RA
12 4: a5 03 popret \$0x3,r5,RA
13 6: b4 03 popret \$0x4,r4,RA
14 8: c3 03 popret \$0x5,r3,RA
15 a: d2 03 popret \$0x6,r2,RA
16 c: e1 03 popret \$0x7,r1,RA
24 1c: 1e 03 popret RA
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
| instructions.h | 9 #define __COPY(RA, RB, L) \
10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
11 #define COPY(RA, RB, L) \
12 .long __COPY((RA), (RB), (L))
33 #define __PASTE(RA, RB, L, RC) \
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
35 #define PASTE(RA, RB, L, RC) \
36 .long __PASTE((RA), (RB), (L), (RC))
|
| /external/valgrind/none/tests/ppc32/ |
| opcodes.h | 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES
[all...] |
| /external/valgrind/none/tests/ppc64/ |
| opcodes.h | 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/ia64/ |
| forward.s | 6 RA == rA
7 rA = r2
15 dep.z RA = one, two + 3, three + 4
20 rA = r3
25 dep.z RA = one, two + 3, three + 4
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRDF.cpp | 19 bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const {
20 if (RA == RB)
23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) &&
26 if (RA.Reg == RB.Reg) {
27 if (RA.Sub == 0)
34 return RegisterAliasInfo::covers(RA, RB);
|
| RDFDeadCode.cpp | 77 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) {
78 if (!LiveNodes.count(RA.Id))
79 WorkQ.push_back(RA.Id);
124 auto RA = DFG.addr<RefNode*>(N);
125 if (DFG.IsDef(RA))
126 processDef(RA, WorkQ);
128 processUse(RA, WorkQ);
134 auto RA = DFG.addr<RefNode*>(N);
135 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n";
148 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)
[all...] |
| HexagonRDF.h | 21 bool covers(RegisterRef RA, RegisterRef RR) const override;
|
| /external/clang/test/Layout/ |
| ms-x86-alias-avoidance-padding.cpp | 301 struct RA {};
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
326 // CHECK-NEXT: 1 | struct RA (base) (empty
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| arc-nps400-tbl.h | 53 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
56 { "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { 0 }},
59 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
74 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }},
77 { "rflt", 0x3e2e7f80, 0xffffffc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { 0 }},
80 { "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }},
86 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
89 { "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }},
92 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
107 { "crc16", 0x38330f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { C_NPS_R }}
[all...] |
| or1k-opc.c | 281 /* l.mfspr $rD,$rA,${uimm16} */
284 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } },
287 /* l.mtspr $rA,$rB,${uimm16-split} */
290 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
293 /* l.lwz $rD,${simm16}($rA) */
296 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
299 /* l.lws $rD,${simm16}($rA) */
302 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
305 /* l.lwa $rD,${simm16}($rA) */
308 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }
[all...] |
| ppc-opc.c | 511 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
512 #define RA NSISIGNOPT + 1
516 /* As above, but 0 in the RA field means zero, not r0. */
517 #define RA0 RA + 1
520 /* The RA field in the DQ form lq or an lswx instruction, which have special
526 /* The RA field in a D or X form instruction which is an updating
527 load, which means that the RA field may not be zero and may not
532 /* The RA field in an lmw instruction, which has special value
537 /* The RA field in a D or X form instruction which is an updating
538 store or an updating floating point load, which means that the RA
[all...] |
| arc-tbl.h | 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
104 { "acm", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
113 { "acm", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
116 { "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
122 { "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
131 { "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
143 { "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
146 { "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
161 { "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
173 { "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}
[all...] |
| /external/linux-kselftest/tools/testing/selftests/powerpc/context_switch/ |
| cp_abort.c | 36 #define PASTE(RA, RB, L, RC) \
37 .long (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
53 #define COPY(RA, RB, L) \
54 .long (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
|
| /external/llvm/lib/Target/ |
| TargetSubtargetInfo.cpp | 24 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
26 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
|
| /external/llvm/include/llvm/Transforms/IPO/ |
| DeadArgumentElimination.h | 122 void MarkValue(const RetOrArg &RA, Liveness L,
124 void MarkLive(const RetOrArg &RA);
126 void PropagateLiveness(const RetOrArg &RA);
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Transforms/IPO/ |
| DeadArgumentElimination.h | 122 void MarkValue(const RetOrArg &RA, Liveness L,
124 void MarkLive(const RetOrArg &RA);
126 void PropagateLiveness(const RetOrArg &RA);
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/Transforms/IPO/ |
| DeadArgumentElimination.h | 122 void MarkValue(const RetOrArg &RA, Liveness L,
124 void MarkLive(const RetOrArg &RA);
126 void PropagateLiveness(const RetOrArg &RA);
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/Transforms/IPO/ |
| DeadArgumentElimination.h | 122 void MarkValue(const RetOrArg &RA, Liveness L,
124 void MarkLive(const RetOrArg &RA);
126 void PropagateLiveness(const RetOrArg &RA);
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/Transforms/IPO/ |
| DeadArgumentElimination.h | 132 void MarkValue(const RetOrArg &RA, Liveness L,
134 void MarkLive(const RetOrArg &RA);
136 void PropagateLiveness(const RetOrArg &RA);
|
