1 #ifndef OPCODES_H 2 #define OPCODES_H 3 4 /* (Along the lines of ../s390x/opcodes.h) Macro definitions to hand-assemble 5 * instructions known to cause problems with assemblers or across assembler 6 * versions. 7 * 8 * Notes: 9 * 10 * 0. Offsets used in encodings are in Valgrind (Right to Left) ordering. 11 * 1. Use register numbers, not register names in macro invocations. 12 * 2. Insert the definitions for a new instruction/instruction format in 13 * the order of the appearance of its definition in the Power ISA. 14 */ 15 16 /* Instruction formats: 17 */ 18 19 /* Power ISA Version 2.07 (May 3, 2013). pp. 15: X-FORM */ 20 #define X20_ASM_DIRECTIVE ".long" 21 #define X20_OPCODE_OFFSET "26" 22 #define X20_TH_OFFSET "21" 23 #define X20_RA_OFFSET "16" 24 #define X20_RB_OFFSET "11" 25 #define X20_XO_OFFSET "1" 26 #define X20_RES_OFFSET "0" 27 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ 29 X20_ASM_DIRECTIVE " " \ 30 "(" #OPCODE "<<" X20_OPCODE_OFFSET ")" "+" \ 31 "(" #TH "<<" X20_TH_OFFSET ")" "+" \ 32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \ 33 "(" #RB "<<" X20_RB_OFFSET ")" "+" \ 34 "(" #XO "<<" X20_XO_OFFSET ")" "+" \ 35 "(" #RES "<<" X20_RES_OFFSET ")" 36 37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) 38 39 /* Instruction specifics: 40 */ 41 42 /* Power ISA Version 2.07 (May 3, 2013). pp. 770: dcbt (Category: Server Syntax) */ 43 #define DCBT_OPCODE 31 44 #define DCBT_XO 278 45 #define DCBT_RES 0 46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES) 47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH)) 48 49 /* Power ISA Version 2.07 (May 3, 2013). pp. 771: dcbtst (Category: Server Syntax) */ 50 #define DCBTST_OPCODE 31 51 #define DCBTST_XO 246 52 #define DCBTST_RES 0 53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES) 54 #define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH)) 55 56 #endif /* OPCODES_H */ 57
