| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_gs_nir.cpp | 67 nir_const_value *offset_reg = nir_src_as_const_value(instr->src[1]); local
71 instr->const_index[0] + offset_reg->u32[0],
89 instr->const_index[0] + offset_reg->u32[0],
|
| brw_vec4_nir.cpp | 529 src_reg offset_reg; local
532 offset_reg = brw_imm_ud(const_offset->u32[0]);
534 offset_reg = get_nir_src(instr->src[2], 1);
630 if (offset_reg.file == IMM) {
631 offset_reg.ud += 4 * skipped_channels;
633 emit(ADD(dst_reg(offset_reg), offset_reg,
644 emit_untyped_write(bld, surf_index, offset_reg, val_reg,
694 src_reg offset_reg; local
697 offset_reg = brw_imm_ud(const_offset->u32[0])
906 src_reg offset_reg; local
919 offset_reg, local
926 surf_index, offset_reg, NULL, NULL); local
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| metag-dis.c | 528 const char *offset_reg; local
533 offset_reg = lookup_reg_name (base_unit, offset_no);
538 snprintf (buf, buf_size, "[%s+%s++]", base_reg, offset_reg);
540 snprintf (buf, buf_size, "[%s++%s]", base_reg, offset_reg);
543 snprintf (buf, buf_size, "[%s+%s]", base_reg, offset_reg);
2402 const char *offset_reg = lookup_reg_name (addr_unit, offset_part); local
[all...] |
| /art/compiler/optimizing/ |
| code_generator_arm64.cc | 2627 Register offset_reg = InputRegisterAt(instruction, 1); local
2628 __ Add(OutputRegister(instruction), offset_reg, Operand(index_reg, LSL, shift)); local
[all...] |
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_shader.c | 1469 int offset_reg = vtx_id \/ 3; local
[all...] |
| /toolchain/binutils/binutils-2.27/gas/config/ |
| tc-metag.c | 187 const metag_reg *offset_reg; member in struct:__anon4320
742 addr->offset_reg = regs[0];
1121 insn->bits |= (addr.offset_reg->no << 9);
[all...] |
| tc-tic6x.c | 1427 tic6x_register offset_reg; local
[all...] |
